NXP Semiconductors Document Number: MC33660

Technical Data Rev 6.0, 7/2016

ISO K line serial link interface

The 33660 is a serial link bus interface device designed to provide bi-directional
33660
half-duplex communication interfacing in automotive diagnostic applications. It
is designed to interface between the vehicle’s on-board microcontroller, and
systems off-board the vehicle via the special ISO K line. The 33660 is designed
to meet the Diagnostic Systems ISO9141 specification. The device’s K line bus ISO9141 PHYSICAL INTERFACE
driver’s output is fully protected against bus shorts and over-temperature
conditions.
The 33660 derives its robustness to temperature and voltage extremes by being
built on a SMARTMOS process, incorporating CMOS logic, bipolar/MOS analog
circuitry, and DMOS power FETs. Although the 33660 was principally designed
for automotive applications, it is suited for other serial communication
applications. It is parametrically specified over an ambient temperature range of
-40 ºC ≤ TA ≤ 125 ºC and 8.0 V ≤ VBB ≤ 18 V supply. The economical SO-8 EF SUFFIX (PB-FREE)
surface-mount plastic package makes the 33660 very cost effective. 98ASB42564B
Features 8-PIN SOICN
• Operates over a wide supply voltage of 8.0 V to 18 V
• Operating temperature of -40 °C to 125 °C Applications
• Interfaces directly to standard CMOS microprocessors • Farm equipment
• ISO K line pin protected against shorts to battery • Automotive systems
• Thermal shutdown with hysteresis • Industrial equipment
• ISO K line pin capable of high currents • Robotic equipment
• ISO K line can be driven with up to 10 nF of parasitic capacitance • Applications where module-to-module
• 8.0 kV ESD protection attainable with few additional components communications are required
• Standby mode: no VBAT current drain with VDD at 5.0 V • Marine and aircraft networks
• Low current drain during operation with VDD at 5.0 V

+VBAT

VDD

33660
VDD VDD VBB

MCU
ISO K-LINE
Dx CEN ISO
SCIRxD RX TXD
SCITxD TX
GND
RXD

Figure 1. 33660 simplified application diagram

© 2016 NXP B.V.

1 Orderable parts

Table 1. Orderable part variations

Temperature
Part number (1) Package Parameter Symbol Condition 33660 33660B (2)
(TA)

VBB(5a) Pulse 5a – 82 V
VBB Load Dump 470 ohm series resistor and
Peak Voltage (in 100 nF capacitor to GND on VBB
MC33660EF accordance with
ISO 7637-2 & ISO Pulse 5b
-40 °C to VBB(5b) 470 ohm series resistor and 45 V 45 V
8-SOICN 7637-3)
125 °C 100 nF capacitor to GND on VBB
Module Level ESD
33 V zener diode and 470 pF
MC33660BEF (Air Discharge, VESD4 – ±25000 V
capacitor to GND on ISO
Powered)

Notes
1. To order parts in tape & reel, add the R2 suffix to the part number.
2. Recommended for all new designs

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2 Internal block diagram

VBB * Only applies to 33660B

60 V 3.0 kΩ 20 V
600 kΩ

CEN
10 V
125 kΩ RX
RHYS
10 V

55 kΩ
550 kΩ
ISO

45 V

Master
Bias 110 kΩ

55 V
Thermal
VDD Shutdown
2.0 kΩ
10 V
125 kΩ

TX

10 V

GND

Figure 2. 33660 simplified internal block diagram

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3 Pin connections

3.1 Pinout diagram

VBB 11 88 CEN
NC 22 77 VDD
GND 33 66 RX
ISO 44 55 TX

Figure 3. 33660 pin connections

3.2 Pin definitions

Table 2. 33660 pin definitions

Pin Number Pin Name Definition
1 VBB Battery power through external resistor and diode.
2 NC Not to be connected. (3)
3 GND Common signal and power return.
4 ISO Bus connection.
5 TX Logic level input for data to be transmitted on the bus.
6 RX Logic output of data received on the bus.
7 VDD Logic power source input.
8 CEN Chip enable. Logic “1” for active state. Logic “0” for sleep state.

Notes
3. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits.

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4 Electrical characteristics

4.1 Maximum ratings

Table 3. Maximum ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol Rating Value Unit Notes

VDD VDD DC Supply Voltage -0.3 to 7.0 V

VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO
7637-3)
V
VBB(5a) • Pulse 5a - 33660B only 82
VBB(5b) • Pulse 5b 45
VISO ISO Pin Load Dump Peak Voltage 40 V (4)

(5)
ESD Voltage (6)
VESD1 ±2000
• Human Body Model (6)
VESD2
• Machine Model
±150
33660
±200
33660B
VESD3-1 • Charge Device Model ±750 V (6)

VESD3-2 Corner Pins ±500

All other Pins
• Module Level ESD (Air Discharge, Powered)
VESD4 ±25000 (7)
33660B only
ISO pin with 33 V zener diode and 470 pF capacitor to GND -

(8)
ECLAMP ISO Clamp Energy 10 mJ
TSTG Storage Temperature -55 to +150 °C
TC Operating Case Temperature -40 to +125 °C
TJ Operating Junction Temperature -40 to +150 °C
PD Power Dissipation TA = 25 °C 100 mW
TPPRT Peak Package Reflow Temperature During Reflow Note 10. °C (9), (10)

RθJA Thermal Resistance: Junction-to-Ambient 150 °C/W

Notes
4. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain within
specified parametric limits during this duration.
5. ESD data available upon request.
6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance
with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), ESD3 testing is performed in accordance with the Charge Device Model (CZAP = 4.0 pF).
7. ESD4 testing is performed in accordance with ISO 10605 ESD model (C = 330 pF, R = 2.0 kΩ). ESD discharges start at ±5.0 kV and go up to
±25 kV in increments of 5.0 kV. There are two positions for discharges: 8.0 cm cable from ISO connector, 85 cm cable from ISO connector. There
are 10 ESD discharges per voltage at each cable position at a minimum of 1.0 s intervals. Remaining charge is not bled off after every discharge.
8. Nonrepetitive clamping capability at 25 °C.
9. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
10. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature
and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to
view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

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4.2 Static electrical characteristics

Table 4. Static electrical characteristics

Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes

Power and control

VDD Sleep State Current
IDD(SS) – – 0.1 mA
• Tx = 0.8 VDD, CEN = 0.3 VDD

VDD Quiescent Operating Current

IDD(Q) – – 1.0 mA
• Tx = 0.2 VDD, CEN = 0.7 VDD

VBB Sleep State Current

IBB(SS) – – 50 µA
• VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD

VBB Quiescent Operating Current

IBB(Q) – – 1.0 mA
• TX = 0.2 VDD, CEN = 0.7 VDD

Chip Enable
(11)
VIH(CEN) • Input High Voltage Threshold 0.7 VDD – – V
(12)
VIL(CEN) • Input Low Voltage Threshold – – 0.3 VDD
(13)
IPD(CEN) Chip Enable Pull-down Current 2.0 – 40 µA
TX Input Low Voltage Threshold (14)
VIL(TX) – – 0.3 x VDD V
• RISO = 510 Ω

TX Input High Voltage Threshold (15)

VIH(TX) 0.7 x VDD – – V
• RISO = 510 Ω
(16)
IPU(TX) TX Pull-up Current -40 – -2.0 µA
RX Output Low Voltage Threshold
VOL(RX) – – 0.2 VDD V
• RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA

RX Output High Voltage Threshold

VOH(RX) 0.8 VDD – – V
• RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA
(17)
TLIM Thermal Shutdown 150 170 – °C

ISO I/O
Input Low Voltage Threshold
VIL(ISO) – – 0.4 x VBB V
• RISO = 510 Ω, TX = 0.8 VDD

Input High Voltage Threshold

VIH(ISO) 0.7 x VBB – – V
• RISO = 510 Ω, TX = 0.8 VDD

VHYS(ISO) Input Voltage Hysteresis 0.05 x VBB – 0.1 x VBB V

Internal Pull-up Current
IPU(ISO) -5.0 – -140 µA
• RISO = ∞ Ω, TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V

Short-circuit Current Limit

ISC(ISO) 50 – 200 mA
• RISO = 0 Ω, TX = 0.4 VDD, VISO = VBB

Notes
11. When IBB transitions to >100 µA.
12. When IBB transitions to <100 µA.
13. Enable pin has an internal current pull-down. Pull-down current is measured with CEN pin at 0.3 VDD.
14. Measured by ramping TX down from 0.8 VDD and noting TX value at which ISO falls below 0.2 VBB.
15. Measured by ramping TX up from 0.2 VDD and noting the value at which ISO rises above 0.9 VBB.
16. Tx pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD.
17. Thermal Shutdown performance (TLIM) is guaranteed by design, but not production tested.

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Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes

ISO I/O (Continued)

Output Low Voltage
VOL(ISO) – – 0.1 x VBB V
• RISO = 510 Ω, TX = 0.2 VDD

Output High Voltage

VOH(ISO) 0.95 x VBB – – V
• RISO = ∞ Ω, TX = 0.8 VDD

4.3 Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics

Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes

Fall Time (18)

tFALL(ISO) – – 2.0 µs
• RISO = 510 Ω to VBB, CISO = 10 nF to Ground

ISO Propagation Delay (19)

tPD(ISO) • High to Low: RISO = 510 Ω, CISO = 500 pF – – 2.0 µs (20)

(21)
• Low to High: RISO = 510 Ω, CISO = 500 pF – – 2.0

Notes
18. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB.
19. Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay.
20. Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIH(Tx) until VISO reaches 0.3 VBB.
21. Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIL(Tx) until VISO reaches 0.7 VBB.

4.4 Electrical performance curves

VIL and VIH, INPUT THRESHOLD (RATIO)

0.6
VIH; VDD = 5.25 V, VBB =
0.575 18 V
VIH; VDD = 4.75 V, VBB =
8.0 V
0.55

0.525

VIL; VDD = 5.25 V, VBB =

0.5 18 V
VIL; VDD = 4.75 V, VBB =
0.475 8.0 V
-50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C)

Figure 4. ISO input threshold/VBB vs. temperature

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NXP Semiconductors 7
 0.95

tfall(ISO), ISO FALL TIME (µs)

0.9
VDD = 5.25 V, VBB = 18 V
0.85

0.8

0.75
VDD = 4.75 V, VBB = 8.0 V
0.7

0.65
-50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C)

Figure 5. ISO output/VBB vs. temperature

1.2
VOL and VOH, ISO OUTPUT (RATIO)

VOH
1.0

0.8
VDD = 4.75 V, VBB = 8.0 V
0.6
and
VDD = 5.25 V, VBB = 18 V
0.4

0.2
VOL
0
-50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C)

Figure 6. ISO fall time vs. temperature

0.7
tPD(ISO), PROPAGATION DELAY (µs)

VDD = 5.25 V, VBB = 18 V

PdH-L
0.6
VDD = 4.75 V, VBB = 8.0 V

0.5

0.4

0.3
VDD = 5.25 V, VBB = 18 V PdL-H
VDD = 4.75 V, VBB = 8.0 V
0.2
-50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C)

Figure 7. ISO propagation delay vs. temperature

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5 Typical applications

5.1 Introduction
The 33660 is a serial link bus interface device conforming to the ISO 9141 physical bus specification. The device is designed for
automotive environment usage, compliant with On-board Diagnostics (OBD) requirements set forth by the California Air Resources Board
(CARB) using the ISO K line. The device does not incorporate an ISO L line. It provides bi-directional half-duplex communications
interfacing from a microcontroller to the communication bus. The 33660 incorporates circuitry to interface the digital translations from 5.0 V
microcontroller logic levels to battery level logic, and from battery level logic to 5.0 V logic levels. The 33660 is built using Freescale
Semiconductor’s SMARTMOS process and is packaged in an 8-pin plastic SOIC.

5.2 Functional description

The 33660 transforms 5.0 V microcontroller logic signals to battery level logic signals and vice versa. The maximum data rate is set by
the rise and fall time. The fall time is set by the output driver. The rise time is set by the bus capacitance and the pull-up resistors on the
bus. The fall time of the 33660 allows data rates up to 150 kbps using a 30 percent maximum bit time transition value. The serial link
interface remains fully functional over a battery voltage range of 6.0 V to 18 V. The device is parametrically specified over a dynamic VBB
voltage range of 8.0 V to 18 V.
Required input levels from the microcontroller are ratio-metric with the VDD voltage normally used to power the microcontroller. This
enhances the 33660’s ability to remain in harmony with the RX and TX control input signals of the microcontroller. The RX and TX control
inputs are compatible with standard 5.0 V CMOS circuitry. For fault tolerant purposes the TX input from the microcontroller has an internal
passive pull-up to VDD, while the CEN input has an internal passive pull-down to ground.
A pull-up to battery is internally provided as well as an active data pull-down. The internal active pull-down is current-limit protected against
shorts to battery, and further protected by thermal shutdown. Typical applications have reverse battery protection by the incorporation of
an external 510 Ω pull-up resistor and a diode to battery.
Reverse battery protection of the device is provided by the use of a reverse battery blocking diode (See “D” in the Typical application
diagram on page 9). Battery line transient protection of the device is provided for by using a 45 V zener and a 500 Ω resistor connected
to the VBB source, as shown in the same diagram. Device ESD protection from the communication lines exiting the module is through the
use of the capacitor connected to the VBB device pin, and the capacitor used in conjunction with the 27 V zener connected to the ISO pin.

On-Board Diagnostic Link +VBAT

Service Scan Tool
or
45 V(2) End of Production Line
D(1)
Programming
+VDD = 5.0 V or
33660 500 Ω(2)
MCU System Checking
VBB
10 nF(3)
VCC VDD
1.0 nF 510 Ω TxD

Dx CEN ISO
ISO Rx D
SCIRxD RX 5.0 nF(3) 27 V(3)
K Line
SCITxD TX GND

Components necessary for Reverse Battery (1), Overvoltage Transient (2), and 8.0 kV
ESD Protection (3) in a metal module case.

Figure 8. Typical application diagram

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NXP Semiconductors 9
6 Packaging

6.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.NXP.com and
perform a keyword search for the drawing’s document number.

Package Suffix Package outline drawing number

8-Pin SOICN EF 98ASB42564B

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10 NXP Semiconductors
 33660

NXP Semiconductors 11
7 Revision history

Revision Date Description of changes

1.0 1/2011 • Initial release

2.0 9/2011 • Adjusted format to meet current compliance standards. No data was altered.
3.0 10/2011 • Updated the PC part number to MC.
• Added PC33660BEF to the ordering information
• Redefined VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO 7637-3) for the 33660B
4.0 2/2013 • Added Module Level ESD (Air Discharge, Powered) for the 33660B
• Added note (7)
• Increased ESD structure voltage for 33660B, and added bleed-off circuit on VBB pin in Figure 2
5.0 10/2013 • Clarified machine model limits for MC33660 and MC33660B, page 5
• Changed document classification to Technical Data
1/2016
6.0 • Updated format and style
7/2016 • Updated to NXP document form and style

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12 NXP Semiconductors
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Document Number: MC33660

Rev 6.0
7/2016