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Noise Margins For The CMOS Inverter: - Noise Margin Related To K - When K 1, NM NM 0.93 V (Better Than NMOS)

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Kumar

The document discusses CMOS logic gates including NOR gates, NAND gates, and inverters. It describes how to size the PMOS and NMOS transistors in these gates to achieve symmetrical delay. Dynamic responses, capacitances, propagation delay, and power dissipation of CMOS logic gates are also covered.

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Noise Margins For The CMOS Inverter: - Noise Margin Related To K - When K 1, NM NM 0.93 V (Better Than NMOS)

Uploaded by

Kumar
50 views16 pages
The document discusses CMOS logic gates including NOR gates, NAND gates, and inverters. It describes how to size the PMOS and NMOS transistors in these gates to achieve symmetrical delay. Dynamic responses, capacitances, propagation delay, and power dissipation of CMOS logic gates are also covered.

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Lecture 29

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The document discusses CMOS logic gates including NOR gates, NAND gates, and inverters. It describes how to size the PMOS and NMOS transistors in these gates to achieve symmetrical delay. Dynamic responses, capacitances, propagation delay, and power dissipation of CMOS logic gates are also covered.

Copyright:

© All Rights Reserved
Download as PDF, TXT or read online from Scribd
Download as pdf or txt
50 views16 pages

Noise Margins For The CMOS Inverter: - Noise Margin Related To K - When K 1, NM NM 0.93 V (Better Than NMOS)

Uploaded by

Kumar
The document discusses CMOS logic gates including NOR gates, NAND gates, and inverters. It describes how to size the PMOS and NMOS transistors in these gates to achieve symmetrical delay. Dynamic responses, capacitances, propagation delay, and power dissipation of CMOS logic gates are also covered.

Copyright:

© All Rights Reserved
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You are on page 1/ 16

Noise 

Margins for the CMOS Inverter

• Noise margin related to KR
• When KR = 1, NMH = NML = 0.93 V (better than NMOS)
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
CMOS NOR Gate

CMOS NOR gate Reference Inverter
• In general, a parallel path in the NMOS network 
corresponds to a series path in the PMOS network.
• CMOS NOR Gate: parallel NMOS, series PMOS.
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
CMOS NOR Gate Sizing
• When sizing the transistors, the Ron on the 
PMOS branch of the NOR gate must be the 
same as the reference inverter (to keep the 
delay times equal under the worst‐case 
conditions)

• For a two‐input NOR gate, the (W/L)p must be 
made twice as large 

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


Three‐Input NOR Gate Layout
• It is possible to extend this same design technique to 
create multiple input NOR gates

Three‐input CMOS NOR gate: 
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
CMOS NAND Gates

Reference Inverter
CMOS NAND gate
• In general, a series path in the NMOS network corresponds 
to a parallel path in the PMOS network.
• CMOS NAND Gate: series NMOS, parallel PMOS.
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
CMOS NAND Gates Sizing
• The same rules apply for sizing the NAND gate 
as the did for the NOR gate, except for now 
the NMOS transistors are in series

• The (W/L)N will be twice the size of the 
reference inverter’s NMOS

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


Multi‐Input CMOS NAND Gates

Five‐input CMOS NAND gate: 

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


Capacitances in Logic Circuits

The capacitances on a given 
node can be lumped into a fixed 
Various capacitances  effective nodal capacitance C
associated with transistors

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


Logic Gate Dynamic Responses
• Rise time (tr): time required 
from 10% point to 90% point
• Fall time (tf): time required 
from 90% point to 10% point 
• Propagation delay (τP):
difference in time between 
the input and output signals 
reaching the 50% points
– for output high‐to‐low:  τPHL
– for output low‐to‐high:  τPLH
– average propagation delay τP = 
(τPLH + τPHL)/2

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


Dynamic Response of 
CMOS Inverter
• Assume abrupt VI change 
from VL to VH
• VO changes from VH to VL
by discharging C via MN
• Same as the resistive load
1.2
1

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


Dynamic Response of 
CMOS Inverter
• Assume abrupt VI
change from VH to VL
• VO changes from VL to VH
by charging C via MP
• Similarly we get
1.2
1

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


CMOS Inverter with Symmetrical Delay
• CMS inverter with symmetrical delay has 

• This is exactly the “symmetrical” inverter
2.5 ⇒ 2.5

1.2
2

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


CMOS Switching Speed

• Can estimate switching time for capacitive load very simply:
∆ ∆
∆

• For τPHL, vI=VDD, PMOS OFF, NMOS ON.
• NMOS saturated for vO > VDD‐VTN, linear for vO < VDD‐VTN
• Just the opposite for LH transition.

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


Symmetrical CMOS Inverter
• Symmetrical CMOS inverter:


• If 

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


CMOS Performance Scaling
•
– ∝
– ∝ ∝

• Delay is proportional to total load capacitance 
C, and inversely proportional to W/L. 
• Larger size (larger W/L) => shorter delay

EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham


Power Dissipation
• Switching: CVDD2 per cycle
• Transition conduction: when VTN < vin < VDD+VTP, 
both transistors are on.
– Depends on amount of time
with vin ~ VDD/2 (tr , tf).
– Can be 20‐30% of CVDD2 

• Subthreshold conduction: small currents even 
when devices are “off.”
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham

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