248 CHAPTER FET Biasing 6.1 INTRODUCTION * In Chapter 5 we found that the biasing levels for a si cl be obtained using the characteristic equations Vag = 0.7 V, Ic = Bln, and le= hp ‘The linkage between input and output variables is provided by 8, which is assumed be fixed in magnitude for the analysis to be performed. ‘The fact that beta is a cons establishes a /inear relationship between Ic and Ip, Doubling the value of Iy double the level of fe, and so on. For the field-effect transistor the relationship between input and output quanti is nonlinear due to the squared term in Shockley’s equation, Linear relations result in straight lines when plotted on a graph of one variable versus the other, i nonlinear functions result in curves as obtained for the transfer characteristics JFET. The nonlinear relationship between J, and Vis can complicate the mat cal approach to the de analysis of FET configurations. A graphical approach my limit solutions to tenths place accuracy but it is a quicker method for most FE amplifiers. Since the graphical approach is in general the most popular the analysis this chapter will have a graphical orientation rather than direct mathematical te niques. Another distinct difference between the analysis of BJT and FET transistors ith the input controlling variable for a BJT transistor is a current level, while for the FE a voltage is the controlling variable. In both cases, however, the controlled vat on the output side is a current level that also defines the important voltage levels the output circuit The general relationships that can be applied to the de analys ers are 1g=0A and. Ip For JFETS and depletion-type MOSFETs Shockley’s equation is applied to rel the input and output quantities:sment-type MOSFET the following equation is applicable: (6.4) ularly important to realize that all of the equations above are for the only! They do not change with each network configuration so long as the isin the active region. The network simply defines the level of current and * associated with the operating point through its own set of equations. In reality ion of BJT and FET networks is the solution of simultaneous equations by the device and network. The solution can be determined using a mathe- for graphical approach—a fact to be demonstrated by the first few networks to d. However, as noted earlier, the graphical approach is the most popular FET networks and is employed in this book. first few sections of this chapter are limited to JFETs and the graphical coach to analysis. The depletion-type MOSFET will then be examined with its ed range of operating points followed by the enhancement-type MOSFET. , problems of a design nature are investigated to fully test the concepts and eedures introduced in the chapter. FIXED-BIAS CONFIGURATION e simplest of biasing arrangements for the n-channel JFET appears in Fig. 6.1 dito as the fixed-bias configuration, it is one of the few FET configurations ‘either method. The configuration of Fig. 6.1 includes the ac levels V; and V;, and the coupling “capacitors (C; and C2). Recall that the coupling capacitors are ‘“open circuits” for the deanalysis and low impedances (essentially short circuits) for the ac analysis. The ‘esistor Re is present to ensure that V; appears at the input to the FET amplifier for the ac analysis (Chapter 9). For the de analysis, ig=0A iGRa = (0 A)Rg = OV and Ve, Figure 6.1 Fixed-bias configu: The zero-volt drop across Re permits replacing Re by a short-circuit equivalent, as appearing in the network of Fig. 6.2 specifically redrawn for the de analysis. 6.2. Fixed-Bias Configuration Figure 6.2 Network for de analysis, 249250 ‘The fact that the negative terminal of the battery is connected directly to the defined positive potential of Vgs clearly reveals that the polarity of Vcs is direelly opposite to Vag. Applying Kirchhoff’s voltage law in the clockwise direction of the indicated loop of Fig. 6.2 will result in een and (6.5) Since Vag is a fixed de supply the voltage Vas is fixed in magnitude, resulting in the notation “‘fixed-bias configuration. ”* ‘The resulting level of drain current /1 is now controlled by Shockley’s equation: Ip = loss(1- Since Vos is a fixed quantity for this configuration its magnitude and sign can simply be substituted into Shockley’s equation and the resulting level of fp caleu- lated. This is one of the few instances in which a mathematical solution to a FET configuration is quite direct. A graphical analysis would require a plot of Shockley’s equation as shown in Fig. 6.3. Recall that choosing Ves = Vp/2 will result in a drain current of [ps4 when plotting the equation. For the analysis of this chapter the three points de- fined by Ipss, Vp, and the intersection just deseribed will be sufficient for plot- ting the curve. Ip (ma) Ios Loss 4 Me ve 0 Vos Figure 6.3. Plotting Shockley’. 2 equation In Fig. 6.4 the fixed level of Ves has been superimposed as a vertical line at Ves = —Vac- At any point on the vertical line the level of Vgs is —Vgg—the level of I must simply be determined on this vertical line. The point where the Ip (ma) oss Device Network 4 Q-point (olution) ™~, ToT, Figure 6.4 Finding the solution ° Yes for the fixed-bias configuration Chapter 6 FET Biasingcurves intersect is the common solution to the configuration—commonly re- to.as the quiescent or operating point. The subscript Q will be applied to in current and gate-to-source voltage to identify their levels.at the O-point. We in Fig. 6.4 that the quiescent level of Jp is determined by drawing a hori- line from the Q-point to the vertical Jp axis as shown in Fig. 6.4. It is portant to realize that once the network of Fig. 6.1 is constructed and operat the de levels of fp and Vs that will be measured by the meters of Fig. 6.5 the quiescent values defined by Fig. 6.4 Voltmeter Black lead Figure 6.5 Measuring the qui- = escent values of Ip and Ves, The drain-to-source voltage of the output section can be determined by applying Kirchhoff's voltage law as follows: +Vps + InRp — Von = 0 and Vos = Vow ~ IpRn (6.6) Recall that single-subscript voltages refer to the voltage at a point with respect to ground. For the configuration of Fig. 6.2, Vs=0V (6.7) Using double-subscript notation: Vos = Vp — Vs or Vp = Vos + Vs = Vos tO V and Vp = Vos (6.8) In addition, HEN or Vg = Ves + Vs= Vos + 0 V and Ve = Ves 6.9) The fact that Vp = Vps and Ve = Ves is fairly obvious from the fact that Vs = OY, but the derivations above were included to emphasize the relationship that exists between double-subscript and single-subscript notation. Since the configuration re- quites two de supplies, its use is limited and will not be included in the forthcoming list of the most common FET configurations. 6.2. Fixed-Bias Configuration 251EXAMPLE 6.1 Determine the following for the network of bare @ Ves, (b) rg 16 (c) Vps- (d) Vo, fe) Ve. (f) Vs. = Figure 6.6 Example 6.1 Solution: “Mathematical Approach: -2V 2 2 (b) Ip, = Iose(1 = a) =10 ma(1 - =) = 10 mA(I — 0.25)? = 10 mA@.75)? = 10 mA(0.5625) = 5.625 mA Vip ~ IpRp = 16 V ~ (5.625 mA)(2 kA) 6 V - 11.25 V=4.75V @ Vo = Vps = 4.75 V (©) Vo =Ves=-2¥ () Vs=0V Graphical Approach: The resulting Shockley curve and the vertical line at Ves = ~2 V are provided in Fig, 6.7. It is certainly difficult to read beyond the second place: (©) Vos Ip (mA) Iss = 10mA Figure 6.7 Graphical solution for the network of Fig. 6.6. Chapter 6 FET Biasing“vilhou significantly increasing the size of the figure but a solution of 5.6 mA from the gph of Fig, 6.7 is quite acceptable. Therefore, for part (a), -2V Vos, = —Vao (b) fo, = 5.6 mA (©) Vos = Von — InRp = 16 V — (5.6 mA)(2 kQ) =16V-11.2V=48V @ Yp=Vs=4.8V fn Vc = Vas = —2.V, ) V=0V The results clearly confirm the fact that the mathematical and graphical approach generate solutions that are quite close. ——— 63 SELF-BIAS CONFIGURATION The self-bias configuration eliminates the need for two de supplies. The controlling gate-o-source voltage is now determined by the voltage across a resistor Rs intro- deed in the source leg of the configuration as shown in Fig. 6.8. Yoo Figure 6.8. JFET self-bias con- figuration, For the de analysis the capacitors can again be replaced by “‘open circuits’ and the resistor Rg replaced by a short-circuit equivalent since J = 0 A. The result is the network of Fig. 6.9 for the important de analysis. The current through Ry is the source current Is, but Js = Ip and Vi, = Ios For the indicated closed loop of Fig. 6.9, we find that Vos ~ Va, = 0 and or (6.10) Note in this case that Vgs is a function of the output current /p and not fixed in magnitude as occurred for the fixed-bias configuration. 6.3. Self-Bias Configuration Figure 6.9 DC analysis of the sell-bias configuration. 253254 Equation (6.10) is defined by the network configuration, and Shockley’s equatir relates the input and output quantities of the device. Both equations relate the same two variables, permitting a mathematical or graphical solution ‘A mathematical solution could be obtained simply by substituting Eq. (6.10) in Shockley’s equation as shown below: _ (, _ =o. =r ‘ad IpR: or ies = ose 1 : es) By performing the squaring proces: the following form can be obtained: Th+ Klp + Kx =0 icated and rearranging terms, an equation of ‘The quadratic equation can then be solved for the appropriate solution for Ip The sequence above defines the mathematical approach. The graphical approach requires that we first establish the device transfer characteristics as shown in Fig, 6.10. Since Eq. (6.10) defines a straight line on the same graph, let us now identify two points on the graph that are on the line and simply draw a straight line between the two points, The most obvious condition to apply is Zp = 0A since it results in Ves = —IpRs = (0 A)Rs = 0 V. For Eq. (6.10), therefore, one point on the straight line is defined by Ip = 0 A and Ves = 0 V, as appearing on Fig. 6.10 I Toss Figure 6.10 Defining a point fon the sel-bias Tine The second point for Eq. (6.10) requires that a level of Ves or Ip be chosen and the corresponding level of the other quantity be determined using Eq. (6.10). The resulting levels of Ip and Vs will then define another point on the straight line and permit an actual drawing of the straight line. Suppose, for example, that we choose @ level of J» equal to one-half the saturation level. That is, — Losses 2 ‘The result is a second point for the straight-line plot as shown in Fig. 6.11. The straight line as defined by Eq. (6.10) is then drawn and the quiescent point obtained at then Vos = =ipRs = Chapter 6 FET BiasingFigure 6.11 Sketching the self 2 bias line intersection of the straight line plot and the device characteristic curve. The jiescent values of ) and Vgs can then be determined and used to find the other ties of interest. The level of Vps can be determined by applying Kirchhoff's voltage law to the uiput circuit, with the result that Vr, + Vos + Ve, — Vop = 0 cand Vps = Von — Vr, — Va, = Yoo ~ Iss — InRp ‘but In = Is and ‘Vos = Vip — to(Rs + Ro) (6.11) In addition: Vs = IRs (6.12) Vg =0'V (6.13) and Vp = Vos + Vs = Vip — Va, (6.14) Determine the following for the network of Fig. 6.12. EXAMPLE 6.2 @) Ves, (6) In, (c) Vps. (@ Vs. (0) Vo. (f) Vo. Figure 6.12 Example 62 63. Self-Bias Configuration 255256 Solution (a) The gate-to-source voltage is determined by Vas = ~IpRs Choosing Jp = 4 mA, we obtain Ves = —4 mA)(1 kQ) = —4-V The result is the plot of Fig. 6.13 as defined by the network. 1, (mA) Figure 6.13 Sketching the bias line for the network of Fig 612 If we happen to choose /p = 8 mA, the resulting value of Ves would be ~8 V, shown on the same graph, In either case the same straight line will result, cle demonstrating that any appropriate value of / can be chosen as long as the c sponding value of Vs as determined by Eq. (6.10) is employed. In addition, keep mind that the value of Vizs could be chosen and the value of /p calculated with same resulting plot For Shockley’s equation if we choose Ves = Vpl2 = —3 V, we find that Ip Ipssi4 = 8 mA/4 = 2 mA, and the plot of Fig. 6.14 will result, representing characteristics of the device. The solution is obtained by superimposing the netwo characteristics defined by Fig. 6.13 on the device characteristics of Fig. 6.14 a finding the point of intersection of the two as indicated on Fig. 6.15. The result operating point results in a quiescent value of gate-to-source voltage of Sh Se eesears Ves) (Ve) ve @) Figure 6.14. Sketching the device charac- Figure 6.15 Determining the Q point forthe teristics for the JFET of Fig. 6.12. network of Fig. 6.12. Chapter 6 FET Biasing(b) Ar the quiescent point: Ip, = 2.6 mA 71) By. (6.11): Vos = Vow ~ Lo(Rs + Ro) 20 V — (2.6 mA)(I KO + 3.3 KO) 20V- 11.18 V 8.82 V (a) Eq. (6.12): Vs = IpRs = (2.6 mA)(1 kQ) =2.6V ~ (e) Eq. (6.13): Vo=0V D Eq. (6.14): Vp = Vos + Vs = 8.82 V + 2.6 V = 11.42 V or Vp = Vo ~ InRp = 20 V — (2.6 mA)(3.3 kM) = 11.42 V bk nt point for the network of Fig. 6.12 if: EXAMPLE 6.3 Solution Note Fig. 6.16. 1p =4MA, Vos =-04V @-point 0K 4 Vilp=04 mA fasy=—4.6V Figure 6.16 Example 63 {@) With the /p scale, Ip, = 6.4 mA From Eq. (6.10), {b) With the Vgs scale, Vos, = 74.6 V From Eq. (6.10), Ip, = 0.46 mA In particular, note how lower levels of Rs bring the load ine of the network closer to the fp axis, while increasing levels of Ry bring the load line closer to the Ves axis. 63 Self-Bias Configuration 257EXAMPLE 6.4 Rv Figure 6.18 Sketching the de ‘equivalent of the network of Fig. 6.7. 258 Determine the following for the network of Fig. 6.17. (@) Ves, (b) Ip,. nv © Vo. @) Vo. (©) Vs (f) Vos. Figure 6.17 Example 6+ Solution ‘The grounded gate terminal and the location of the input establish strong similarities with the common-base BJT amplifier. Although different in appearance from th basic structure of Fig. 6.8, the resulting de network of Fig. 6.18 has the same basie structure as Fig. 6.9. The de analysis can therefore proceed in the same manner & recent examples. (a) The transfer characteristics and load line appear in Fig. 6.19. In this case the second point for the sketch of the load line was determined by choosing (arbitrar ily) Ip = 6 mA and solving for Ves. That is, Ves = IpRs = —(6 mA)(680 0) = —4.08 V as shown in Fig. 6.19. The device transfer curve was sketched using fp Se ea iA 4 4 Jy (ma) 12 Ipss n 10 Figure 6.19 Determining the Q point lor the network of Fi 67, Chapter 6 FET BiasingVos, = -2.6 V ‘and the associated value of Vgs: Vp 6V fre Se Bacal eta Ge aio 4 shown on Fig. 6.19. Using the resulting quiescent point of Fig. 6.19 results in (b) From Fig. 6.19, Ip, =3.8 mA (0) Vb = Vin — In =12 V - G.8 mA)(1.S kQ) = 12 V-5.7V . =6.3V (a) Ve=0V (@) Vs = IpRs = (3.8 mA)(680 0) 2.58 V (®) Vos = Vo — Vs 3V — 2.58 V 3.72'V 64 VOLTAGE-DIVIDER BIASING The voltage-divider bias arrangement applied to BIT transistor amplifiers is also applied to FET amplifiers as demonstrated by Fig. 6.20. The basic construction is exactly the same, but the de analysis of each is quite different. fq =0 A for FET amplifiers, but the magnitude of /p for common-emitter BJT amplifiers can affect the de levels of current and voltage in both the input and output circuits. Recall that J provided the link between input and output circuits for the BIT voltage-divider con- figuration while Ves will do the same for the FET configuration. The network of Fig. 6.20 is redrawn as shown in Fig. 6.21 for the de analysis, Note that all the capacitors, including the bypass capacitor C's, have been replaced by an “open-circuit” equivalent. In addition, the source Viyp was separated into two Yop us Yo <= * Re Figure 6.20 Voltage-divider bias arrangement. Figure 6.21 Redrawn network of Fig, 6.20 for de an: 6.4 Voltage-Divider Biasing260 equivalent sources to permit a further separation of the input and output regions of| network. Since Iq = 0A, Kirchhoff's current law requires that Je, = Je, and series equivalent circuit appearing to the left of the figure can be used to find the le of Vo. The voltage Vi, equal to the voltage across Ro, can be found using the voll divider rule as follows: (6.15) Applying Kirchhoff’s voltage law in the clockwise direction to the indicated loop of Fig. 6.21 will result in VG Wars Vin: and. Vas = Va — Vr, Substituting Va, = IsRs = IpRs, we have (6.16) The result is an equation that continues to include the same two variables appear ing in Shockley’s equation: Ves and Jp. The quantities Vc; and Rs are fixed by the network construction. Equation (6.16) is still the equation for a straight line, but the origin is no longer a point in the plotting of the line. The procedure for plotting Eq. (6.16) is not a difficult one and will proceed as follows. Since any straight line requires two points to be defined, let us first use the fact that anywhere on the horizonal axis of Fig. 6.22 the current Ip = 0 mA. If we therefore select Ip to be 0 mA, we are in essence stating that we are somewhere on the horizontal axis. The exact location can be determined simply by substituting /) = 0 mA into Eq. (6.16) and finding the resulting value of Vgs as follows: Vas = Va — IRs Vo — (0 mA)Rs and. Vos = Vals ~ 0 The result specifies that whenever we plot Eq. (6.16), if we choose fp = 0 mA, the value of Ves for the plot will be Vg volts. The point just determined appears in Fig 6.22. Vos =0V. Ip = VoiRs Vas Vo~tpRs ee ia Ve 0 We Ves Figure 6.22 Sketching the network equation for che voltage-divider configuration. Chapter 6 FET BiasingFor the other point let us now employ the fact that at any point on the vertical axis Ves =0 V and solve for the resulting value of Ip: Vas = Ve — IoRs and (6.18) The result specifies that whenever we plot Eq. (6.16) if Ves = 0 V, the level of fp is tktermined by Eq. (6.18). This intersection also appears on Fig. 6.22. ‘The two points defined above permit the drawing of a straight line to represent Ey, (6,16). The intersection of the straight line with the transfer curve in the region to the left of the vertical axis will define the operating point and the corresponding levels af Ip and Ves. Since the intersection on the vertical axis is determined by Ip = Vo!Rs and Ve; is fixed by the input network, increasing values of Rs will reduce the level of the J, intersection as shown in Fig. 6.23. It is fairly obvious from Fig. 6.23 that: Increasing values of Rs result in-lower quiescent values of Ip and more nega- tive values of Ves Figure 6.23. Elfect of R; on the resulting Q point. Once the quiescent values of fp, and Vos, are determined, the remaining network analysis can be performed in the usual manner. That is, Vos = Vow = In(Ro + Rs) (6.19) Vp = Vow = foRp (6.20) Vs = IpRs (6.21) Vo hai re, = Ir, Rik (6.22) 6.4 Voltage-Divider Biasing 261EXAMPLE 6.5 Determine the following for the network of Fig. (a) Ip, and Ves, (b) Vp. (©) Vs. (@) Vos (©) Vos. Figure 6.24 Example 6.5 Solution (a) For the transfer characteristics, if Ip = Inss/4 = 8 mA/4 = 2 mA, then Vey Vpi2 = —4 V/2 = —2 V. The resulting curve representing Shockley’s equation appears in Fig. 6.25. The network equation is defined by RV; me eee (270 kQ)(16 V) 2.1 MQ + 0.27 MO = 1:82 ¥. and Ves = Vo — IpRs = 1.82 V = Ip (1.5 kO) Ip =O mA: Ves = +1.82V Ty (mA) 8 Iss a ~ log=2:4 ma 21 mA(Vas=0V) Figure 6.25 Detettining the Q Vesg=-I.8 V Vo=182¥ point for the network of Fig, (p=0mA) 64 262 Chapter 6 FET Biasing1.82 V To ey 2 mA ‘The resvuting bias line appears on Fig. 6.25 with quiescent values of : Ip, = 2.4 ma ‘and Ves, = 1.8 V (0) Yo = Von ~ IR = 16 V - (2.4 mAy(2.4 KO) = 10.24 V (0) Vs = IpRs = (2.4 mA)(1.5 kOQ) =3.6V (@) Vos = Vow — In(Rv + Rs) = 16 V — (2.4 mA)(2.4 kQ + 1.5 kQ) | 6.64. V | Vos = Vo ~ Ve = 10.24 V ~ 3.6 V = 6.64 V (@) Although seldom requested, the voltage Vpg can easily be determined using Yoe = Vo — Ve = 10.24 V ~ 1.82 V = 8.42 V Although the basic construction of the network in the next example is quite differ- ent from the voltage-divider bias arrangement, the resulting equations require a solu- tion very similar to that just described. Note that the network employs a supply at the drain and source. Determine the following for the network of Fig. 6.26. EXAMPLE 6.6 (a) Ip, and Ves, () Vos. . rove Vp=20V () Vs. ly Rp=18k0 10V Figure 6.26 Example 6.6 64 Voltage-Divider Biasing 263Figure 6.27 Determining the network equation for the configu: ration of Fig. 6.26. Figure 6.28 Determining the Q point for the network of Fig. 626 Solution (a) An equation for Vgs in terms of Jp is obtained by applying Kirchhoff's vol law to the input section of the network as redrawn in Fig. 6.27 Ves — IsRs + Vss = 0 or Vas = Vss — IsRs but and (6. ‘The result is an equation very similar in format to Eq. (6.16) that can be superi posed on the transfer characteristics using the procedure described for Eq. (6.16) That is, for this example, Ves = 10 V — Ip(1.5 kQ) For Ip = 0 mA, Ves= Ves =10V For Ves = 0 V, 0 = 10 V ~ sp(1.5 kQ) 10V ’ = = 6.67 mA a iComranr The resulting plot points are identified on Fig. 6.28. Jp (md) 9 loss) 324 ;[01 234567 8 9 10 Vp 1 = (vp) Vos = -035-V Ks=10V Vos The transfer characteristics are sketched using the plot point established by Vos = V2 = =1.5 Vand lp = Ipsy4 = 9 mA/4 = 2.25 mA, as also appearing “ig. 6.28. The resulting operating point establishes the following quiescent levels: Ip, = 6.9 mA Ves, = —0.35 V (b) Applying Kirchhoff’s voltage law to the output side of Fig. 6.26 will result in —Vss + IsRy + Vos + lpRp — Von = 0 Chapter 6 FET BiasingSubstituting /; = /p and rearranging gives “Vos = Von + Vss ~ In(Rp + Rs) (6.24) Which for this example results in Vos = 20 V + 10 V = (6.9 mA)(1.8 kO + 1.5 kQ) =30 V- 22.77 = 7.23 (Vp = Vo ~ In Ro 20 V — (6.9 mA)(1.8 KO) = 20 V ~ 12.42 V = 7.58 V 7.58 V — 7.23 V 0.35 V 6.5 DEPLETION-TYPE MOSFETs The similarities in appearance between the transfer curves of JFETs and depletion- type MOSFETs permit a similar analysis of each in the de domain, The primary difference between the two is the fact that depletion-type MOSFETs permit operating points with positive values of Vis and levels of Zp that exceed Ipss. In fact, for all the configurations discussed thus far, the analysis is the same if the JFET is replaced by a depletion-type MOSFET. ‘The only undefined part of the analysis is how to plot Shockley’s equation for positive values of Vs. How far into the region of positive values of Vgs and values of Tp greater than Ipss does the transfer curve have to extend? For most situations thi required range will be fairly well defined by the MOSFET parameters and the result- ing bias line of the network. A few examples will reveal the impact of the change in device on the resulting analysis. For the n-channel depletion-type MOSFET of Fig. 6.29, determine: (a) Ip, and Ves, (b) Vos 9 18V Figure 6.29 Example 6.7 EXAMPLE 6.7 265Solution (a) For the transfer characteristics a plot point is defined by Ip = Ipssi4 = 6 mA = 1.5 mA and Ves = Vpi2 = —3V/2 = —1.5 V. Considering the level of Vp and the fact that Shockley’s equation defines a curve that rises more rapidly as Vos becomes more positive, a plot point will be defined at Vos = +1 V. Substituting into Shockley’s equation yields 12 6 ma(t + 3) = 6 mA(1.778) = 10.67 mA ‘The resulting transfer curve appears in Fig. 6.30. Proceeding as described for JFETs, we have: 10 MQQ8 V) Eg. (6.15) = ne 419)" Vo=T9 Mo + 110 MO Eq. (6.16): Vi Vo — IpRs = 1.5 V = [p(750 Q) Tp (mA) nL Figure 6.30 Determining the Q Vp : point for the network of Fig Vosg=-08 ¥ be Setting Ip = 0 mA, results in Setting Vos = 0 V, yields Vo _ 1.5V CRS NE A 75007 ™ ‘The plot points and resulting bias line appear in Fig. 6.30. The resulting operating point lo, = Ves, = 266 Chapien 6, FET Biasing(b) Eq. (6.19); Vos = Vp ~ In(Rn + Rs) 18-¥ — (3.1 mA)(1.8 kQ. + 750 2) 10.1V Repeat Example 6.7 with Ry = 150 0. EXAMPLE 6.8 Solution (a) The plot points are the same for the transfer curve as shown in Fig. 6.31. For the bias line, Vas = Va — Ips = 1.5 V — Ip 150.9) Figure 6.31 Example 68 Setting fy = 0 mA results in Vos = 1.5V Setting Vay = 0 V yields Vo _ LSV pare = 10 mA Parse SU a ‘The bias line is included on Fig, 6.31. Note in this case that the quiescent point results in a drain current that exceeds pss with a positive value for Ves. The result: Ip, = 7.6 mA Vos, = +0.35 V - (0) Eq. (6.19): Vos = Von — In(Rp + Rs) = 18 V — (7.6 mA)(1.8 kQ + 150.0) 3.18 V 6.5. Depletion-Type MOSFETs 267EXAMPLE 6.9 Determine the following for the network of Fig. 6.32. (a) Ip, and Ves, Ay Vie 20 Figure 6.32 Example 6.9 Solution (a) The self-bias configuration results in . Vas = —lpRs as obtained for the JFET configuration, establishing the fact that Vos must be less than zero volts. There is therefore no requirement to plot the transfer curve for posi- tive values of Ves, although it was done on this occasion to complete the transfer characteristics. A plot point for the transfer characteristics for Ves <0 V is Joss _ 8 mA I, =2mA Eh 4 Vp ea and Vere % 4 and for Ves > 0 V since Vp = —8 V we will choose Ves = +2 and i= Ioss(1 - = 12.5 mA The resulting transfer curve appears in Fig. 6.33. For the network bias line, at Ves = 0 V, ly = 0 mA. Choosing Ves = — 6 V gives 6V ie 24k0 The resulting Q-point: Ip, = 1.7 mA -43V (b) Vp = Von — IoRo = 20 V ~ (1.7 mA)(6.2 KO) 9.46 V Chapter 6 FET Biasing== Ip =A. mA { ‘0 67-65-43 2-1 Ve Vis Figure 6.33 Determining the Q gre point for the network of Fig Yos=-43V a ‘The example to follow employs a design that can also be applied to JFET transis- tors. At first impression it appears rather simplistic, but in fact it often causes some confusion when first analyzed due to the special point of operation. Determine Vps for the network of Fig. 6.34, EXAMPLE 6.10 Solution The direct connection between the gate and source terminals requires that Ves =0V Since Ves is fixed at 0 V the drain current must be Ipss (by definition). In other words, Vos, =0V and Ip, = 10 mA There is therefore no need to draw the transfer curve and Vp = Vpn — IR = 20 V — (10 mA)(1.5 kQ) =0V-15V =5V Figure 6.34 Example 6.10 6.6 ENHANCEMENT-TYPE MOSFETs The transfer characteristics of the enhancement-type MOSFET are quite different from those encountered for the JFET and depletion-type MOSFETs resulting in a graphical solution quite different from the preceding sections. First and foremost, recall that for the n-channel enhancement-type MOSFET, the drain current is zero for levels of gate-to-source voltage less than the threshold level Vejscrm), a8 shown in Fig 6.35. For levels of Vas greater than Vescry), the drain current is defined by 6.6. Enhancement-Type MOSFETs 269270 Ves amy Y ¥os Ve Ip=0mA Yas om Figure 6.35 Transfer characteristics of an n-channel enhancement type MOSFET. Ip = KVos = Vesctty)” (6.25) Since specification sheets typically provide the threshold voltage and a level of drain current (Foq)) and its corresponding level of Vesiony, tWo points are defined immedi- ately as shown in Fig. 6.35. To complete the curve the constant k of Eq. (6.25) must be determined from the specification sheet data by substituting into Eq. (6.25) and solving for k as follows: Ip = Kas — Veescrm)? Foron = KVesion) ~ Veasert)” 1 See eee eS (6.26) Weston; = Vascrny) and Once & is defined, other levels of 2 can be determined for chosen values of Vos Typically, a point between Vescrm) and Vesion) and one just greater than Vision) Will provide a sufficient number of points to plot Eq. (6.25) (note Zp, and Ip, on Fig. 6.35). Feedback Biasing Arrangement A popular biasing arrangement for enhancement-type MOSFETs is provided in Fig, 6.36. The resistor Re brings a suitably large voltage to the gate to drive the MOSFET Since Iq = 0 mA and Vp, = 0 V, the de equivalent network appears as shown in Fig. 6.37. A direct connection now exists between drain and gate, resulting in and. (6.27) Chapter 6 FET BiasingFigure 637 DC equivalent of Figure 6.36 Feedback biasing arrangement. the network of Fig, 6.36. For the output circuit, Vos = Von — InRo ‘which becomes the following after substituting Eq. (6.27): (6.28) The result is an equation that relates the same two variables as Eq. (6.25), permitting the plot of each on the same set of axes Since Eq. (6.28) is that of a straight line, the same procedure described earlier can be employed to determine the two points that will define the plot on the graph. Substituting /) = 0 mA into Eq. (6.28) gives (6.29) (6.30) The plots defined by Eqs. (6.25) and (6.28) appear in Fig. 6.38 with the resulting operating point. Figure 6.38 Determining the Q point for the network of Fig, : Yop Ves ies 6.36 6.6 Enhancement-Type MOSFETs 271‘@ EXAMPLE 6.11 Determine J, and Vps, for the enhancement-type MOSFET of 6.39. qi2Vv Figure 6.39 Example 6 11 Solution Plotting the Transfer Curve: Two points are defined immediately as shown in Fig. 6.40, Solving for k: Lo ,0n) Se ole Same an ___ 6 mA @V-3V = 0.24 x 1075 A/V? 6 V (between 3 and 8 V): Ip = 0.24 x 1073(6 V ~ 3 V)? = 0,24 x 10-3(9) =2.16 mA é Vos= 10V, tp = 11.76 mA 16 VsIp=2.16mA Figure 6.40 Plotting the trans fer curve lor the MOSFET off Yasar Yoston 639. ' r2s45678 9 10 22 Chapter 6 FET Biasing4 shown on Fig. 6.40. For Vos = 10 V (slightly greater than Vescrm) Tp = 0.24 % 107(10 V — 3 V)? = 0.24 x 10°-*(49) 1.76 mA asalso appearing on Fig. 6.40. The four points are sufficient to plot the full curve for the range of interest as shown in Fig. 6.40. For the Network Bias Line: Ves = Voo ~ IpRp = 12 V~ Ip(2 k®) Eq. (6.29): Vas = Vop = 12 VI), ~ama. Yoo _ 12V Rp 2kO The resulting bias line appears in Fig. 6.41. The operating point Ip, = 2.75 mA Eq. (6.30): Ip = and Vos, = 6.4 V with Vos, = Vas, = 64 V Ip=mA 617 8 9 1011 1d Ves Vouy=04V Wool Figure 6.41 Determining the Q point for the network of Fig. 6.39 Yoltage-Divider Biasing Arrangement A second popular biasing arrangement for the enhancement-type MOSFET appears in Fig, 6.42. The fact that J =0 mA results in the following equation for Veg as derived from an application of the voltage-divider rule: (6.31) 6.6 Enhancement-Iype MOSFETs 273Applying Kirchhoff's voltage law around the indicated loop of Fig. 6.42 will resultin +V6— Vos — Va, = 0 and Vas = Va — Ve, or (6.32) For the output section: Va, + Vos + Ve, ~ Vop = 0 and Vos = Vop ~ Vr, ~ Vr, or Vos = Vow = In(Rs + Rp) (6.33) Since the characteristics are a plot of Jp versus Vs and Eq. (6.32) relates the same two variables, the two curves can be plotted on the same graph and a solution deter mined at their intersection. Once Ip, and Vgs, are known, all the remaining quantities of the network such as Vps, Vp, and Vs can be determined. 274 EXAMPLE 6.12 Determine Ip,, Vas, and Vps for the network of Fig. 6.43. + oNaasi Yes ¥OSIpqy= 3A at V5) = 10V 082k Figure 6.43. Example 6.12. Solution Network: (18 MQ)40 V) Eq. (63D: Vo= aan. = ISMOGOV) _ gy gq. (6.31): Vag R,}+R, 22M0+18MQ . Eq. (6.32): Vos = Vo ~ IpRs = 18 V — 1p (0.82 kA) When /p = 0 mA, Vas = 18 V ~ (0 mA)(0.82 kM) = 18 V as appearing on Fig. 6.44. When Vos = 0 V, Vos = 18 V ~ 1p(0.82 kQ) 0 = 18 V ~ 1,(0.82 kQ) __18v > 0.82 KO 21.95 mA as appearing on Fig. 6.44. Chapter 6 FET Biasing15 20 2.5V Ve=18V Vasey Yasg= Figure 6.44 Determining the Q-point for the network of Example 6.12, Device: Vos =5-V, Laon) = 3 MA with Vesion = 10 V Eq. (6.26); k= Io, (Weston — Vesern) 3mA - = A aT = 0.12 x 107? AV? qov —5 vy? oe Ip = Vos ~ Voscrm)* = 0.12 x 10° (Ves — 5)? which is plotted on the same graph (Fig. 6.44). From Fig. 6.44, Ip, = 6.7 mA, Vos, = 12.5 V Eq. (6.33): Vis = Vop — In(Rs + Ro) 0 V = (6.7 mA)(0.82 kQ + 3.0 k) =40V—25.6V =14.4V 6.7 SUMMARY TABLE Now that the most popular biasing arrangements for the various FETs have been introduced, Table 6.1 was developed to review the basic results and to demonstrate the similarity in approach for a number of configurations. It also reveals that the general analysis of de configurations for FETs is not overly complex. Once the trans- fer characteristics are established, the network self-bias line can be drawn and the Q-point determined at the intersection of the device transfer characteristic and the network bias curve. The remaining analysis is simply an application of the basic laws of circuit analysis. 6.7 Summary Table 275276 TABLE 6.1 FET Bias Configurations Type Configuration Pertinent Equations Veo Ry JFET Vas = Voc Fixed-bias Yos= Von ~ lols at JET Vas = lols Selt-bias Vos = Vow ~ toto + Rs) JFET Voltage-divider Vora eRe bias = Ve Ins Vos = Von ~ lofRip * Rs) JFET Vos = Ves ~ Tots Dual-supply Van Vox ~ UolBy + Ry JFET ov Wasp =0-V) ss JFET s (p= 0.0) Vo Jokes ~ Ik, Depletion-type MOSFET ‘(AI configurations ‘hove pls eases where Vas -+votage) Fixed-bias Depletion-type MOSFET. Voltage-divider bias R: Yoo Ri tRs Vos = Vo — leks Vos = Vn — InfRn + Ro) Enhancement. type MOSFET Feedback configuration Enhancement- type MOSFET Voltage-divider bias68 COMBINATION NETWORKS Now that the de analysis of a variety of BJT and FET configurations is established, the opportunity to analyze networks with both types of devices presents itself. Funda- mentally, the analysis simply requires that we first approach that device that will provide a terminal voltage or current level. The door is then usually open to calculate other quantities and concentrate on the remaining unknowns. These are usually par- ticularly interesting problems, due to the challenge of finding the opening and then using the results of the past few sections and Chapter 5 to find the important quantities. for each device, The equations and relationships used are simply those we have now employed on more than one occasion—no need to develop any new methods of analysis, Determine the levels of Vp and Ve for the network of Fig. 6.45. lov 2.7ka Vp Yo Bee 1.62 Figure 6.45 Example 6.13 Solution, is typically an important quantity to a From past experience we now realize that V, determine or write an equation for when analyzing JFET networks. Since Ves level for which an immediate solution is not obvious, let us turn our attention to the transistor configuration, The voltage-divider configuration is one where the approxi mate technique can be applied (BRy = (180 x 1.6 kQ) = 288 kO > 10R> 240 kQ), permitting a determination of Vs using the voltage-divider rule on the input cireuit. For Vy Using the fact that Vg = 0.7 V results in — Ver = 3.62 V- 0.7 V 6.8 Combination Networks EXAMPLE 6.13 217and. with Continuing, we find for this configuration that Ip= ly = Ic and Vp = 16 V ~ Ip(2.7 kQ) = 16 V ~ (1,825 mA)(2.7 kM) = 16 V ~ 4.93 V = 1107 The question of how to determine Ve is not as obvious. Both Ver and Vps are unknown quantities preventing us from establishing a link between Vp and V¢-or from Vp to Vp. A more careful examination of Fig. 6.45 reveals that Ve is linked to Vz by Ves (assuming that Vz, = 0 V). Since we know Vp if we can find Ves, Ve can be determined from Vo = Vp - Vi The question then arises as to how to find the level of Vos, from the quiescent value of Ip. The two are related by Shockley’s equation: Vase \* pg tom ae) . e and Ves, could be found mathematically by solving for Ves, and substituting numeri cal values, However, let us turn to the graphical approach and simply work in the reverse order employed in the preceding sections. The JFET transfer characteristics are first sketched as shown in Fig. 6.46. The level of p, is then established by a horizontal line as shown in the same figure. Vos, is then determined by dropping a line down from the operating point to the horizontal axis, resulting in Ves, = —3.7V The level of Vez Vo = Va — Vas, = 3.62 V ~ (-3.7 V) =7.32V Figure 6.46 Determining the Q point for the network of Fig. 645, 278 Chapter 6 FET Biasing———— EXAMPLE 6.14 Determine Vp for the network of Fig. 6.47. lev 36k 470 KO B30 YD ¥ 24k Figure 6.47 Example 6.14 In this case there is no obvious path to determine a voltage or current level for the transistor configuration. However, turning to the self-biased JFET, an equation for Ves can be derived and the resulting quiescent point determined using graphical techniques. That is, Solution Ves = —IpRs = ~In(2.4 kO) resulting in the self-bias line appearing in Fig. 6.48 that establishes a quiescent point at Ves, = -2.6V Ip, = 1 mA For the transistor, and Vp = 16 V ~ [9(470 kO) = 16 V ~ (12.5 #A)(470 kM) = 16 V ~ 5.875 V 10.125 V and Ve = Vo = Va — Var = 10.125 V-0.7V Figure 6.48 Determining the Q = 9.426 y point for the network of Fig. Sit. 6.8 Combination Networks 279Figure 6.49 Self-bias configura- tion to be designed 6.9 DESIGN The design process is one that is not limited solely to de conditions. The area of application, level of amplification desired, signal strength, and operating conditions are just a few conditions that enter into the total design process. However, we will first concentrate on establishing the chosen de conditions. For example, if the level of Vp and [p is specified for the network of Fig. 6.49, the level of Ves, can be determined from a plot of the transfer curve and Rs can then be determined from Vg = —IpRs. If Vpn is specified, the level of Rp can then be calculated from Rp = (Vpp — Vp)flp. Of course, the value of Rs and Rj may not be standard commercial values requiring that the nearest commercial value be employed However, with the tolerance (range of values) normally specified for the parameters of a network, the slight variation due to the choice of standard values will seldom cause a real concer in the design process. The above is only one possibility for the design phase involving the network of Fig. 6.49. It is possible that only Vpp and Rp are specified together with the level of Vps. The device to be employed may have to be specified along with the level of Ry, It appears logical that the device chosen should have a maximum Vps greater than the specified value by a safe margin. In general, it is good design practice for linear amplifiers to choose operating points that do not crowd the saturation level (Ipss) or cutoff (Vp) regions. Levels f Vos, close to Vp/2 or Ip, near Ipss/2 are certainly reasonable starting points in the design. Of course, in every design procedure the maximum levels of fp and Vos & appearing on the specification sheet must not be considered exceeded. The examples to follow have a design or synthesis orientation in that specific levels are provided and network parameters such as Rp, Rs, Vp, and so on, must be determined. In any case the approach is in many ways the opposite of that described in previous sections. In some cases it is just a matter of applying Ohm’s law in its appropriate form. In particular, if resistive levels are requested, the result is often obtained simply by applying Ohm’s law in the following form: (6.34) where Vp and Jp are often parameters that can be found directly from the specified voltage and current levels. EXAMPLE 6.15 280 For the network of Fig. 6.50 the levels of Vp, and Jp, are specified. Determine the required values of Rp and Rs. What are the’ closest ‘standard commercial values? p20v Figure 6.50. Example 6.15, Chapter 6. FET BiasingSolution As defined by Eq. (6.34), kp = Vie = Yoo = Vo, ee ees 2V-12V_ BV ee a) es 25mA 2.5 mA Plotting the transfer curve in Fig. 6.51 and drawing a horizontal line at Ip, = 2.5 mA will result in Vos, = ~1 V, and applying Ves = —/pRs will establish the level of Rs: Yes Figure 6.51 Determining Vos, for the network of Fig, 6.50. The nearest standard commercial values are Rp = 3.2 KO > 3.3kD Rs = 0.4 kD > 0.39 kQ EXAMPLE 6.16 For the yoltage-divider bias configuration of Fig. 6.52, if Vp = 12 V and Ves, =2V, determine the value of Rs. o16V Solution The level of Ve; is determined as follows: Vg= 47 4206.V) 470 + 91 KO Vow = Vo Ro 16V-12V neem SEG The equation for Ves is then written and the known values substituted: 18k =5.44.V o12V with Tp = 2.22 mA Vas = Va — InRs -2 V = 5.44 V ~ (2.22 mA)Rs 7.44 V = —(2.22 mA)Rs 144V. joes lian ee S222 mA Figure 6.52. Example 6.16 = 3.35 kO ‘The nearest standard commercial value is 3.3 kQ. 6.9 Design 281282 EXAMPLE 6.17 The levels of Vps and Ip are specified as Vps = Vp and Ip of Fig. 6.53. Determine the level of Vpp and Rp a = Figure 6.53 Example 6.17 Solution Given Ip = Ingon = 4 MA and Ves = Vesion = 6 V, for this configuration, Vip and 6V =Wpp so that Vpp = 12.V Applying Eq. (6.34) yields Vay _ Vow ~Yos _ Von ~ Won _ ov R ° lb Ton Toven Toeon 6Vv a = eae and Rp Wank 5k which is a standard commercial value. 6.10 TROUBLESHOOTING How often has a network been carefully constructed only to find that when the power is applied, the response is totally unexpected and fails to match the theoretical caleu- lations. What is the next step? Is it a bad connection? A misreading of the color code for a resistive element or simply an error in the construction process? The range of possibilities seems vast and often frustrating, The troubleshooting process first de- scribed in the analysis of BJT transistor configurations should narrow down the list of possibilities and isolate the problem area following a definite plan of attack. In gen- eral, the process begins with a rechecking of the network construction and the termi- nal connections. This is usually followed by the checking of voltage levels between specific terminals and ground or between terminals of the network. Seldom are cur rent levels measured since such maneuvers require disturbing the network structure to insert the meter, Of course, once the voltage levels are obtained, current levels can be calculated using Ohm’s law. In any case, some idea of the expected voltage or current level must be known for the measurement to have any importance. In total, therefore, the troubleshooting process can only begin with some hope of success if the basic operation of the network is understood along with some expected levels of voltage or Chapter 6 FET Biasingat, For the n-channel JFET amplifier it is clearly understood that the quiescent of Ves, is limited to 0 V or a negative voltage. For the network of Fig. 6.54, Jimited to negative values in the range 0 V to Vp. If a meter is hooked up as Fig. 6.54, with the positive lead (normally red) to the gate and the negative ¢l (usually black) to the source, the resulting reading should have a negative sign a magnitude of a few volts. Any other response should be considered suspicious ml needs 10 be investigated “Tie level of Vos is typically between 25 and 75% of Vpp. A reading of 0 V for ‘clearly indicates that either the output circuit has an “‘open’’ or the JFET is mally short-circuited between drain and source. If Vp is Vpp volts, there is obvi- no drop across Rj, due to the lack of current through Rp and the connections d be checked for continuity. Ifthe level of Vps seems inappropriate, the continuity of the output circuit can vollage levels from Vipp to ground using the positive lead. If Vp = Vp, the current gh Rp may be zero, but there is continuity between Vp and Vin. It Vs = Vo. onfirmed, however. In this case it is possible that there is a poor il connection between Rs and ground that may not be obvious. ‘The internal ction between the wire of your lead and the terminal connector may have sepa- d, Other possibilities also exist such as a shorted device from drain to source but the troubleshooter will simply have to narrow down the possible causes for the mal- function. ‘The continuity of a network can also be checked simply by measuring the voltage across any resistor of the network (except for Rg in the IFET configuration). An indication of 0 V immediately reveals the lack of current through the element due to an open circuit in the network. The most sensitive element in the BIT and JFET configurations is the amplifier isell. The application of excessive voltage during the construction or testing phase or the use of incorrect resistor values resulting in high current levels can destroy the “device. If you question the condition of the amplifier, the best test for the FET is the _ suve acer since it not only reveals whether the device is operable but also its range ‘pf current and voltage levels. Some testers may reveal that the device is still funda- mentally sound but do not reveal whether its range of operation has been severely reduced The development of good troubleshooting techniques comes primarily from expe- rience and a level of confidence in what to expect and why. There are, of course, times when the reasons for a strange response seem to disappear mysteriously when ‘you check a network. In such cases it is best not to breathe a sigh of relief and continue with the construction. The cause for such a sensitive “make or break’* ‘Situation should be found and corrected or it may reoccur at the most inopportune ‘moment, 6.11 P-CHANNEL FETs ‘The analysis thus far has been limited solely to n-channel FETs. For p-channel FETS 4 mirror image of the transfer curves is employed and the defined current directions are reversed as shown in Fig. 6.95 for the various types of FETs. Note for each configuration of Fig. 6.55 that each supply voltage is now a nega- tive voltage drawing current in the indicated direction. In particular, note that the double-subscript notation for voltages continues as defined for the n-channel device: Ves: Vos, and so on. In this case, however, Ves is positive (positive or negative for the depletion-type MOSFET) and Vps negative: 6.11 P-Channel FETs Figure 6.54 Checking the de operation of the JPET self-bias configuration 283Figure 6.55 p-Channel configurations Due to the similarities between the analysis of n-channel and p-channel devices, one can actually assume an n-channel device and reverse the supply voltage and perform the entire analysis. When the results are obtained the magnitude of each quantity will be correct, although the current direction and voltage polarities will have to be reversed. However, the next example will demonstrate that with the experience gained through the analysis of n-channel devices the analysis of p-channel devices is quite straightforward Chapter 6 FET BiasingDetermine Ip,, Vos,, and Vs for the p-channel JFET of Fig. 6.56. Figure 6.56 Example 6.18 Solution 20 kQ(—20 V) ve 20 che 68 a ane Applying Kirchhoff's voltage law gives Vo — Vos + IRs = 0 and. Vas = Ve + IpRs Choosing Ip = 0 mA yields Ves = Va = ~4.55V a appearing in Fig. 6.57 Choosing Ves = 0 V. we obtain = 2.53 mA as also appearing in Fig. 6.57. The resulting quiescent point from Fig. 6.57: 4 mA Ig 2-point rages Ve Vos Figure 6.57 Determining the Q Vee point for the JFET configuration Vase AV of Fig, 6.56. 6.11 P-Channel FETs EXAMPLE 6.18Figure 6.58 Universal JFET bias curve 286 For Vps Kirchhoff's voltage Jaw will result in —IpRs + Vos — IpRp'+ Vop = 0 and Vps = —Vpp + Ip(Rp + Rs) —20 V + (3.4 mA)(2.7 kO + 1.8 KO) -20V + 15.3.V =-4.7V 6.12 UNIVERSAL JFET BIAS CURVE Since the de solution of a FET configuration requires drawing the transfer curve for each analysis, a universal curve was developed that can be used for any level of and Vp. The universal curve for an n-channel JFET or depletion-type MOSFET (fo negative values of Vos.) is provided in Fig, 6.58. Note that the horizontal axis is that of Vs but of a normalized level defined by Vgs/|V|, the |Vp indicating that ony the magnitude of Vp is to be employed, not its sign. For the vertical axis the scale iy also a normalized level of [p/fpss. The result is that when I) = Ipss the ratio is 1, and when Vos = Vp the ratio Vas/|Vpl is —1, Note also that the scale for Ip/pss is on the left rather than on the right as encountered for fp in past exercises. The additional two scales on the right need an introduction. The vertical scale labeled m can in itself be used to find the solution to fixed-bias configurations. The other scale, labeled M, is employed along with the m scale to find the solution to voltage-divider configurt to Wl Vee ca Manx Nb HR Ios Wal Lo Ves el Chapter 6 FET Biasingtions. The scaling for m and M come from a mathematical development involving the network equations and normalized scaling just introduced. The description to follow will not concentrate on why the m scale extends from 0 to 5 at Vesi|Vp| = —0.2 and the M scale from 0 to 1 at Ves/|Vp] = 0 but rather on how to use the resulting scales to obiain a solution for the configurations. The equations for m and M are the following, with Ve as defined by Eq. (6.18). (6.35 : (6.36) Ro with Vo RR: Keep in mind that the beauty of this approach is the elimination of the need to sketch ihe transfer curve for each analysis, that the superposition of the bias line is a great deal easier, and that the calculations are fewer. The use of the m and M axes is best described by examples employing the scales. Once the procedure is clearly under- stood, the analysis can be quite rapid with a good measure of accuracy Determine the quiescent values of Zp and Vgs for the network of Fig. 6.59. @16v 39ko. 0.05 uF Tv — 0.05 we SS 40uF Figure 6.59 Example 6.19 Solution Calculating the value of m, we obtain Il |=3y| IpssRs_ (6 mA)(1.6 kQ) The self-bias line defined by Rs is plotted by drawing a straight line from the origin through a point defined by m = 0.31, as shown in Fig. 6.60. The resulting Q-point: ii ve and. Joss [vel = 0.31 m= 0.575 6.12 Universal JFET Bias Curve EXAMPLE 6.19 287Mens 10 os 06 Pere Q-point (Ex. 6.20) Bee Soa $0365 Q-poiilt (Ex. 6.19) — rH 02 EEE HEH bet Figure 6.60 Universil curve for Examples 6.19 and 6.20. The quiescent values of fp and Vs can then be determined as follows: Ip, = 0-18Ipss = 0.18(6 mA) = 1.08 mA and Ves, = —0.575|Vp| = —0.575(3 V) = -1.73 V EXAMPLE 6.20 Determine the quiescent values of fr) and Vgs for the network of Fig. 6.61. 18v Soiosa tap 288 ¥ Figure 6.61 Example 6.20Solution Calculating m gives (220 kO)(18 V) En 910 KO + 220 kO Finding M, we have 3.5V Mek ee 0.625(23.Y Vel Ove Now that m and M are known, the bias line can be drawn on Fig. 6.60. In particular, note that even though the levels of Ipsy and Vp are different for the two networks, the same universal curve can be employed. First find on the M axis as shown in Fig, 6.60. Then draw a horizontal line over to the m axis and at the point of intersection add the magnitude of m as shown in the figure. Using the resulting point on the m axis and the M intersection, draw the straight line to intersect with the transfer curve and define the Q-point That is, =0.53 and = -0.26 Vol and = 0.53fpss = 0.53(8 mA) = 4.24 mA with = —0.26|Vp| = —0.26(6 V) = -1.56 V 6.13 COMPUTER ANALYSIS ‘The computer analysis of a voltage-divider JFET configuration is performed in this section using both BASIC and PSpice. The PSpice approach will be quite similar to that employed for the BJT configuration of Chapter 4. The use of BASIC will require mathematical approach that will include finding the solution to a quadratie equation. PSpice ‘The voltage-divider configuration of Fig. 6.61 is redrawn in Fig. 6.62 with the de- fined nodes and device parameters as introduced in Chapter 5. The parameters are 18V 0.222. 10°AN? Figure 6.62 Nework of Fig, 6.61 with defined nodes for a PSpice analysis. 289290 ‘ess 02/28/90 *####8% Evaluation PSpice (January 1989) AA##¥4" 15:11:26 # be Bias of JPET configuration in Fig. 6.61 B ‘448 || CIRCUIT DESCRIPTION yop 2.0 18v t Ri 2 1 910K R21 0 220K RD 23 2.2K RS 40 1.2K i 314 9N “MODEL JN NJF(VTO=~6V BETA=.2228-3) ibe vp 18 18 1 IPRINT DC V(1,4) (RD) LOPTIONS NOPAGE SEND ‘eee Sunction FET MODEL PARAMETERS oN NaF vro=6 BETA 222.000000E-06 ness DC TRANSFER CURVES ‘TEMPERATURE = 27-000 DEG ¢ vo v(a,4) 1(RD) T.Q00E+01 -1.565E+00 4.225803 Figure 6.63. PSpice analysis of the JFET configuration of Fig. 6.61. entered as appearing in Fig. 6.63 in the same manner as described in previous chap ters with the JFET introduced using the formats described in Chapter 5. The voltage requested as V(1,4) is Vos, and the current I(RD) is Zp,,. Note how closely the resis match those of Example 6.20 with Ip, (Example 6.20) = 4.24 mA and Ip, (PSpice) = 4.23 mA, and Vos, (Example 6.20) = —1.56 V and Ves, (PSpice) = 157 V. BASIC If a language such as BASIC is employed, a common solution for the equations defined by the network and device must be found using mathematical techniques. For the network of Fig. 6.64a, we recognize that the device is described by Shockley’s equation (6.64b) Ib= Ioss\ 1 =| Vp (6.37) while the network is defined by (Fig. 6.64b) Vas = Va ~ Inks (6.38) Rov Ry + Rp with (6.39) If we insert the equation for fp (Eq. (6.37)] into Eq. (6.38), we obtain Vas\? Vp! Ves = Ve ~tnsks(1- Chapter 6 FET Biasingay bo. @ te Vasp 0 Yoo Vas Figure 6.64 Voltage-divider config. tration to he analyzed using BASIC, ) which, when expanded, results the quadratic equation sR: a a) fos + (ossRy — Ve)=0 ip B iG The solutions to the quadratic equation are then determined by B+ VB 2A 4AC with the actual solution being that value of Ves which falls within the range 0 to Vp. ‘The program will, of course, test the value of B? ~ 4AC, indicating no solution for the case of a negative value. The drain and source voltages are then Vp = Von ~ InRp (6.40) Vs = IpRs (6.41) and Vos = Vn ~ Vs (6.42) A summary of the variables and equations used in module 11000 are provided in Tables 6.2 and 6.3. The program listing appears in Fig. 6.65 with a run for the same values employed in the PSpice analysis. Again note the close correspondence in solutions. 6.13 Computer Analysis 291‘TABLE 6.2 Equations and Computer Statements ‘TABLE 6.3 Equation and Program Z for Module 11000 Variables for Module 11000 pation Variable Program Varabl Equation Computer Statement Eas ena . = Vo VG GG = (RIIRI + R2) * DD Vs vs Yo vb Ye GG Yon DD Voss Gs Gs" Vos bs SS ¥ 1 GSIVP) 1 2 e Bs bb 1D A=SS*RSIVE 1 2 i 8s R, RI 1-25 «RSVP R R2 Re RS C= lossRs = Ve C=S5+RS~GG Ro, RD D= BP 4Ac D=Bt2-44A9C Z yee Vi =(-B + SQRDYVI2 * A) 2A -B-VD V, Dy V2 = (-B — SQRDY/2 + A) Uo QRID)}(2 # A) Yo = Voo ~ Ino YD = DD - ID * RD Vs = toRs YS = 1D + RS Yos = Vo ~ DS = vp- vs 10 REM SAGARA UCR RAIA REAR RARE RR AHR RRa AEE 20 REM 30 REM Module for FET dc Bias Calculations 40 REM ; 50 REM RARERRARSAHRRRAARI ERS ERRARIERARRRAHHAMRRRAH EH 60 REM 100 PRINT "This program provides the dc bias calculations" 110 PRINT "for a JFET or depletion MOSFET’ 120 PRINT "voltage-divider configuration. 330 PRINT. 140 PRINT “Enter the following circuit data: 150 PRINT. 160 INPUT "R1 (use 1630 if open)=";R1 170 INPUT ™R2 =m RR 120 INPUT "RS=";RS 190 INPUT "RD=";RD 200 PRINT 210 INPUT “Supply voltage, VDD=" 220 PRINT 220 PRINT “Enter the following device data:" 240 INPUT "Drain-ource saturation current, IDS! 250 INPUT "Gate-source pinchoff voltage, VP=";VP 260 PRINT :PRINT 270 REM Now do bias calculations 280 cosuB 11000 200 PRINT "Bias ourrent is, ED=";1D*100 300 PRINT "Bias voltage " 310 PRINT * 165; "vol 320 PRINT. i¥O; volts” 330 PRINT. iV8;"volts" 340 PRINT 350 END DD a Figure 6.65 BASIC program for the analysis of the network of Fig. 6.64. 292 Chapter 6 FET Biasing11000 REW Module for FET de bias calculations 11010 Ge=(Ra/(R1+R2)) *DD 41020 A=SS4RS/VP~2 11030 B=1-248S+RS/vP 11040 c=ss+Rs-co 11050 D=B*2-4easc 11060 IF Deo THEN PRINT " 11070 Vi=(-BSOR(D)) /(2#A) 11080 V2=(=B-SOR(D)) /(2#A) 41090 IF ABS(V1)>AR5(VP) THEN GS=v2 11100 IP ABS(V2)>ADS(VP) THEN GS=v2 31110 1D=s54(1-G8/vP) “2 11120 11130 vo-ce 11140 vp=pp-zp*RD 11150 DS=vD-vs 11160 RETURN 10 Solution! RUN ‘This program provides the de bias calculations for a JPET or depletion MosPET voltage-divider configuration. Enter the following circuit data: Ri (use 1830 if open)=? 91083 Ra =? 22083 RS=? 1.263 RD=? 21223 Supply voltage, vpD=? 18 Enter the following device data: Drain-source saturation current, IDS. Gate-source pinchoff voltage, vP=? -6 Bias current is, Tb» 4.26821 mA Bias voltages are: v@S=-1,617427 volte vO= 8.609939 volts Vs= 5.121952 volts vps= 3.488087 volte Figure 6.65 (Continued,) § 6.2 Fixed-Bias Configuration |. For the fixed-bias configuration of Fig. 6.66: {a) Sketch the transfer characteristics of the device. (b) Superimpose the network equation on the same graph (©) Determine fp,, and Vos, (a) Using Shockley’s equation, solve for Zp, and then find Vps,. Compare with the solutions of part (c). Rv Figure 6.66. Problems 1, 35, 38 Problems. PROBLEMS 293294 2. For the fixed-bias configuration of Fig. 6.67, determine: (a) Ip, and Vos,- (b) Vos. Vo. Vex and Vs. 168 = Figure 6.67. Problem 2 3. Given the measured value of Vp in Fig, 6.68, determine: @) Ip. 0) Vos. nay, © Vee: \) D 16k0 Vy=9V Vou. as Figure 6.68, Problem 3 4. Determine Vp for the fixed-bias configuration of Fig. 6.69. 5. Determine Vp for the fixed:-bias configuration of Fig. 6.70. 20V IBV Ima 2MQ. a Figure 6.69 Problem 4 Figure 6.70. Problem 5 Chapter 6 FET Biasing§ 6.3 Self Bias Configuration 6, For the self-bias configuration of Fig. 6.71 (@) Sketch the transfer curve for the device. (b) Superimpose the network equation on the same graph (6) Determine fp, and Ves, @) Calculate Vps, Vp. Ve. and Vs. isv Figure 6.71 Problems 6, 7, 36, 39 . Determine Jp, for the network of Fig. 6.71 using a purely mathematical approach, That is, establish a quadratic equation for fp and choose that solution compatible with the network characteristics. Compare to the solution obtained in Problem 6, , For the network of Fig. 6.72, determine: (@) Ves, and Ip, (©) Voss Vox Ves and Vs. 9. Given the measurement Vy = 1.7 V for the network of Fig. 6.73, determine: @) Io, ©) Vesye ©) oss (@) Vo. ©) Vos. +10, For the network of Fig. 6.74, determine: (@) Ip 0) Vos. © Vp @) Vs ny I8v 20 1a pene 0.68 ka Figure 6,72 Problem 8 Figure 6.73. Problem 9 Figure 6.74 Problem 10 Problems 295© 11. Find Vs for the network of Fig. 6.75. lay 220 We 039%Q Figure 6.75 Problem 11 § 64 Voltage-Divider Biasing 12. For the network of Fig. 6.76, determine: (a) Vo. (b) dg and Vos. ©) Vos, (@) Vp and Vs. ‘Figure 6.76 Problems 12, 13, 40 13, (@) Repeat Problem 12 with Ry = 0.51 KO (about 50% of the value of 12). What is the effestof a smaller Rs on Ip, and Vos,? (b) What is the minimum possible value of Rs for the network of Fig. 6.767 14, For the network of Fig. 6.77, Vp = 9 V. Determine: (@) In. 0) Vs» Vos. © Vo. @) Vr. © 15. For the network of Fig. 6.78, determine: (@) Ing and Ves, (b) Vos and Vs. 16v 22kQ -4V Figure 6.77 Problem 14 Figure 6.78 Problems 15, 37 296 Chapter 6 FET Biasing+16. Given Vps = 8 V for the network of Fig. 6.79, determine: @) Ip. (b) Vp and Vs. © Ves: § 6.5 Depletion-Iype MOSFETs 17, For the self-bias configuration of F (@) Ip, and Vos, (0) Vos and Vp 18. For the network of Fig. 6.81, determine: @ Ip, and Ves, (0) Vos and Vs. 6.80, determine: lav IBV 043 ko Figure 6.80 Problem 17 Figure 6.81 Problem 18 § 6.6 Enhancement-Type MOSFETs 19. For the network of Fig. 6.82, determine: (a) Ig. (b) Yes, and Vos,. (0) Vp and Vs. (@ Vos. 20, For the voltage-divider configuration of Fig. 6.83, determine: (a) Ip, and Vos, (0) Vo and Vs. 24 1.2kQ og Lo 0, ¥% He 1MQ. a cans O5TKQ Res eae Figure 6.82 Problem 19 Figure 6.83 Problem 20 Problems Ry 3V Figure 6.79 Problem 16 297§ 6.8 Combination Networks 421, For the network of Fig. 6.84, determine: (@) Ve ©) Vos, and Ing © le @ In ©) Vp (f) Ve Figure 6.84 Problem 21 © 22, For the combination network of Fig. 6.85, determine: (a) Va. Vo (b) Ve. (0) Tes les Io- (@) Ty. (©) Ve, Vs, Vo. © Vee. (g) Vos. 10k Figure 6.85. Problem 22 298 Chapter 6 FET Biasing§ 6.9 Design #2. Design a self-bias network using a JPET transistor with [ps5 = 8 mA and Vp = —6 V to havea @-point at fp, = 4 mA using a supply of 14 V. Assume that Ry = 3Rs and use standard values. ‘+4. Design a voltage-divider bias network using a depletion-type MOSFET with [pgs = 10 mA and Vp = —4 V to have a Q-point at fp, = 2.5 mA using a supply of 24 V. In addition, set Vo 4V and use Ry = 2.5Rs with R= 22 MQ. Use standard values. 25, Design a network such as appearing in Fig. 6.39 using an enhancement-type MOSFET with Vescr 0.5 X 10 7A/V? to have a Q-point of Ip, = 6 mA. Use a supply of 16 V § 6.10 Troubleshooting +26, What do the readings for each configuration of Fig. 6.86 suggest about the operation of the network? 1Ma. 12VQ1Ma o @ Figure 6.86 Problem 26 +27. Although the readings of Fig. 6.87 initially suggest that the network is behaving properly, determine « possible cause for the undesirable state of the network. is the specific cause for its failure? #28. The network of Fig. 6.88 is not operating properly. Wh: 20V 20V 2a 2aK0 0a 3040 av oy a ae sasv sta ska ce ia Figure 6.87 Problem 27 Figure 6.88 Problem 28 Problems: RV © 299300 29. 30. § 6.11 P-Channel FETs For the network of Fig. 6.89, determine: (a) Ip, and Ves, (b) Vas, © Vo. For the network of Fig. 6.90, determine (a) Ip, and Ves,. (b) Vas. (©) Vo. Figure 6.89 Problem 29 Figure 6.90 Problem 30 al. ae 33. . Perform a PSpi § 6.12 Universal JFET Bias Curve Repeat Problem 1 using the universal JFET bias curve. Repeat Problem 6 using the universal JFET bias curve. Repeat Problem 12 using the universal JFET bias curve. Repeat Problem 15 using the universal JFET bias curve. § 6.13 Computer Analysis analysis of the network of Problem 1, Determine fp, and Ves,. Perform a PSpice analysis of the network of Problem 6. Determine Ip, and Vos, Perform a PSpice analysis of the network of Problem 15. Determine I Using BASIC, determine /y, and Vas, for the network of Problem 1. Using BASIC, determine p, and Vas, for the network of Problem 6. Using BASIC, determine I,,, Vosy- and Vis, for the network of Problem 12. ‘sg. 10d Vos, Please Note: Asterisks indicate more difficult problem. Chapter 6 FET Biasing