Miniature, Low-Voltage, Precision Step-Down Controller: General Description - Features
Miniature, Low-Voltage, Precision Step-Down Controller: General Description - Features
Miniature, Low-Voltage, Precision Step-Down Controller: General Description - Features
KIT
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EVALU BLE
AVA ILA
Miniature, Low-Voltage,
Precision Step-Down Controller
General Description ____________________________Features
MAX1637
The MAX1637 synchronous, buck, switch-mode power- ♦ ±2% DC Accuracy
supply controller generates the CPU supply voltage in
battery-powered systems. The MAX1637 is a stripped- ♦ 0.1% (typ) DC Load Regulation
down version of the MAX1636 in a smaller 16-pin QSOP ♦ Adjustable Switching Frequency to 350kHz
package. The MAX1637 is intended to be powered sep-
arately from the battery by an external bias supply (typi- ♦ Idle Mode™ Pulse-Skipping Operation
cally the +5V system supply) in applications where the ♦ 1.10V to 5.5V Adjustable Output Voltage
battery exceeds 5.5V. The MAX1637 achieves excellent
DC and AC output voltage accuracy. This device can ♦ 3.15V Minimum IC Supply Voltage (at VCC pin)
operate from a low input voltage (3.15V) and delivers the ♦ Internal Digital Soft-Start
excellent load-transient response needed by upcoming
generations of dynamic-clock CPUs. ♦ 1.1V ±2% Reference Output
Using synchronous rectification, the MAX1637 achieves ♦ 1μA Total Shutdown Current
up to 95% efficiency. Efficiency is greater than 80% over
a 1000:1 load-current range, which extends battery life in ♦ Output Overvoltage Crowbar Protection
system-suspend or standby mode. Excellent dynamic ♦ Output Undervoltage Shutdown (foldback)
response corrects output load transients caused by the
latest dynamic-clock CPUs within five 300kHz clock ♦ Tiny 16-Pin QSOP Package
cycles. Powerful 1A on-board gate driv-ers ensure fast ______________Ordering Information
external N-channel MOSFET switching.
PART TEMP RANGE PIN-PACKAGE
The MAX1637 features a logic-controlled and synchro-
nizable, fixed-frequency, pulse-width-modulation (PWM) MAX1637EEE 40°C to +85°C 16 QSOP
operating mode. This reduces noise and RF interference MAX1637EEE+ 40°C to +85°C 16 QSOP
in sensitive mobile-communications and pen-entry appli- +Denotes lead-free package.
cations. Asserting the SKIP pin enables fixed-frequency
mode, for lowest noise under all load conditions. For a __________Typical Operating Circuit
stand-alone device that includes a +5V VL linear regula-
tor and low-dropout capabilities, refer to the MAX1636
data sheet. VBIAS VBATT
BST
TOP VIEW
CSH 1 16 SKIP LX OUTPUT
CSL 2 15 LX
DL
FB 3 14 DH CC
PGND
CC 4 MAX1637 13 BST REF
REF 5 12 PGND SKIP CSH
SHDN 6 11 DL CSL
SYNC
SYNC 7 10 VGG
GND FB
GND 8 9 VCC
QSOP
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Miniature, Low-Voltage,
Precision Step-Down Controller
ABSOLUTE MAXIMUM RATINGS
MAX1637
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VCC = VGG = 5V, SYNC = VCC, IREF = 0mA, TA = 0°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.)
2 _______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
ELECTRICAL CHARACTERISTICS (continued)
MAX1637
(Circuit of Figure 1, VCC = VGG = 5V, SYNC = VCC, IREF = 0mA, TA = 0°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
OVERVOLTAGE PROTECTION
Overvoltage Trip Threshold FB, with respect to regulation point 4 7 10 %
Overvoltage Fault Propagation Delay FB to DL delay, 22mV overdrive, CGATE = 2000pF 1.25 µs
Output Undervoltage Lockout Threshold % of nominal output 60 70 80 %
Output Undervoltage Lockout Delay From shutdown or power-on-reset state 6144 clocks
INPUTS AND OUTPUTS
Logic Input Voltage High SHDN, SKIP, SYNC 2.4 V
Logic Input Voltage Low SHDN, SKIP, SYNC 0.8 V
Logic Input Bias Current Pin at GND or VCC -1 1 µA
CSH = CSL = 5V, VCC = VGG = GND,
Current-Sense Input Leakage Current 10 µA
either CSH or CSL input
Gate Driver Sink/Source Current DH or DL forced to 2V 1 A
Gate Driver On-Resistance High or low, DH or DL 7 Ω
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VCC = VGG = 5V, SYNC = VCC, IREF = 0mA, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
_______________________________________________________________________________________ 3
Miniature, Low-Voltage,
Precision Step-Down Controller
ELECTRICAL CHARACTERISTICS (continued)
MAX1637
(Circuit of Figure 1, VCC = VGG = 5V, SYNC = VCC, IREF = 0mA, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
EFFICIENCY vs. LOAD CURRENT EFFICIENCY vs. LOAD CURRENT EFFICIENCY vs. LOAD CURRENT
(1.7V/7A CIRCUIT) (2.5V/3A CIRCUIT) (2.5V/2A CIRCUIT)
100 100 100
MAX1637-03
MAX1637-01
MAX1637-02
SKIP = LOW VBATT = 22V SKIP = LOW
SKIP = LOW 90
90 VBATT = 7V 80 90 VBATT = 7V
VBATT = 15V
70 VBATT = 7V
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
80 60 80
VBATT = 22V 50
VBATT = 15V VBATT = 22V
70 40 70 VBATT = 15V
30
60 20 60
10
50 0 50
0.01 0.1 1 10 0.001 0.01 0.1 1 10 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
VOUT = 3.3V
90
15 15
EFFICIENCY (%)
50 0 0
0.01 0.1 1 10 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 1 2 3 4 5 6 7 8 9
LOAD CURRENT (A) SUPPLY VOLTAGE (V) LOAD CURRENT (A)
4 _______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
____________________________________Typical Operating Characteristics (continued)
MAX1637
(VOUT = 3.3V, TA = +25°C, unless otherwise noted.)
MAX1637-09
MAX1637-10
MAX1637-08
8 VOUT FORCED TO 3.27V
800
0.5 SYNC = VCC
REF LOAD REGULATION ΔV (mV)
LOAD REGULATION ΔVOUT (mV)
6 700
-10 0 0
0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10
LOAD CURRENT (A) REF LOAD CURRENT (μA) LOAD CURRENT (A)
VOUT VOUT
50mV/div 50mV/div
4A
LOAD
2A CURRENT 10A
0A 5A LOAD CURRENT
0A
100μs/div 100μs/div
5V 5V
VLX
VLX VLX 2V/div
0V 0V
1A 1A 1A
INDUCTOR INDUCTOR INDUCTOR
CURRENT CURRENT CURRENT
0A 0A 0A
VOUT FORCED TO 3.27V
20μs/div 1μs/div
1μs/div
_______________________________________________________________________________________ 5
Miniature, Low-Voltage,
Precision Step-Down Controller
MAX1637
OVERVOLTAGE-PROTECTION WAVEFORMS
TIME EXITING SHUTDOWN (VIN SHORTED TO VOUT
(VOUT = 3.3V, ILOAD = 7A) THROUGH A 0.5Ω RESISTOR)
MAX1637-16
MAX1637-17
VOUT
100mV/div
VOUT
1V/div 5V
VDL
0V
0A
INDUCTOR
VSHDN -5A
CURRENT
5V/div -10A
500μs/div 10μs/div
______________________________________________________________Pin Description
PIN NAME FUNCTION
1 CSH High-Side Current-Sense Input
2 CSL Low-Side Current-Sense Input
3 FB Feedback Input. Connect to center of resistor divider.
4 CC Compensation Pin. Connect a small capacitor to GND to set the integration time constant.
5 REF 1.100V Reference Output. Capable of sourcing 50µA for external loads. Bypass with 0.22µF minimum.
Shutdown Control Input. Turns off entire IC. When low, reduces supply current below 0.5µA (typ). Drive with
6 SHDN
logic input or connect to RC network between GND and VCC for automatic start-up.
Oscillator Frequency Select and Synchronization Input. Tie to VCC for 300kHz operation; tie to GND for
7 SYNC
200kHz operation.
8 GND Analog Ground
Main Analog Supply-Voltage Input to the Chip. VCC powers the PWM controller, logic, and reference. Input
9 VCC
range is 3.15V to 5.5V. Bypass to GND with a 0.1µF capacitor close to the pin.
Gate-Drive and Boost-Circuit Power Supply. Can be driven from a supply other than VCC. If the same supply
10 VGG is used by both VCC and VGG, isolate VCC from VGG with a 20Ω resistor. Bypass to PGND with a 4.7µF
capacitor. VGG current = (QG1 + QG2) x f, where QG is the MOSFET gate charge at VGS = VGG.
11 DL Low-Side Gate-Driver Output
12 PGND Power Ground
13 BST Boost Capacitor Connection
14 DH High-Side Gate-Driver Output
15 LX Inductor Connection
16 SKIP Low-Noise Mode Control. Forces fixed-frequency PWM operation when high.
6 _______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
MAX1637
VBIAS
VBATT
+5V
NOMINAL
20Ω
VCC
4.7μF
SYNC
VGG
0.1μF C1
MAX1637 CMPSH-3
470pF BST
CC DH Q1
0.1μF
REF L1 R1 OUTPUT
LX
1μF
SKIP DL Q2 C2
*
GND PGND
CSH
CSL
1M** R2
ON/OFF
SHDN FB
0.01μF**
R3
*SEE RECTIFIER CLAMP DIODE SECTION
**OPTIONAL RC NETWORK FOR POWER-ON-RESET
_______________________________________________________________________________________ 7
Miniature, Low-Voltage,
Precision Step-Down Controller
MAX1637
8 _______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
MAX1637
VBATT
3.15V TO 5.5V
VBIAS
+
VCC SYNC SKIP
IC
MAX1637
VGG
POWER
BST
200kHz
TO
300kHz DH
OSC PWM LX
VOUT
LOGIC
DL +
PGND
REF 1.1V
REF.
SHDN SHUTDOWN
CONTROL
OFF + CSH
CSL
REF -
UNDER-
SLOPE ERROR
VOLTAGE
COMPENSATION INTEGRATOR
FAULT CC
gm
-
+
OVERVOLTAGE
- FAULT
+
REF
VREF -30% -
+
VREF +7% FB
60kHz
LP FILTER
GND
The pulse-width-modulation (PWM) controller consists cision reference. The circuit blocks are powered from
of a multi-input PWM comparator, high-side and low- an internal IC power rail that receives power from VCC.
side gate drivers, and logic. It uses a 200kHz/300kHz VGG provides direct power to the synchronous-switch
synchronizable oscillator. The MAX1637 contains fault- gate driver, but provides indirect power to the high-
protection circuits that monitor the PWM output for side-switch gate driver via an external diode-capacitor
undervoltage and overvoltage. It includes a 1.100V pre- boost circuit.
_______________________________________________________________________________________ 9
Miniature, Low-Voltage,
Precision Step-Down Controller
MAX1637
CSH
1X
CSL
FB
2X
REF
REF
gm
CC
BST
R
Q LEVEL DH
S SHIFT
LX
OSC
SLOPE
COMPENSATION
30mV
SKIP
SOFT-START
SYNCHRONOUS
RECTIFIER CONTROL
VGG
R Q
LEVEL DL
-100mV
S SHIFT
PGND
PWM Controller Block compensation ramp (Figure 3). The PWM controller is
The heart of the current-mode PWM controller is a a direct-summing type, lacking a traditional error
multi-input, open-loop comparator that sums four sig- amplifier and the phase shift associated with it. This
nals: the output voltage error signal with respect to direct-summing configuration approaches ideal
the reference voltage, the current-sense signal, the cycle-by-cycle control over the output voltage.
integrated voltage-feedback signal, and the slope-
10 ______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
Idle Mode Table 3. SKIP PWM Table
MAX1637
When SKIP is low, idle-mode circuitry automatically
optimizes efficiency throughout the load-current range. LOAD
SKIP MODE DESCRIPTION
Idle mode dramatically improves light-load efficiency CURRENT
by reducing the effective frequency, subsequently Pulse-skipping, discontin-
reducing switching losses. It forces the peak inductor Low Light Idle
uous inductor current
current to ramp to 30% of the full current limit, deliver-
ing extra energy to the output and allowing subsequent Constant frequency PWM,
Low Heavy PWM
continuous inductor current
cycles to be skipped. Idle mode transitions seamlessly
to fixed-frequency PWM operation as load current Constant frequency PWM,
High Light PWM
increases (Table 3). continuous inductor current
VCC
R1 R2
TO PWM
LOGIC
UNCOMPENSATED
CC FB HIGH-SPEED
LEVEL TRANSLATOR
AND BUFFER
OUTPUT DRIVER
I1 I2 I3 I4 VBIAS
REF
CSH
CSL
SLOPE COMPENSATION
______________________________________________________________________________________ 11
Miniature, Low-Voltage,
Precision Step-Down Controller
REF, VCC, and VGG Supplies If the circuit is operating in continuous-conduction
MAX1637
The 1.100V reference (REF) is accurate to ±2% over mode, the DL drive waveform is simply the complement
temperature, making REF useful as a precision system of the DH high-side-drive waveform (with controlled
reference. Bypass REF to GND with a 0.22µF (min) dead time to prevent cross-conduction or “shoot-
capacitor. REF can supply up to 50µA for external through”). In discontinuous (light-load) mode, the syn-
loads. Loading REF reduces the main output voltage chronous switch is turned off as the inductor current
slightly because of the reference load-regulation error. falls through zero.
The MAX1637 has two independent supply pins, VCC Shutdown Mode and Power-On Reset
and VGG. VCC powers the sensitive analog circuitry of SHDN is a logic input with a threshold of about 1.5V
the SMPS, while VGG powers the high-current MOSFET that, when held low, places the IC in its 0.5µA shut-
drivers. No protection diodes or sequencing require- down mode. The MAX1637 has no power-on-reset cir-
ments exist between the two supplies. Isolate VGG from cuitry, and the state of the device is not known on initial
VCC with a 20Ω resistor if they are powered from the power-up. In applications that use logic to drive SHDN,
same supply. Bypass VCC to GND with a 0.1µF capaci- it may be necessary to toggle SHDN to initialize the
tor located directly adjacent to the pin. Use only small- part once VCC is stable. In applications that require
signal diodes for the boost circuit (10mA to 100mA automatic start-up, drive SHDN through an external RC
Schottky or 1N4148 diodes are preferred), and bypass network (Figure 5). The network will hold SHDN low
VGG to PGND with a 4.7µF capacitor directly at the until VCC stabilizes. Typical values for R and C are 1MΩ
package pins. The VCC and VGG input range is 3.15V and 0.01µF. For slow-rising VCC, use a larger capacitor.
to 5.5V. When cycling VCC, VCC must stay low long enough to
High-Side Boost Gate Drive (BST) discharge the 0.01µF capacitor, otherwise the circuit
Gate-drive voltage for the high-side N-channel switch is may not start. A diode may be added in parallel with
generated by a flying-capacitor boost circuit (Figure 2). the resistor to speed up the discharge.
The capacitor between BST and LX is alternately Current-Limiting and Current-
charged from the VGG supply and placed parallel to Sense Inputs (CSH and CSL)
the high-side MOSFET’s gate-source terminals. The current-limit circuit resets the main PWM latch and
On start-up, the synchronous rectifier (low-side turns off the high-side MOSFET switch whenever the
MOSFET) forces LX to 0V and charges the boost voltage difference between CSH and CSL exceeds
capacitor to VGG. On the second half-cycle, the SMPS 100mV. This limiting is effective for both current flow
turns on the high-side MOSFET by closing an internal directions, putting the threshold limit at ±100mV. The
switch between BST and DH. This provides the neces- tolerance on the positive current limit is ±20%, so the
sary enhancement voltage to turn on the high-side external low-value sense resistor (R1) must be sized for
switch, an action that boosts the gate-drive signal 80mV / IPEAK, where IPEAK is the peak inductor current
above the battery voltage. required to support the full load current. Components
Ringing at the high-side MOSFET gate (DH) in discon- must be designed to withstand continuous current
tinuous-conduction mode (light loads) is a natural oper- stresses of 120mV / R1.
ating condition. It is caused by residual energy in the
tank circuit, formed by the inductor and stray capaci-
tance at the switching node, LX. The gate-drive nega- VIN
tive rail is referred to LX, so any ringing there is directly
coupled to the gate-drive output. VGG VCC
R
Synchronous-Rectifier Driver (DL)
Synchronous rectification reduces conduction losses in SHDN
the rectifier by shunting the normal Schottky catch C
diode with a low-resistance MOSFET switch. Also, the MAX1637
synchronous rectifier ensures proper start-up of the
boost gate-driver circuit. If the synchronous power
MOSFET is omitted for cost or other reasons, replace it R = 1MΩ
with a small-signal MOSFET, such as a 2N7002. C = 0.01μF
12 ______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
For prototyping or for very high-current applications, it summed into the PWM comparator, with the gain
MAX1637
may be useful to wire the current-sense inputs with a weighted so that the signal has only enough gain to
twisted pair rather than PC traces (two pieces of correct the DC inaccuracies. The integrator’s response
wrapped wire twisted together are sufficient). This time is determined by the time constant set by the
reduces the noise picked up at CSH and CSL, which can capacitor placed on the CC pin. The time constant
cause unstable switching and reduced output current. should neither be so fast that the integrator responds to
the normal VOUT ripple, nor too slow to negate the inte-
Oscillator Frequency grator’s effect. A 470pF to 1500pF CC capacitor is suf-
and Synchronization (SYNC) ficient for 200kHz to 300kHz frequencies.
The SYNC input controls the oscillator frequency as fol-
lows: low selects 200kHz, high selects 300kHz. SYNC Figure 6 shows the output voltage response to a 0A to
can also be used to synchronize with an external 5V 3A load transient with and without the integrator. With
CMOS or TTL clock generator. It has a guaranteed the integrator, the output voltage returns to within 0.1%
240kHz to 340kHz capture range. A high-to-low transi- of its no-load value with only a small AC excursion.
tion on SYNC initiates a new cycle. Without the integrator, load regulation is degraded
(Figure 6b). Asymmetrical clamping at the integrator
Operation at 300kHz optimizes the application circuit output prevents worsening of load transients during
for component size and cost. Operation at 200kHz pulse-skipping mode.
increases efficiency, reduces dropout, and improves
load-transient response at low input-output voltage dif- Output Undervoltage Lockout
ferences (see the Low-Voltage Operation section). The output undervoltage-lockout circuit protects
against heavy overloads and short-circuits at the main
Output Voltage Accuracy (CC) SMPS output. This scheme employs a timer rather than
Output voltage error is guaranteed to be within ±2% a foldback current limit. The SMPS has an undervolt-
over all conditions of line, load, and temperature. The age-protection circuit, which is activated 6144 clock
MAX1637’s DC load regulation is typically better than cycles after the SMPS is enabled. If the SMPS output is
0.1%, due to its integrator amplifier. The device opti- under 70% of the nominal value, it is latched off and
mizes transient response by providing a feedback sig- does not restart until SHDN is toggled. Applications
nal with a direct path from the output to the main that use the recommended RC power-on-reset circuit
summing PWM comparator. The integrated feedback will also clear the fault condition when VCC falls below
signal from the CC transconductance amplifier is also 0.5V (typical). Note that undervoltage protection can
VOUT VOUT
(mV) (mV)
-50 -50
4 4
IOUT IOUT
(A) 2 (A) 2
0 0
(100μs/div) (100μs/div)
Figure 6a. Load-Transient Response with Integrator Active Figure 6b. Load-Transient Response with Integrator
Deactivated
______________________________________________________________________________________ 13
Miniature, Low-Voltage,
Precision Step-Down Controller
make prototype troubleshooting difficult since only The exact time of the output rise depends on output
MAX1637
20ms or 30ms elapse before the SMPS is latched off. capacitance and load current, but it is typically 1ms
The overvoltage crowbar protection is disabled in out- with a 300kHz oscillator.
put undervoltage mode.
Setting the Output Voltage
Output Overvoltage Protection The output voltage is set via a resistor divider connect-
The overvoltage crowbar-protection circuit is intended ed to FB (Figure 1). Calculate the output voltage with
to blow a fuse in series with the battery if the main the following formula:
SMPS output rises significantly higher than its standard VOUT = VREF (1 + R2 / R3)
level (Table 4). In normal operation, the output is com-
pared to the internal precision reference voltage. If the where VREF = 1.1V nominal.
output goes 7% above nominal, the synchronous-recti- Recommended normal values for R3 range from 5kΩ to
fier MOSFET turns on 100% (the high-side MOSFET is 100kΩ. To achieve a 1.1V nominal output, connect FB
simultaneously forced off) in order to draw massive directly to CSL. Remote output voltage sensing is pos-
amounts of battery current to blow the fuse. This safety sible by using the top of the external resistor divider as
feature does not protect the system against a failure of the remote sense point.
the controller IC itself, but is intended primarily to guard
against a short across the high-side MOSFET. A crow- __________________Design Procedure
bar event is latched and can only be reset by a rising The standard application circuit (Figure 1) contains a
edge on SHDN (or by removal of the VCC supply volt- ready-to-use solution for common application needs.
age). The overvoltage-detection decision is made rela- Use the following design procedure to optimize the
tive to the regulation point. basic schematic for different voltage or current require-
ments. But before beginning a design, firmly establish
Internal Digital Soft-Start Circuit the following:
Soft-start allows a gradual increase of the internal cur-
rent-limit level at start-up to reduce input surge cur- • Maximum input (battery) voltage, V IN(MAX) . This
rents. The SMPS contains an internal digital soft-start value should include the worst-case conditions, such
circuit controlled by a counter, a digital-to-analog con- as no-load operation when a battery charger or AC
verter (DAC), and a current-limit comparator. In shut- adapter is connected but no battery is installed.
down, the soft-start counter is reset to zero. When the VIN(MAX) must not exceed 30V.
SMPS is enabled, its counter starts counting oscillator • Minimum input (battery) voltage, VIN(MIN). This value
pulses, and the DAC begins incrementing the compari- should be taken at full load under the lowest battery
son voltage applied to the current-limit comparator. The conditions. If the minimum input-output difference is
DAC output increases from 0mV to 100mV in five equal less than 1.5V, the filter capacitance required to
steps as the count increases to 512 clocks. As a result, maintain good AC load regulation increases (see
the main output capacitor charges up relatively slowly. Low-Voltage Operation section).
Run High VOUT in regulation All circuit blocks active Normal operation
Shutdown Low — All circuit blocks off Lowest current consumption
Overvoltage VOUT greater than 7% Rising edge on SHDN exits
High REF = off, DL = high
(Crowbar) above regulation point crowbar
Output VOUT below 70% of
Rising edge on SHDN exits
Undervoltage High nominal after 20ms to REF = off, DL = low
UVLO
Lockout 30ms timeout expires
14 ______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
Inductor Value be acceptable, even at 300kHz. For high-current appli-
MAX1637
The exact inductor value is not critical and can be cations, shielded-core geometries (such as toroidal or
freely adjusted to allow trade-offs among size, cost, pot core) help keep noise, EMI, and switching-
and efficiency. Lower inductor values minimize size waveform jitter low.
and cost, but reduce efficiency due to higher peak-
current levels. The smallest inductor value is obtained Current-Sense Resistor Value
by lowering the inductance until the circuit operates at The current-sense resistor value is calculated accord-
the border between continuous and discontinuous ing to the worst-case, low-current limit threshold volt-
mode. Further reducing the inductor value below this age (from the Electrical Characteristics) and the peak
crossover point results in discontinuous-conduction inductor current:
operation, even at full load. This helps lower output filter RSENSE = 80mV / IPEAK
capacitance requirements, but efficiency suffers under Use IPEAK from the second equation in the Inductor
these conditions, due to high I2R losses. On the other Value section. Use the calculated value of RSENSE to
hand, higher inductor values produce greater efficien- size the MOSFET switches and specify inductor satura-
cy, but also result in resistive losses due to extra wire tion-current ratings according to the worst-case high-
turns—a consequence that eventually overshadows the current-limit threshold voltage:
benefits gained from lower peak current levels. High
inductor values can also affect load-transient response IPEAK = 120mV / RSENSE
(see the VSAG equation in the Low-Voltage Operation Low-inductance resistors, such as surface-mount metal
section). The equations in this section are for continu- film, are recommended.
ous-conduction operation.
Input Capacitor Value
Three key inductor parameters must be specified: Connect low-ESR bulk capacitors directly to the drain
inductance value (L), peak current (IPEAK), and DC on the high-side MOSFET. The bulk input filter capaci-
resistance (R DC). The following equation includes a tor is usually selected according to input ripple current
constant, LIR, which is the ratio of inductor peak-to- requirements and voltage rating, rather than capacitor
peak AC current to DC load current. A higher LIR value value. Electrolytic capacitors with low enough equiva-
allows lower inductance, but results in higher losses lent series resistance (ESR) to meet the ripple-current
and ripple. A good compromise is a 30% ripple-current requirement invariably have sufficient capacitance val-
to load-current ratio (LIR = 0.3), which corresponds to a ues. Aluminum electrolytic capacitors, such as Sanyo
peak inductor current 1.15 times higher than the DC OS-CON or Nichicon PL, are superior to tantalum
load current. types, which risk power-up surge-current failure, espe-
L = VOUT(VIN(MAX) - VOUT) / (VIN(MIN) x ƒ x IOUT x cially when connecting to robust AC adapters or low-
LIR) impedance batteries. RMS input ripple current (IRMS) is
where ƒ = switching frequency (normally 200kHz or determined by the input voltage and load current, with
300kHz), and IOUT = maximum DC load current. the worst case occurring at VIN = 2 x VOUT. Therefore,
when VIN is 2 x VOUT:
The peak current can be calculated as follows:
IRMS = ILOAD / 2
IPEAK = ILOAD + [VOUT(VIN(MAX) - VOUT) / (2 x ƒ x L
x VIN(MAX))] VCC and VGG should be isolated from each other with a
20Ω resistor and bypassed to ground independently.
The inductor’s DC resistance should be low enough Place a 0.1µF capacitor between VCC and GND, as
that RDC x IPEAK < 100mV, as it is a key parameter for close to the supply pin as possible. A 4.7µF capacitor
efficiency performance. If a standard, off-the-shelf is recommended between VGG and PGND.
inductor is not available, choose a core with an LI2 rat-
ing greater than L x IPEAK2 and wind it with the largest Output Filter Capacitor Value
diameter wire that fits the winding area. For 300kHz The output filter capacitor values are generally deter-
applications, ferrite-core material is strongly preferred; mined by the ESR and voltage-rating requirements,
for 200kHz applications, Kool-Mu® (aluminum alloy) or rather than by actual capacitance requirements for loop
even powdered iron is acceptable. If light-load efficien- stability. In other words, the low-ESR electrolytic capac-
cy is unimportant (in desktop PC applications, for itor that meets the ESR requirement usually has more
example), then low-permeability iron-powder cores can output capacitance than is required for AC stability.
______________________________________________________________________________________ 15
Miniature, Low-Voltage,
Precision Step-Down Controller
Use only specialized low-ESR capacitors intended for Selecting Other Components
MAX1637
16 ______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
Rectifier Clamp Diode added capacitance can be supplied by a low-cost bulk
MAX1637
The rectifier is a clamp across the low-side MOSFET capacitor in parallel with the normal low-ESR capacitor.
that catches the negative inductor swing during the
60ns dead time between turning one MOSFET off and __________Applications Information
turning each low-side MOSFET on. The latest genera- Heavy-Load Efficiency Considerations
tions of MOSFETs incorporate a high-speed silicon The major efficiency-loss mechanisms under loads are
body diode, which serves as an adequate clamp diode as follows, in the usual order of importance:
if efficiency is not of primary importance. A Schottky
diode can be placed in parallel with the body diode to • P(I2R) = I2R losses
reduce the forward voltage drop, typically improving • P(tran) = transition losses
efficiency 1% to 2%. Use a diode with a DC current rat- • P(gate) = gate-charge losses
ing equal to one-third of the load current; for example,
use an MBR0530 (500mA-rated) type for loads up to • P(diode) = diode-conduction losses
1.5A, a 1N5819 type for loads up to 3A, or a 1N5822 • P(cap) = capacitor ESR losses
type for loads up to 10A. The rectifier’s rated reverse- • P(IC) = losses due to the IC’s operating supply current
breakdown voltage must be at least equal to the maxi-
mum input voltage, preferably with a 20% margin. Inductor core losses are fairly low at heavy loads
because the inductor’s AC current component is small.
Boost-Supply Diode D2 Therefore, these losses are not considered in this
A signal diode such as a 1N4148 works well in most analysis. Ferrite cores are preferred, especially at
applications. Do not use large power diodes, such as 300kHz, but powdered cores, such as Kool-Mu, can
1N5817 or 1N4001. also work well.
Low-Voltage Operation Efficiency = POUT / PIN x 100%
Low input voltages and low input-output differential volt- = POUT / (POUT + PTOTAL) x 100%
ages each require extra care in their design. Low PTOTAL = P(I2R) + P(tran) + P(gate) + P(diode) +
VIN-VOUT differentials can cause the output voltage to P(cap) + P(IC)
sag when the load current changes abruptly. The sag’s
amplitude is a function of inductor value and maximum P = (I R) = ILOAD2 x (RDC + RDS(ON) +RSENSE)
2
duty factor (DMAX, an Electrical Characteristics parame- where RDC is the DC resistance of the coil, RDS(ON) is
ter, 93% guaranteed over temperature at f = 200kHz) as the MOSFET on-resistance, and RSENSE is the current-
follows: sense resistor value. The RDS(ON) term assumes iden-
VSAG = [(ISTEP)2 x L] / [2CF x (VIN(MIN) x DMAX - tical MOSFETs for the high-side and low-side switches
VOUT)] because they time-share the inductor current. If the
MOSFETs are not identical, their losses can be estimat-
Table 5 is a low-voltage troubleshooting guide. The ed by averaging the losses according to duty factor.
cure for low-voltage sag is to increase the output
capacitor’s value. For example, at VIN = 5.5V, VOUT = PD(tran) = transition loss = V IN x I LOAD x ƒ x
5V, L = 10µH, ƒ = 200kHz, and ISTEP = 3A, a total [(VIN CRSS / IGATE ) + 20ns]
capacitance of 660µF keeps the sag below 200mV. where CRSS is the reverse transfer capacitance of the
Note that only the capacitance requirement increases; high-side MOSFET (a data sheet parameter), IGATE is
the ESR requirements do not change. Therefore, the the DH gate-driver peak output current (1.5A typ), and
the rise/fall time of the DH driver is typically 20ns.
______________________________________________________________________________________ 17
Miniature, Low-Voltage,
Precision Step-Down Controller
P(gate) = Qg x ƒ x VGG and VCC. Also, heavy current surges from the input
MAX1637
where Qg is the sum of the gate-charge values for low- may cause transient dips on VCC. To prevent this, the
side and high-side switches. For matched MOSFETs, decoupling capacitor on V CC may need to be
Q g is twice the data-sheet value of an individual increased to 2µF or greater. This circuit uses low-
MOSFET. Efficiency can usually be optimized by con- threshold (specified at VGS = 2.7V) IRF7401 MOSFETs
necting VGG to the most efficient 5V source, such as which allow a typical startup of 3.15V at above 4A. Low
the system +5V supply. input voltages demand the use of larger input capaci-
tors. Sanyo OS-CONs are recommended for their high
P(diode) = diode conduction losses = ILOAD x VFWD capacity and low ESR.
x tD x ƒ
where tD is the diode conduction time (120ns typ), and PC Board Layout Considerations
VFWD is the diode forward voltage. This power is dissi- Good PC board layout is required to achieve specified
pated in the MOSFET body diode if no external noise, efficiency, and stable performance. The PC
Schottky diode is used. board layout artist must be given explicit instructions,
preferably a pencil sketch showing the placement of
P(cap) = input capacitor ESR loss = IRMS2 x RESR power-switching components and high-current routing.
where IRMS is the input ripple current as calculated in See the PC board layout in the MAX1637 evaluation kit
the Input Capacitor Value section. manual for examples. A ground plane is essential for
optimum performance. In most applications, the circuit
Light-Load Efficiency Considerations will be located on a multi-layer board, and full use of
Under light loads, the PWM operates in discontinuous the four or more copper layers is recommended. Use
mode. The inductor current discharges to zero at some the top layer for high-current connections, the bottom
point during the charging cycle. This makes the induc- layer for quiet connections (REF, CC, GND), and the
tor current’s AC component high compared to the load inner layers for an uninterrupted ground plane. Use the
current, which increases core losses and I2R losses in following step-by-step guide:
the input-output filter capacitors. For best light-load effi-
ciency, use MOSFETs with moderate gate-charge lev- 1) Place the high-power components (C1, C2, Q1, Q2,
els and use ferrite MPP or other low-loss core material. D1, L1, and R1) first, with their grounds adjacent.
Avoid powdered-iron cores; even Kool-Mu (aluminum • Minimize current-sense resistor trace lengths and
alloy) is not as desirable as ferrite. ensure accurate current sensing with Kelvin con-
nections (Figure 8).
Low-Noise Operation
Noise-sensitive applications such as hi-fidelity multi- • Minimize ground trace lengths in the high-current
media-equipped systems, cellular phones, RF commu- paths.
nicating computers, and electromagnetic pen-entry • Minimize other trace lengths in the high-current
systems should operate the controller in PWM mode paths.
(SKIP = high). This mode forces a constant switching — Use >5mm-wide traces.
frequency, reducing interference due to switching
noise by concentrating the radiated EM fields at a — CIN to high-side MOSFET drain: 10mm
known frequency outside the system audio or IF bands. max length
Choose an oscillator frequency for which switching- — Rectifier diode cathode to low side
frequency harmonics do not overlap a sensitive fre- — MOSFET: 5mm max length
quency band. If necessary, synchronize the oscillator
to a tight-tolerance external clock generator. — LX node (MOSFETs, rectifier cathode, induc-
tor): 15mm max length
Powering From a Single Ideally, surface-mount power components are butted
Low-Voltage Supply up to one another with their ground terminals almost
The circuit of Figure 7 is powered from a single 3.3V to touching. These high-current grounds are then con-
5.5V source and delivers 4A at 2.5V. At input voltages nected to each other with a wide, filled zone of
of 3.15V, this circuit typically achieves efficiencies of top-layer copper so they do not go through vias. The
90% at 3.5A load currents. When using a single supply resulting top-layer subground plane is connected to the
to power both VBATT and VBIAS, be sure that it does not normal inner-layer ground plane at the output ground
exceed the 5.5V rating (6V absolute maximum) for VGG terminals, which ensures that the IC’s analog ground is
18 ______________________________________________________________________________________
Miniature, Low-Voltage,
Precision Step-Down Controller
MAX1637
20Ω VBIAS 3.15V TO 5.5V
4.7μF
TANTALUM
1μF
220μF
VCC VGG OS-CON
SYNC CMPSH-3
SKIP
BST
0.1μF
MAX1637 DH IRF7401
20mΩ
10μH 1% OUTPUT = 2.5V AT 4A
LX
CDHR125-100
DL IRF7401
MBRS130 470μF
SHDN LOW ESR
ON/OFF 130k TANTALUM
PGND 1%
CSH
REF
CSL
1μF GND CC FB
470pF 100k
1%
______________________________________________________________________________________ 19
Miniature, Low-Voltage,
Precision Step-Down Controller
MAX1637
________________________________________________________Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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