caicteesia chen to ARM Cortey ND eeanees - Grtex 2 on advanced micrecontvalley in ARM family , developed by ARMVT arvchttecture - Cortex farnly ts Avb-diided into three Aub- families - ARM CoRTEX AX- Series - ARM CoRTEX Rx- Seticn ~ ARM CoRTEx Mx- Serie X indicates a number that identities in detail the Core These ARM james eve diuded into three macro tombe. Clanarce EmbedJe J Application ARM Procesfora Cortex Procesrsra Cortex Proceasgr, wa oy (cortex < Korea g é at} Laan4 Capabilityte Cortex _ Application ‘Cie - Cortex A-Senen " These Pprocestora delwer exception Performance upts 2GHZ* typ eal freqmency In advanced Process nodes, tnabl "3 dhe next een aliee of mobile mternet devices - There Procerrora ave available in Su cies and multi- Core Vertien scelivenne upto & processing unila wth option NEON muthmecha Brean itera cc and advanced Flo acting pont exe cetion unih Applicationn - Smart Phones | Dien TV, Smartbookn & N@etbocks , Home Gotesayr » e-beek readers , Sevvera ete. ~ Support for Gmplex 05 and uner applicationa - Supports ARM, Thumb and Thumb 2 inatruction acts 2. ARM Cortex Embedded Proce anova - Covtex R-Series - Provider enceptond Performance Lar real-time application where theve 14 a need por low power aad deed ioteroet behaviewr and Provide Gmpatbilty wtb existing Placttoren zAppheations - Automotive braking Dystema, Power train Solutions Mann Storage Conteller (De Drives) Netitortng & Taatog , Digrtal Camerar ete Thumb and Thumb-2 instruction Acts = Cotter RX Belivers Including ARMN, eng Covtexy M- Sener - Supporh agen, % voad map trom classic ARM Procenaor, a6 emisting applications te be cantly ported te o higher Pe vtormona, Plater - Gost pensitive aolutiona for determimatic mmicvetortroller applications where the need for fast, neat dete rmanistie, Inte wrupt management © Goupled sath the dearee for extemly lows ote Goat and lowest ponaible Power Consumption. Applicationa - Microcontrollers, Mined Sipe Deuces, Smart Senrery , Avtometive body electronies and arbapa Cortex MX in diuded into hee eur teapon eae are Mo, MI1,M3 and My. The power Grrumption of Cortex Mew 9 the Yange of 0-84 Dmips/ oz to L25 DMs) mHz Embedded Procemeore “ve Promarily focused on nigh dletermininte Yeal time behavior with Power Denaitevely eel an Rtos alengaide Unrer- tpn & Memer, 7 Protechon unit (Mes) an opposed to MMi in as cites execute developed application cde ond hence a iComparison of Cortex . A Procen row family ARM Cove Year of Eatoblishment ARM Architecture No. of Tnatruction Pipeline Stages External intertaces used ATB - Advanced Trace Bur AS AMBA Ax! Aes, APB OFT Al dell ARM VT Ace APB DET MBIST APB - Advancea Rrpheral Bur Compartaon ek ARM Cove Yeor } Extablishmest ARM Architecture Memory Architecture No- of Instruction Pipeline ste ge2 Mox. Clock Hepancy Ag Aq 2005 2007 ARMVT ARM ta(ateger) F lo (nicons) AMBA Axt — AMBA AXI AMBA APB Debug V1- AMBA ATER Complaiet leer. OFT DFT Cortex. RQ oonily of Reocesnora Ry Do! ARM VT Harvard AVUGAZ RS Zou ARM VT Harvard yy GAZ Re RI 2ol 20l6 ARMut Agu 7 Harvard Harvard uy 8 yh Gaz >eSGHZCompanson of ARM Corte mM Family of Qrocearora ARM Core Mo ei ee - ss Year o 2004 Doag eas ue aie Entoblishment ARM viE-M ARM Avehitectare ARMVE-M ARMVE-M — ARMUT-M ARMvIe-M Hare a) Von Neuman Von-Neuman Henord Harvard Architecture 6 No.of infttruction 3 3 3 3 Pipeline Steger ic Toterrup te (Gar \ te 240 Ite 240 “ (xm) Cnr) (nm) (nim) ot Gene lg cycler 23 frst a el letency 1 2b Pr (RQ MicreGontroll ex Toahiba leo —— yeilnx Spartan-3 Nxplpc ideo Toslnbext ot inne70 chips bared on NxP LPe Noe Alter Cyclone-T. Toshiba Tkos Axe v3 i i a 1 Kioeken ne eee Lavoo |e Actelsmort cing, ee Soc uy HawWerd vs Von- Neumann Architectare Havvar 4 alae \ Seperate buren for instruction and date fetehias 2- Eary te Prpelne, Ao Dyk Performona. con be acheive d 3- Compartuely Hyh cost 1 Single Ahared bea for inctrection anddoto fetching 2 Low Performance Compared Harvard BechenperHorvevd Von-Neumann No memory ier! problema | 4 Allows elf rnedisy ng Giza Since data memory and Peon 5. Since data mersery and program memory ate alored phyareally meiery ave atored phyacaly in in ethene ap locations, no chenar dhyel nance riba joe weedy He ec aeta carats il corcapteant ey Program merry. Program memory ARM Covtex-M Architective (Typreatty M3 & My ove most Avceeatsl) Features ot M3 & My - 32 bit vegulers - 82 bit intemal deta Path > 82 bit Bus Interface unit — Thumb ISA (instuction set avehrectue)) — Thumb > - Tree stage pipeline Deagn including branch freed & Speci - Horvard architectwe tain Umbtec memory apace 32 bt addvenamny, Aupporting Goa of memory APA - Onehip bus tevbaces based on ARM Ampa ( Advanced Micve Grtroller Bus Avchitecture ) - An intevvupt Controtled Called Nvic (Nested Vector wite vrupi Controller ) etn upte 240 mtorr upt vepuersta and IR tol Sie “inttewasetopuaeita levelas= Supper Jor Vanous features jor os implementation Aveh 24 Syatem tic timer, Ahadowed stack pomber ete - Sleep mode Support and Venous low power features - Svpport Pr a7 optional Memory Protection unit (mie) te Proude memory Protection jeatwen hee Programmable memory s access Permunion CGontvo)- intewropt Cortex m3[mbs Procemer Contvalle” Looting Pout Soe Embedded Trace Macvotet! Cet) doa pom System Bun Bun mies eee rr Pro! en Memory Caan Penph eicls)) Nested Vectors Tritenupt Contielley (atvic) - Faster intewopt veapenae wrth leos Aobtioa re ether - ineyeles , detemimutec and low letteney> Tntewwpt Service Routines are Atandard © functions - Tntewupt toble ws Arimply a ret of potntera te © voutine, - An nee ete Nutc handles ig Savery Corruphble vepusters - Exception provetization ~ Encephon Nesting Weke-up Interrupt Controlley (re) = optional ~ Allowe precearoy te be powered down and power op When vegreate d Enables nid power Conmuption m deep Sleep mode wth natant Wake op: -Cortex.M supports sleep mode and Deep Skep mode. ~ Enter Sleep uae net] Hee matrction oy “Sleep -on- exit tate rvupt handling , pshich enables the processor t& deep whence all extend tap interyupts are Complete Covter M3] Ms has tio modes 2} ePeration = Normal Program ~ Thumb State — Bunning Rrogram Code ~ Exception handler _ Debug state ~ when pyecemoy ‘is haltel ar) Secunty levels - Base Securcty mode! ~ Can accem ell Yesources in the ProceArov ~ Memory Accenn Protection - Few memery regions & 129 opalon not availabl - Reguater File is Aumlay te traditional ARM but with reduced avea- ~ Within Cane there ave tise Stack pomtera,namely, Main and Procem:wrth Thomb-2 Technology, Covlex-M han a No-o}, edvertofen - No State each overhead, aoing beth execution Hime ant ndtrection apace - No need to apechy ApeAiistects sax. (naebistate - Easy to fet beat SeevCode denarty ef free ney and Perfor mana ot the Aame time Cortes Proceanova do not Come uth memones included - the vender adda them an Prograan Memory - Typically Flaah Oe Memory - TyPcally SRAM Pew Pherotr Cortex implements Qt Bonar 1 & method of Perfprany ostemie bitmine modsfeationa to memory tty preventing data lena earl iwtervupted during & Yead- modify torite Cele Memory Protection Drit (optional) - Has euht memory Begiona Sub vegion Disable , ena blen¢ effecent wre aL memory Yeptony - Ability te enable o background Yepten that im ple ment a The default memory map attribute. Float Pont Unt (FPL) - Opbonas ~ 82 dedrahS2-bit instructions ts Single- Precision deta. (add vessable an 16 doubli werd resister) Beesaning taatruction - Combined Moth aly ows Acecenclate. mittinelevinile os 1occ cd euk~ Hawisave Support for Converaron, addition, subtraction, multipliatio, beth optional accumulate, divuton and avereroot - Decoupled three Stage pipet me Low Coat Debug Subsystem (optionat) ~ Debug ee Ay) memory eel regintero m the ayaten, including accens to memovy mapped devices , aECe7" itor interes Core vegisters shen the Gre is halted and aeceos to de bug Control veg itera faien When SYSRESETe is anterted - Embedded Trace Macrocet] (ETH) - Foy matruction trace Trace Inteypace Unt G20) - tow bridging to a trace povt analyze Ime lading Sugle wre output mode Dnatomentotion Trace Macrocell (ttm) - Support by Print gle eps Deke Watch Rint and Trace (Dut) - For mplementin f betch pointe, deta Trocing and Ay Aten Pret Flash Patch and Breat Pint (eps) - Implementing break pow'ts & Rites Senal Wie Debug /TTAG Deboy Port ~ Debug Accens Bos Snter fo Cen Preceanon Contain four ANB (Advanced High Prlormens us). Lite Bon Irtterjacesraat Poupheced Bua (PRE) - Data and a accens te external PPR Apace, O% E004000d 4%, OXEOOFFFEF ore Performed over Advanced Rripherol BuslARD -Troce Prt Mterbat unit and Vendew apeabe peripherals ave on the bua. ~ Cove alotn aceense s have higher provity then debug aceetne 4 “Only addienr bib necennary te ktode the extermel PPB Ve AvP Ported on thir mberfac. ET™ Interface ~ Simple Connection of Et tte the Proceanox - Provides o Chowne! for natroction trace te 61H AHB “Trace Macvocell Interface ~ Enables Connection op ANB Tyate mocrecell te precerroy ~ Provides channe| br Date trace te HTM Vabog Port ANB-AP Intev}ace = Piedeanoy Caters fans-Ap iwhrbace +e de bag cee -awa4 hye ugh 2m external debug Por + - Seral tive STAG debug Port to a standard Gre aught debug + that 2 Pov “" Gmbines TtAG-Dp and Su-DP (spin interac to Ana -ae)T Cede Memory interlace InAtvuction \etchen from Code memory Space , oxee00ce0o te OXIEFEFFFRE are Performed over this S2-bet buy a Deer ies Cannot accenn thir inter|ace - AW fetehen are Word - wide Ne. o} nat. jetehed per Word depends on the Code Tonal ng and algement +} Gde in memory D Code Memory Interface pat aw debug accem fpaute Code memory pad, ner 990000 to oxieEFEEFE are Performed over they bun Core dot han Pye ey Prionty over ao ettennes Contve\ lepre thin interlace Convertr Cae nes deta and acer accearer into “too ov-three al ipned Beeenne rs dependie onthe Aize and ah fnment + Unabyaed acces Dede hay Dita Priority than Teo d ¢ Sy atem “InterLace ~ Taatvection fetches ,and date and debus accenten to adver anger oxzeooccce to oXDFFFFEFEE and oxeoloooce t, oxFtectt FF ore Performed over hes bu, - ‘The ovder in decreo. ning Pronty for ace airt thin bus & Date Acec ee a Insts eon ond Vector fete he 4 aOUR Proce nrcr- Open Mobile Application fieecons -Ttina platter Comprixed of high. Performance, power Softisa re 5 offer at Procerrora , & vobuat intrastre ctore ond Gmprchersiu Depport network for the vapid development of diperentatedl inte vnet applancen, 256 ane 36 joyeless hendbetr and PDAs and sther muttmedia- enhanced devices Hin = Caakinchen of DEP Core and hugh 4 perormanc RISC Procennor “ The DSP proceascy in autable | ai agne) Preecoalng apples Avch aa APeech capitan, MPEGy Video & Audio play back. Rise Procensor wm purtable fe execution ot Gntrel natry ction» Yepeired fr 65, Man-machime interlace a and os application, - Major ee denen ape uelbe Too Preteanera ia to Yedice the Consumption of power te a laige extent Ter greater battery Ihe and alno DSP & allowed t "hee Avppert trom Rise Precesror-OMAP Architectare Genegel - Purfore Multimedia Denignes| Progrosmmer Enginen Tms320 PSP Dem ner programa omap’s dual proceanor plattorea an aheexa addrenaing a aingle procenvoy (interrater AQM Rise & Texan nat IMs 3r0c DSP) =u 2. OMAP Uren dtandard Bee inter laces (api) fer 44 frendly application developmen! + 3. Multimedia enginen make une of prone fey Te lated Dsp torn, wn the GPP demain % Dsp]aies bridge Govdinaten deta, tlo streams and DSP TaAK Contre! between the prowies and the actual 05p Soffaae to manimize Perprmance writhent Reciicn battler Power. Other Feature» OMAP aoplreatien envivonment ws pully Programmable that allown wireless device oem's Corpinat Equi pment Moansjaduer) independent develepern and Camiern te provide clewnloal able Dohtwa re. vpdrades os atandarda change ov bygn are pod.- No need to develop new Aste havdiare to tmpleme nt change ~ OMAP har an open archrtecture bth Ptordavdized wera, and culated third Party develepero to create new appeal inert avatlable thir 3 party and os native tools wrth TE's uner friendly Code Compo ner Studio (ces) hey rater! development environment (E0E) makes Complete Software development avetladle kr OMAP Hn & she Dsp Advanta ge - BOSP's provide Avpertor Power] performance in Video & Audis application, sy they ove aye! Procenning tanks und DSPs are optmnzed kes aveh Type of applicationn only and Yepuive lean Pponey Per Gele than Rise = Pregrammable DSP's atte developers te implement any avetlable standard wWrthout creadin g naecceptable battery drain - Dse yequiven fewer Inatroctions to tmpleme nt a math-intenstve ve petitive ee, and tt Comes out more inatwetions Per clock cycle venulting wn footer implementation roth lero Power Connumot on.Coupling Dsp wrth Rise - OMAP avehrtecture (i OEM'S accenn to Capabitien of DSP® while alno pravicing Command and Gntvol functions ad which RISC Procenneya ave best suited. Aare : Improves geelty Of baste wiveleaa telephony fonctions and permits twe multimedia mau th Tesking on wireless appliance Dsp [Bios Bridge — Provides apphcation pohtioare develop ev, a Aeamleran cory to use mntevbace to the Dse. Tt allows developer on the RISC te acce rn and Gntv) the DSP vuntime envivonment nene a standardized API - No need fr the developRems to Program fer tee Procemon independ ently ov +0 wavk in more. Aye ult bopper Dometimes amociate d sacth Dsp's Open Arvehitectuve - once an application ia developed br oMAp Hata OSandexds ted APL, if will be Compatible svn future end epuipments bared en OMAP architectuve, Rae yeune . TE supports Javea in OMAP architecture and makes Psp/ates bide APL acceraible to developera “4 java media players