Delayed Locked Loop Design Issues

Chulwoo Kim
ckim@korea.ac.kr
Advanced Integrated Systems Lab
Korea University
 Outline
z Introduction
z DLL operation and control theory
z DLL building blocks
z DLL design issues
z Multiplying DLL

2 AISL
 DLL vs PLL
z PLL z DLL
- VCO + VCDL
9 jitter accumulation 9 no jitter accumulation
- higher order system + 1st order system
9 can be unstable 9 always stable
- slow locking time + fast locking time
- hard to integrate LF + easy to integrate LF
- hard to design + easier to design
+ less ref. signal dependent - ref. signal dependent
+ freq. multiplication - no freq. multiplication
+ no limited locking range - limited locking range

3 AISL
 Jitter Accumulation Comparison
z PLL-based clock generator z DLL-based clock generator

Closed loop Open loop

- jitter accumulation - No jitter accumulation

4 AISL
 Basic DLL Architectures
z Delay-locked Loop (Delay line based first order PLL)

z Phase-Locked Loop (VCO based second order)

5 AISL
DLL Locking Process

6 AISL
 Frequency Response

z Open loop response

7 AISL
 Frequency Response(cnt’d)
z Closed loop response

where loop bandwidth is

8 AISL
 Delay Cell
z Single-ended delay cell
- Simple
- Dynamic power only (no static current)
z Differential delay cell
- Complex biasing
- Static power consumption
- Immune to supply noise and thus smaller jitter
z Variables for delay control
- Current
- Capacitance
- Resistance
- Voltage swing
z Fine delay generation
- Phase interpolation
- Vernier delay line

9 AISL
 Single-Ended Delay Cell
z Current-starved inverter delay line

10 AISL
 Single-Ended Delay Cell(cnt’d)
z Capacitor-loaded inverter delay line

11 AISL
 Single-Ended Delay Cell(cnt’d)
z Inverters with regulated supply voltage

[S. Sidiropoulos, SOVC00]

12 AISL
 Differential Delay Cell
z Differential delay element with resistive loads

- High power supply rejection ratio

- Requirements
9 Adjustable loads to control the delay and resistive loads to
reject power supply noise

13 AISL
 Differential Delay Cell(cnt’d)
z Voltage-controlled two-element PFET “Resistor”

- Adjustable load : Iload=Bp(Vc-Vtp)2

- Resistive load : S-shaped, nearly resistive

14 AISL
 Differential Delay Cell(cnt’d)
z Replica-biased differential delay line circuitry

- The low end of the signal swing can be set by controlling the bias
current with a replica bias circuit

15 AISL
 Differential Delay Cell(cnt’d)
z Replica-biased delay line

(a) Delay adjustment range for replica- (b) Static supply sensitivity for replica-
biased delay element biased delay element

16 AISL
 Phase Interpolation

z Can interpolate between two edges through a weighted sum

- Control over delay is guaranteed to be monotonic,
but not necessarily linear
9 Resolution can be arbitrarily high
9 Precision is limited by linearity

17 AISL
 Delay Line Vernier

z Can use two delay lines with switches to use part of one and
remainder of the other with fractionally larger delays (1 + 1/N)
- Delay resolution is a buffer delay / N
- Relative precision is limited by control over tx / ty

18 AISL
 Phase Detector

z Output describes phase

difference between two
inputs
- may be analog or digital
- may linearly cover a wide
range, or just a narrow phase
difference
- “Dead zone” may occur

19 AISL
Phase-Frequency Detector

20 AISL
 Dead-Zone in PFD
z “Dead-zone” occurs when the loop doesn’t respond
to small phase errors - e.g. 10 ps phase error at PFD
inputs:
- Solution: delay reset to guarantee min. pulse width (typically > 100 ps)

Remove dead zone

dead zone

21 AISL
 Charge Pump
z Converts PFD digital UP/DN signals into
charge
z Charge is proportional to duration of UP/DN
signals
z Qcp = IUP*tUP – IDN*tDN
z The LPF converts integrates currents
z Charge pump requirements:
- Match currents IUP and IDN
- Reduce control voltage coupling
- Supply noise rejection, PVT insensitivity
(Simple or bandgap biased)

22 AISL
 Charge Pump: Better Switches
z Unity-gain buffer controls the voltage over switches
z Current mirrored into Iup/Idn

23 AISL
 Charge Pump: Zero-Offset

z Up and down nodes track with each other thanks to the self-
bias scheme.

24 AISL
Charge Pump : Reversed Switches

25 AISL
2nd Order Charge-Pump Scheme :
Mismatch Cancellation
[K. Kim, ISSCC 04]

26 AISL
 Design Issues
z Bandwidth
z Limited lock range
z Lock in time
z Static phase offset
z Power dissipation limits
z Area limits
z Peak output jitter

27 AISL
 Bandwidth
z Bandwidth
- A wider loop bandwidth
9 Fast acquisition time but degraded jitter performance
-
[A. Chandrakasan, IEEE Press, 2001]
- ICH, KDL, and C are process technology dependent.
- According to the design target, the loop bandwidth varies.

28 AISL
 Adaptive Bandwidth
z Self-biased DLL [J. Maneatis,JSSC 96]

FREF U VBP
Phase Charge C1 Bias
D VCTRL VBN VCDL DO(S)
Comp Pump Gen

DI(S)
Fo
Current and gain of VCDL ωN 1 1
= I C H K D L F R E F
k CB ω REF ω REF C1
I D = • (VCTRL − VT ) 2 K DL =
2 4I D =
1
I C H K D L F R E F
1
2π C1
Current of Charge pump
1 C 1
= x ( 2 I D ) B
I CH = x • (2 • I D ) 2π 4 I D C 1
1 CB
=
4π C 1
29 AISL
 Locking Range
z Locking range

0.5 × TCLK < TVCDL min < TCLK

TCLK < TVCDL max < 1.5 × TCLK

Max(TVCDL min , 2 / 3 × TVCDL max ) < TCLK < Min(2 × TVCDL min , TVCDL max )

30 AISL
 Harmonic Lock Problem
z Correct and false locking

Correct locking

False locking

31 AISL
 DLL Locking Using Inversion
External clock

Initial internal
clock

Inversion of
External clock

Initial internal
clock

Internal clock
after locking

32 AISL
 Wide Range DLL
z Overcome the false locking problem
- Rotating phase DLL
- Phase detector which can detect harmonic locking
- Initial locking starts within delay range

z Widen operating frequency

- Using multiple phases

33 AISL
 Rotating Phase DLL

z Uses N-stage VCDL or VCO phase-locked to clock period

as timing reference to supply output phases that are uniformly
distributed over clock period
z Selects or interpolates output phases from delay reference
z Unlimited output phase range (modulo clock period)
34 AISL
 Rotating Phase DLL (cnt’d)
Semi-digital DLL [S. Sidiropoulos, JSSC97]

35 AISL
 Self-Correction DLL
[D.J.Foley, JSSC01]

Correct locking False locking

z Phase detector gains the control of loop according to release,

under and over

36 AISL
 DLL Using A Replica Delay Line
[Y.Moon, JSSC00]

z The control voltage of RDL protect false locking

37 AISL
DLL Using Multiple Phases
[B.Kim, CICC04]

38 AISL
 Lock Time
z Lock time limits (< 100 cycles for DDR)
- Need high tracking bandwidth ( self-biased DLLs)
- Digital DLLs can use “non-linear” techniques
- Open loop

39 AISL
 Digital Delay Line DLL

z Uses digital delay line with fixed delay as timing reference

z Selects output phases from delay reference (digital control)
z Correction step size is typically fixed
- Large locking time (clock cycle · number of steps)
- Can use exponentially decreasing steps (SADLL)
z Digital delay control provides more flexibility
40 AISL
 Digital Delay Line DLL with SAR
z Successive Approximation Register DLL [M.Hasegawa, ISSCC98]

z Fast-lock by successive
approximation < 64 cycles
z Counter-mode operation during
normal cycle

41 AISL
Digital Delay Line DLL with SAR(cnt’d)

42 AISL
All-Digital DLL Using a TDC
[C.Chung, JSSC04]

Overall architecture

Architecture of the
time-to-digital
converter (TDC)

43 AISL
Schematic of Dual Coarse Delay Line
[J. Kwak, SOVC03]

44 AISL
Compensation of Static Phase Offset
[B.Kim, CICC04]

45 AISL
 Power Dissipation and Area
z Power dissipation limits
- Operating power
9 Analog DLLs can use less power than digital DLLs
- Stand-by power
9 Analog DLLS cannot be turned off for long without relocking
(charge in loop filter cap. Will leak away)
9 Digital DLLs store locked state in registers
z Area limits
- Analog DLLs can have smaller area than digital DLLs
9 Digital delay line DLLs that support low operating frequencies
can be very large

46 AISL
 Register Controlled DLL
[A.Hatakeyama, ISSCC97]

z Locking information is stored as a digital code.

z High resolution because of vernier type delay line.

47 AISL
 Portable DLL
[B.W.Garlepp, JSSC99]

z Phase information is stored in control logic.

48 AISL
 Multiplying DLL
z Avoid jitter accumulation problem of PLL without VCO
z 1st-order system
- Stable and easier to design
z Block diagram

49 AISL
 Multiplying DLL With LC tank

[G. Chien, JSSC 2000]

50 AISL
Multiplying DLL With LC tank (cnt’d)

z Diff. pair modulates tail currents into LC-tank circuit

z LC-Tank enhances load impedance : large area & fixed
multiplication ratio
z Large current necessary for large voltage swing

51 AISL
 Multiplying DLL With AND/OR Gate
[D.J.Foley, JSSC 2001]

z AND/OR gate: 9 times freq. multiplication

z Need analog OR I/O buffer & 50 Ω pull-up resistor: off-chip
clock signal

52 AISL
 Multiplying DLL With Digital Controls
[C.Kim, JSSC 2002]

z Low power and small area

z Easier to integrate
z Multiplication factor can be easily
programmable

53 AISL
Multiplying DLL for Low-jitter Clock
Generation
[R. Farjad-Rad, JSSC 2002]

54 AISL
 Conclusions
z As data rates increase, DLLs will become essential to relax
system timing constraints in each direction of data transfer.
z DLL consists of phase detector, voltage controlled delay cell,
loop filter and charge pump.
z DLL should be designed as considering below issues.
- Bandwidth
- Limited lock range
- Lock in time
- Power dissipation limits
- Area limits
- Peak output jitter

55 AISL
 References
[S.Sidiropoulos SOVC 2000] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, “Adaptivebandwidth DLL’s and PLL’s using regulated supply CMOS buffers,” inVLSI Symp.
Dig. Tech. Papers, June 2000, pp. 124–127.
[Young JSSC 1992] I.A. Young; J.K Greason; K.L Wong, “A PLL clock generator with 5 to 10MHz of lock range for microprocessors,” IEEE J. Solid-state Circuits, vol. 27, no. 11,
pp1599-1607
[Ingino JSSC 2001] J.M. Ingino, V.R von Kaenel, “A 4-GHz clock system for a high-performance system-on-a-chip design” IEEE J. Solid-state Circuits, vol. 36, no. 11, pp1693-1698
[K. Kim ISSCC 04] K. Kim et al , “1.4Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-sped DRAM application” ISSCC 2004 Dig. Tech. Papers, pp
212-213, Feb 2004
[A. Chandrakasan, IEEE Press, 2001] A. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuit. New York: IEEE Press, 2001, p. 240.
[J. Maneatis, JSSC Nov 96] J. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-
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[S. Sidiropoulos, JSSC Nov 97] S. Sidiropoulos, and M. Horowitz, “A semidigital dual delay-locked loop,” IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.
[D.J. Foley JSSC] D.J.Foley and M.P.Flynn, “CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator,” IEEE J. Solid-State , vol.
36, pp.417-423, Mar. 2001
[Y.Moon JSSC 2000] Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-
jitter performance,” IEEE J. Solid-State Circuits, vol.35, pp. 377–384, Mar. 2000.
[B.Kim, CICC04] B.Kim and L. Kim, “A 250MHz-2GHz wide range delay-locked loop,” In Proc.IEEE CICC 2003, pp.139-142, Oct 2004.
[M. Hasegawa, ISSCC98] M. Hasegawa, et al., “A 256Mb SDRAM with subthreshold leakage current suppression,” ISSCC 1998 Dig. Tech. Papers, pp. 80-81, Feb. 1998.
[C.Chung, JSSC04] C. Chung and C. Lee “A New DLL-Based Approach for All-Digital Multiphase Clock Generation” IEEE J. Solid-State Circuits,vol. 39, pp 469-475, MAR. 2004
[J. Kwak, SOVC03] J.Kwak et al.“A low cost high performance register-controlled digital DLL for 1 Gbps_spl times_32 DDR SDRAM” Symp. VLSI Circuits Dig. Tech. Papers, pp283-
284, 2003
[A. Hatakeyama ISSCC 1997] A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takita, Y. Ishii, H. Tsuboi, S. Fujioka, S. Yamaguchi, M. Koga, Y. Serizawa, K. Nishimura, K. Kawabata,
Y. Okajima, M. Kawano, H. Kojima, K. Mizutani, T. Anezaki, M. Hasegawa, and M. Taguchi, “A 256 Mb SDRAM using register-controlled digital DLL,” in ISSCC 1997 Dig.
Tech. Papers, Feb.1997, pp. 72–73.
[B.W Garlepp JSSC 99] B.W. Garlepp, K. S. Donnely, J. Kim, P. S. Chau, J. L. Zerbe, C. Haung, C. V. Tran, C. L. Pourtman, D. Stark, Y. Chan, T. H. Lee, and M. A. Horowitz, “A
portable digital DLL for high-Speed CMOS interface circuits,”IEEE J. Solid-State Circuits, vol. 34, pp. 632–644, May 1999.
[V. von Kaenel, ISSCC98] V. von Kaenel, et al., “A 600MHz CMOS PLL microprocessor clock generator with a 1.2GHz VCO,” ISSCC 1998 Dig. Tech. Papers, pp. 396-397, Feb.
1998.
[G. Chien , JSSC 2000] G. Chien and P. R. Gray, “A900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications,” IEEE J. Solid- State Circuits,
vol. 35, pp. 1996–1999, Dec. 2000.
[C. Kim, JSSC 2002] C. Kim, I.-C. Hwang, and S.-M. Kang, "A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator," IEEE J. Solid-State Circuits, vol. 37, no. 11,
pp. 1414-1420, Nov. 2002.
[R. Farjad-Rad, JSSC 2002] R. Farjad-Rad et al., “Alow-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J.Solid-State
Circuits, vol. 37, pp. 1804–1812, Dec. 2002.[J. Kwak, SOVC03] J.Kwak et al.“A low cost high performance register-controlled digital DLL for 1 Gbps_spl times_32 DDR
SDRAM” Symp. VLSI Circuits Dig. Tech. Papers, pp283-284, 2003

56 AISL