Computer Organization Laboratory Section 0

Class Notes
Course Objectives, Plans, and
Lab Tools
Instructor: Ken Q. Yang
Dept. of ECE, URI

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Course Objectives: What to learn? Course Plan: How to Learn?

•  Computer Architecture Concepts
•  Regular lectures (twice a week, 1:15 each)
–  Instruction Set Architecture –  Covers basic concepts and knowledge
–  CPU, Memory, and I/O Organizations –  Explain tools and techniques necessary
•  Weekly laboratory experiments (minimum 3 hours/week)
•  Interfacing and Communication •  Assessments:
–  Serial and parallel ports –  5 Laboratory experiments,
•  UART, DMA, PI/Timer •  Each lab accounts for 5% of your grade
–  1 Design project, 15% of your grade
–  Wired and wireless networking •  Design and documentations, 5% of your grade
•  Project proposal Presentation (5 minutes), 2%
•  Applying µProcessor to Design Systems •  Final project presentation (10 minutes), 4%
•  demonstration (10 minutes), 4%
•  Advanced Topics –  Exams
All are based on one specific commercial embedded •  3 midterm exams, each accounts for 15% of your grade
•  1 final exam, 20% of your grade
processor: ARM Processor
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Option 2 Pope’s
Inauguration

•  Regular lectures (twice a week, 1:15 each) Then…

–  Covers basic concepts and knowledge
–  Explain tools and techniques necessary
•  One or two design teams will be selected to design an
autonomous vehicle to participate in Freescale Cup in April.
“When smartphones
and tablets
–  Design and implement a autonomous car
–  Meet weekly for at least 3 hours to discuss progress and demonstrate its light up the sky,
operations
–  No Lab for the team
–  Select anyone of the Exams
load up the clouds. ”
Now…

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Source : http://www.alternet.org/speakeasy/alyssa-figueroa/recording-memories-why-must-we-capture-our-every-moment
 Era of Internet and Cloud
All Boil Down to One Thing

Computer
A Very Large Fraction: Embedded Computers and Systems
–  End user devices
–  Variety of appliances
–  Network cores
–  Consumer Electronics
–  More and more

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*Source: Intel 2012

Sec. 1. ARM Family Processors The Cortex™ Processor Family

•  ARM Cortex™-M Family

•  Cortex™-M4 Features
•  Kinetis Cortex™-M4 Enhencement

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Range of Cortex-M Outline

•  ARM Cortex™-M Family

•  Cortex™-M4 Features
•  Kinetis Cortex™-M4 Enhencement

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 What is Cortex™-M CORTEX M-4
•  Harvard Architecture
•  3 stage pipeline
•  Single cycle multiply
•  Hardware Divide
•  Thumb-2 Instruction Set
•  Vectored Interrupt
Controller

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Cortex™-M Pipeline ARM® Instruction Set – Some History

•  ARM Instruction Set

–  Original 32-bit Instruction Set
•  Thumb Instruction Set
–  16-bit Instruction Set
•  Thumb-2 Instruction Set
–  Mixed 16/32 bit Instruction Set

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Effects of the Thumb-2 ISA Register Sets 1

The processor has the following 32-bit registers:
•  13 general-purpose registers, R0-R12
•  Stack Pointer (SP), R13 alias of banked registers, P_process and SP_main
•  Link Register (LR), R14
•  Program Counter (PC), R15
•  Special-purpose Program Status Registers, (xPSR).

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 Register Sets 2 Programmers Model 1
Low registers
Registers R0-R7 are accessible by all instructions that specify a general-purpose register.
High registers
Registers R8-R12 are accessible by all 32-bit instructions that specify a general-purpose register.
Registers R8-R12 are not accessible by any 16-bit instructions.
Registers R13, R14, and R15 have the following special functions:
Stack pointer
Register R13 is used as the Stack Pointer (SP). Because the SP ignores writes to bits [1:0], it is auto aligned
to a word, four-byte boundary.
Handler mode always uses SP_main, but you can configure Thread mode to use either SP_main or
SP_process.
Link register
Register R14 is the subroutine Link Register (LR).
The LR receives the return address from PC when a Branch and Link (BL) or Branch and Link with
•  APSR – Application process status register
Exchange (BLX) instruction is executed.
The LR is also used for exception return.
•  IPSR – Interrupt process status register
At all other times, you can treat R14 as a general-purpose register.
Program counter
•  EPSR – Execution process status register
Register R15 is the Program Counter (PC).
Bit [0] is always 0, so instructions are always aligned to word or half word boundaries.

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Programmers Model 2 Programmers Model 3

Control Register

PRIMASK – Disable all interrupt except NMI and hard fault

FAULTMASK – Disable all interrupt except NMI
BASEPRI – Disable all interrupt of specific priority and lower

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