SEMICONDUCTOR IRF13N50 Series RoHS

RoHS
Nell High Power Products

N-Channel Power MOSFET

(14A, 500Volts)

DESCRIPTION
The Nell IRF13N50 are N-channel enhancement mode D
silicon gate power field effect transistors.
They are designed, tested and guaranteed to withstand
level of energy in breakdown avalanche made of operation.
They are designed as an extremely efficient and reliable
device for use in a wide variety of applications such as G
SMPS, UPS, convertors, motor drivers and drivers for high D TO-220AB
S
power bipolar switching transistors requiring high speed (IRF13N50A)
and low gate drive power.
These transistors can be operated directly from D (Drain)
integrated circuits.

FEATURES G
(Gate)
RDS(ON) = 0.45Ω @ VGS = 10V
Ultra low gate charge(81nC max.) S (Source)

Low reverse transfer capacitance

(C RSS = 11pF typical)
Fast switching capability
100% avalanche energy specified PRODUCT SUMMARY
Improved dv/dt capability ID (A) 14
150°C operation temperature VDSS (V) 500
RDS(ON) (Ω) 0.45 @ V GS = 10V
QG(nC) max. 81

ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise specified)

SYMBOL PARAMETER TEST CONDITIONS VALUE UNIT
VDSS Drain to Source voltage(Note 1) T J =25°C to 150°C 500
V DGR Drain to Gate voltage R GS =20KΩ 500 V
V GS Gate to Source voltage ±30
V GS =10V, T C =25°C 14
ID Continuous Drain Current
V GS =10V, T C =100°C 9.1
A
I DM Pulsed Drain current (Note 1) 56
I AR Repetitive avalanche current (Note 1) 14
E AR Repetitive avalanche energy(Note 1) I AR =14A, R GS =50Ω, V GS =10V 25 mJ
E AS Single pulse avalanche energy (Note 2) I AS =14A, L=5.7mH 560 mJ
dv/dt Peak diode recovery dv/dt(Note 3) 9.2 V /ns
Total power dissipation T C =25°C 250 W
PD
Derating factor above 25 ° C 1.9 W /°C
TJ Operation junction temperature -55 to 150
T STG Storage temperature -55 to 150 ºC

TL Maximum soldering temperature, for 10 seconds 1.6mm from case 300

Mounting torque, #6-32 or M3 screw 10 (1.1) lbf . in (N . m)

Note: 1. Repetitive rating: pulse width limited by junction temperature.

2 . V DD =50V, L=5.7mH, I AS =14A, R G =25Ω, dV/dt=7.6 V/ns, starting T J =25˚C
3 . I SD ≤ 14A, di/dt ≤ 250A/µs, V DD ≤ V (BR)DSS , T J ≤ 150°C.

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 SEMICONDUCTOR IRF13N50 Series RoHS
RoHS
Nell High Power Products

THERMAL RESISTANCE
SYMBOL PARAMETER Min. Typ. Max. UNIT
Rth(j-c) Thermal resistance, junction to case 0.50
Rth(c-s) Thermal resistance, case to heatsink 0.5 ºC/W
Rth(j-a) Thermal resistance, junction to ambient 62

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)

SYMBOL PARAMETER TEST CONDITIONS Min. Typ. Max. UNIT
STATIC
V(BR)DSS Drain to source breakdown voltage V GS = 0V, I D = 250µA 500 V
▲V (BR)DSS/▲T J Breakdown voltage temperature coefficient I D = 1mA, referenced to 25°C 0.55 V/ºC
V DS =500V, V GS =0V T C = 25°C 25
I DSS Drain to source leakage current μA
V DS =400V, V GS =0V T C =125°C 250
Gate to source forward leakage current V GS = 30V, V DS = 0V 100
I GSS nA
Gate to source reverse leakage current V GS = -30V, V DS = 0V -100
R DS(ON) Static drain to source on-state resistance V GS = 10V, l D = 8.4A (Note 1) 0.45 Ω
V GS(TH) Gate threshold voltage V GS =V DS , I D =250μA 2 4 V
g fS Forward transconductance V DS =50V, I D =8.4A 8.1 S
DYNAMIC
C ISS Input capacitance 1910
C OSS Output capacitance V DS = 25V, V GS = 0V, f =1MHz 290
C RSS Reverse transfer capacitance 11
pF
V DS = 1.0V, f =1.0MHz 2730
C OSS Output capacitance
V GS = 0V V DS = 400V, f =1.0MHz 82
C OSS eff. Effective output capacitance (Note 2) V DS = 0 to 400V 160
t d(ON) Turn-on delay time 15
tr Rise time V DD = 250V, I D = 14A, R G = 7.5Ω, 39
ns
t d(OFF) Turn-off delay time V GS = 10V, (Note 1) 39
tf Fall time 31
QG Total gate charge 81
Q GS Gate to source charge V DS = 400V, V GS = 10V, I D = 14A 20 nC
Q GD Gate to drain charge (Miller charge) 36

SOURCE TO DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25°C unless otherwise specified)
SYMBOL PARAMETER TEST CONDITIONS Min. Typ. Max. UNIT
VSD Diode forward voltage I SD = 14A, V GS = 0V 1.5 V
I s (I SD ) Continuous source to drain current Integral reverse P-N junction 14
diode in the MOSFET
D (Drain)

A
I SM Pulsed source current 56
G
(Gate)

S (Source)

t rr Reverse recovery time 370 550 ns

I SD = 14A, V GS = 0V,
Q rr Reverse recovery charge 4.4 6.5 μC
dI F /dt = 100A/µs
I RRM Reverse recovery current 21 31 A
t ON Forward turn-on time Intrinsic turn-on time is negligible (turn-on is domonated by LS+LD)

Note: 1. Pulse test: Pulse width ≤ 300μs, duty cycle ≤ 2% .

2. C oss eff. is a fixed capacitance that gives the same charging time as Coss while V DS is rising from 0 to 80% V DS

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 SEMICONDUCTOR IRF13N50 Series RoHS
RoHS
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ORDERING INFORMATION SCHEME

IRF 13N50 A

MOSFET series
N-Channel, IR series

Current & Voltage rating, lD & VDS

14A / 500V

Package type
A = TO-220AB

Fig.1 Typical output characteristics, Fig.2 Typical transfer characteristics

T C =25°C

100 100
V GS
Top: 15V T J = 25°C
Drain-to-Source current, l D (A)

Drain-to-Source current, l D (A)

10V
8V
7V
6V
T J =150°C
10 5.5V
5V
Bottorm: 4.5V 10

1
4.5V

1
0.1

20µs pulse width V DS =50V

T C =25°C 20µs pulse width
0.01 0.1
0.1 1 10 100 4 6 8 10 12 14 16

Drain-to-Source voltage , V DS (V) Gate-to-Source voltage , V GS (V)

Fig.3 Typical output characteristics, Fig.4 Normalized On-Resistance vs. Temperature

T C =150°C
100 3.0
Drain-to-Source on resistance, R DS(on)

V GS
Top: 15V l D =14A
Drain-to-Source current, l D (A)

10V
8V 2.5
7V
6V
5.5V
5V
10 Bottorm: 4.5V 2.0
(Normalized)

4.5V 1.5

1 1.0

0.5
20µs pulse width
V GS =10V
T J =150°C
0.1 0.0
0.1 1 10 100 -60 -40 -20 0 20 40 60 80 100 120 140 160

Drain-to-Source voltage , V DS (volts) Junction Temperature,T J (°C)

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Fig.5 Typical capacitance vs. Drain-to-Source Fig.6 Typical source-drain diode forward
voltage voltage

100000 100
V GS = 0V, f =1MHZ
C iss = C gs +C gd ( C ds = shorted )
C rss = C gd

Reverse drain current,I SD (A)

10000 C oss = C ds +C gd
Capacitance, (pF)

T J = 150°C
Ciss 10
1000
T J = 25°C

Coss
100
1

10 Crss

V GS = 0V
0 0.1
1 10 100 1000 0.2 0.5 0.8 1.1 1.4

Drain-to-Source voltage , V DS (V) Source-to-drain voltage, V SD (V)

Fig.7 Typical gate charge vs. gate-to-source

voltage Fig.8 Maximum safe operating area

12 10³
Gate-to-source voltage , V GS (volts)

l D = 14A Operation in This Area is Limited by R DS(ON)

V DS = 400V
Drain-to-Current , l D (A)

10 V DS = 250V
V DS = 100V 10²

10 100µs

5
1mssx

1 Note:
2 10msec
1. T C = 25°C
2. T J = 150°C
3. Single Pulse
0 0.1
0 12 24 36 48 60 10 100 1000

Total gate charge , Q G (nC) Drain-to-Source voltage, V DS (V)

Fig.9 Maximum drain current vs.

Case temperature
15

12
Drain Current , l D (A)

0
25 50 75 100 125 150

Case temperature, T C ( ° C)

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Fig.10 Maximum effective transient thermal impedance,

Junction-to-Case

1
Thermal response (RthJc)

D = 0.50

0.1 0.20
0.10
0.05
0.02 Single pulse
0.01
(Thermal response) PDM
0.01
t1

Notes: t2

1. Duty factor, D = t1/ t2

2. Peak TJ = PDM * Rth(j-c) +TC
0.001
0.00001 0.0001 0.001 0.01 0.1 1

Rectangular Pulse Duration , t 1 (seconds)

Fig.11a. Switching time test circuit Fig.11b. Switching time waveforms

RD
V DS
V DS
V GS 90%

RG D.U.T. +
- V DD

10V 10%
Pulse width ≤ 1µs V GS
Duty Factor ≤ 0.1%
t d(ON) t d(OFF)

tR
tF

Fig.12a. Unclamped lnductive test circuit Fig.12b. Unclamped lnductive waveforms

15 V

BV DSS

L l AS
V DS

l D(t)
RG D.U.T. + V DS(t)
V
- DD V DD
l AS A
20V

tP 0.01Ω

Time
tp

Vary t p to obtain required I AS

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Fig.12c. Maximum avalanche energy vs.

Drain current

1150
lD

Single pulse avalanche energy,

TOP 6.3A
8.9A
920 BOTTOM 14A

E AS (mJ)
690

460

230

0
25 50 75 100 125 150

Starting Junction temperature, T J (°C)

Fig.13a. Basic gate charge waveform Fig.13b. Gate charge test circuit

Current Regulator
Same Type as D.U.T.
V GS

50KΩ
QG
12V 0.2µF
10V
0.3µF

Q GD
+
Q GS V DS
D.U.T. -

V GS

3mA

RG RD
Charge
Current Sampling Resistors

Fig.14 Peak diode recovery dv/dt test circuit for N-Channel MOSFET

Driver Gate Drive

D.U.T. Period D=
P.W.
+ Circuit Layout Considerations P.W. Period
• Low Stray lnductance
• Ground Plane VGS=10V *
• Low Leakage lnductance
Current Transformer
-
D.U.T. I SD Waveform
+
Reverse
Recovery Body Diode Forward
Current Current
- + di/dt
-
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

Re-Applied
• dv/dt controlled by R G Voltage
RG + Body Diode Forward Drop
• Driver same type as D.U.T.
• l SD controlled by Duty Factor " D " V DD Inductor Curent
-
• D.U.T. -Device Under Test
Ripple ≤ 5% ISD

*V GS = 5V for Logic Level Devices and 3V for drive devices

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 SEMICONDUCTOR IRF13N50 Series RoHS
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Nell High Power Products

Case Style

TO-220AB
10.54 (0.415) MAX.

9.40 (0.370) 3.91 (0.154) 4.70 (0.185)

9.14 (0.360) 3.74 (0.148) 4.44 (0.1754)
1.39 (0.055)
2.87 (0.113)
1.14 (0.045)
2.62 (0.103)

3.68 (0.145)
3.43 (0.135)
16.13 (0.635) 15.32 (0.603)
15.87 (0.625) 14.55 (0.573)
PIN 8.89 (0.350)
1 2 3 8.38 (0.330)
4.06 (0.160) 29.16 (1.148)
3.56 (0.140) 28.40 (1.118)
2.79 (0.110)
2.54 (0.100)
1.45 (0.057)
1.14 (0.045) 14.22 (0.560)
13.46 (0.530)
2.67 (0.105)
2.41 (0.095) 0.90 (0.035) D (Drain)
2.65 (0.104) 0.70 (0.028)
5.20 (0.205) 0.56 (0.022)
2.45 (0.096)
4.95 (0.195) 0.36 (0.014)

G
(Gate)

S (Source)
All dimensions in millimeters(inches)

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