Linear Li-Ion Battery Charger With Power Path and USB Compatibility in LFCSP

Linear Li-Ion Battery Charger with Power
Path and USB Compatibility in LFCSP

Data Sheet ADP5062
FEATURES GENERAL DESCRIPTION
4 mm × 4 mm LFCSP package The ADP5062 charger is fully compliant with USB 3.0 and the
Fully programmable via I2C USB Battery Charging Specification 1.2 and enables charging
Flexible digital control inputs via the mini USB VBUS pin from a wall charger, car charger, or
Up to 2.1 A current from an ac charger in LDO mode USB host port.
Operating input voltage from 4.0 V to 6.7 V
The ADP5062 operates from a 4 V to 6.7 V input voltage range
Tolerant input voltage from −0.5 V to +20 V (USB VBUS)
but is tolerant of voltages up to 20 V thereby alleviating concerns
Fully compatible with USB 3.0 and USB Battery Charging
about USB bus spikes during disconnect or connect scenarios.
Specification 1.2
Built-in current sensing and limiting The ADP5062 features an internal FET between the linear
As low as 54 mΩ battery isolation FET between battery and charger output and the battery. This permits battery isolation
charger output and, hence, system powering under a dead battery or no battery
Thermal regulation prevents overheating scenario, which allows for immediate system function on connec-
Compliant with JEITA 1 and JEITA 2 Li-Ion battery charging tion to a USB power supply.
temperature specifications Based on the type of USB source, which is detected by an external
SYS_EN flag permits the system to be disabled until battery is at USB detection chip, the ADP5062 can be set to apply the correct
the minimum required level for guaranteed system start-up current limit for optimal charging and USB compliance.
APPLICATIONS The ADP5062 has three factory-programmable digital input/out-
Digital still cameras put pins that provide maximum flexibility for different systems.
Digital video cameras These digital input/output pins permit combinations of features
Single cell Li-Ion portable equipment such as, input current limits, charging enable and disable, charging
PDAs, audio, and GPS devices current limits, and a dedicated interrupt output pin.
Portable medical devices
Mobile phones
TYPICAL APPLICATION CIRCUIT

ADP5062
AC OR VBUS VIN ISO_Sx SYSTEM
USB CBP C3
C4 C1 22µF
10µF 10nF
SCL
SDA ISO_Bx
PROGRAMMABLE
CHARGER BAT_SNS C2
DIG_IO1 CONTROL 22µF
DIG_IO2
BLOCK + Li-ion
DIG_IO3 THR
SYS_EN
ILED
VLED
10806-001
AGND
Figure 1.
Rev. B Document Feedback

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ADP5062* PRODUCT PAGE QUICK LINKS
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ADP5062 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Battery Isolation FET ................................................................. 21
Applications ....................................................................................... 1 Battery Detection ....................................................................... 21
General Description ......................................................................... 1 Battery Pack Temperature Sensing .......................................... 22
Typical Application Circuit ............................................................. 1 I2C Interface ................................................................................ 26
Revision History ............................................................................... 2 I2C Register Map......................................................................... 27
Specifications..................................................................................... 3 Register Bit Descriptions ........................................................... 28
Recommended Input and Output Capacitances ...................... 6 Applications Information .............................................................. 36
I C-Compatible Interface Timing Specifications ..................... 6
2
External Components ................................................................ 36
Absolute Maximum Ratings ....................................................... 8 PCB Layout Guidelines.............................................................. 38
Thermal Resistance ...................................................................... 8 Power Dissipation and Thermal Considerations ....................... 39
ESD Caution .................................................................................. 8 Charger Power Dissipation ....................................................... 39
Pin Configuration and Function Descriptions ............................. 9 Junction Temperature ................................................................ 39
Typical Performance Characteristics ........................................... 10 Factory-Programmable Options .................................................. 40
Temperature Characteristics ..................................................... 12 Charger Options ......................................................................... 40
Typical Waveforms ..................................................................... 14 I2C Register Defaults .................................................................. 41
Theory of Operation ...................................................................... 15 Digital Input and Output Options ........................................... 41
Summary of Operation Modes ................................................. 15 Packaging and Ordering Information ......................................... 43
Introduction ................................................................................ 16 Outline Dimensions ................................................................... 43
Charger Modes............................................................................ 18 Ordering Guide .......................................................................... 43
Thermal Management ............................................................... 21
REVISION HISTORY
10/13—Rev. A to Rev. B
Changes to Table 19 ........................................................................ 28
Changes to Table 26 ........................................................................ 32
Changes to Charger Options Section and Table 41 ................... 40
Changes to Ordering Guide .......................................................... 43
4/13—Rev. 0 to Rev. A
Changes to Figure 3 .......................................................................... 9
9/12—Revision 0: Initial Version
Rev. B | Page 2 of 44
Data Sheet ADP5062
SPECIFICATIONS
−40°C < TJ < +125°C, VVINx = 5.0 V, RHOT_RISE < RTHR < RCOLD_FALL, VBAT_SNS = 3.6 V, VISO_Bx = VBAT_SNS, CVIN = 10 µF, CISO_S = 22 µF, CISO_B = 22 µF,
CCBP = 10 nF, all registers at default values, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
GENERAL PARAMETERS
Undervoltage Lockout VUVLO 2.25 2.35 2.5 V Falling threshold, higher of VVINx and VBAT_SNS 1
Hysteresis 50 100 150 mV Hysteresis, higher of VVINx and VBAT_SNS rising1
Total Input Current ILIM 74 92 100 mA Nominal USB initialized current level 2
114 150 mA USB super speed
300 mA USB enumerated current level (specification for
China)
425 470 500 mA USB enumerated current level
900 mA Dedicated charger input
1500 mA Dedicated wall charger
VINx Current Consumption IQVIN 2 mA Charging or LDO mode
IQVIN_DIS 280 450 µA DIS_IC1 = high, VISO_Bx < VINx < 5.5 V
Battery Current Consumption IQBATT 20 µA LDO mode, VISO_Sx > VBAT_SNS
5 µA Standby, includes ISO_Sx pin leakage, VVINx = 0 V,
TJ = −40°C to +85°C
0.5 0.9 mA Standby, battery monitor active
CHARGER
Fast Charge Current CC Mode ICHG 700 750 790 mA VISO_Bx = 3.9 V; fast charge current accuracy is
guaranteed at temperatures from TJ = −40°C to the
isothermal regulation limit (typically TJ = +115°C)2, 3
Fast Charge Current Accuracy −8 +7 % ICHG = 400 mA to 1300 mA
−33 +29 mA ICHG = 250 mA to 350 mA
−45 +40 mA ICHG = 50 mA to 200 mA
Trickle Charge Current2 ITRK_DEAD 16 20 25 mA
Weak Charge Current2, 3 ICHG_WEAK ITRK_DEAD + ICHG mA
Trickle to Weak Charge Threshold
Dead Battery VTRK_DEAD 2.4 2.5 2.6 V VTRK_DEAD < VBAT_SNS < VWEAK2, 4
Hysteresis ΔVTRK_DEAD 100 mV On BAT_SNS2
Weak Battery Threshold
Weak to Fast Charge Threshold VWEAK 2.89 3.0 3.11 V On BAT_SNS2, 4
ΔVWEAK 100 mV
Battery Termination Voltage VTRM 4.200 V
Termination Voltage Accuracy −0.25 +0.25 % On BAT_SNS, TJ = 25°C, IEND = 52.5 mA2
−1.04 +0.89 % TJ = 0°C to 115°C2
−1.16 +1.20 % TJ = −40°C to +125°C
Battery Overvoltage Threshold VBATOV VIN − 0.075 V Relative to VINx voltage, BAT_SNS rising
Charge Complete Current IEND 15 52.5 98 mA VBAT_SNS = VTRM
Charging Complete Current Threshold 17 83 mA IEND = 52.5 mA, TJ = 0°C to 115°C2
Accuracy
59 123 mA IEND = 92.5 mA, TJ = 0°C to 115°C
Recharge Voltage Differential VRCH 160 260 390 mV Relative to VTRM, BAT_SNS falling2
Battery Node Short Threshold Voltage2 VBAT_SHR 2.2 2.4 2.5 V
Battery Short Detection Current ITRK_SHORT 20 mA ITRK_SHORT = ITRK_DEAD2
Charging Start Voltage Limit VCHG_VLIM 3.6 3.7 3.8 V Voltage limit is not active by default
Charging Soft Start Current ICHG_START 185 260 365 mA VBAT_SNS > VTRK_DEAD
Charging Soft Start Timer tCHG_START 3 ms
ADP5062 Data Sheet
BATTERY ISOLATION FET
Pin to Pin Resistance Between ISO_Sx RDSON_ISO 54 89 mΩ On battery supplement mode, VINx = 0 V, VISO_Bx =
and ISO_Bx 4.2 V, IISO_Bx = 500 mA
Regulated System Voltage: VBAT Low VISO_SFC 3.6 3.8 4.0 V VTRM[5:0] programming ≥ 4.00 V
3.2 3.4 3.5 V VTRM[5:0] programming < 4.00 V
Battery Supplementary Threshold VTHISO 0 5 12 mV VISO_Sx < VISO_Bx, VSYS rising
LDO AND HIGH VOLTAGE BLOCKING
Regulated System Voltage VISO_STRK 4.214 4.3 4.386 V VSYSTEM[2:0] = 000 (binary) = 4.3 V, IISO_Sx =
100 mA, LDO mode2
Load Regulation −0.56 %/A IISO_Sx = 0 m A to 1500 mA
High Voltage Blocking FET (LDO FET) RDS(ON)HV 330 485 mΩ IVINx = 500 mA
On Resistance
Maximum Output Current 2.1 A VISO_Sx = 4.3 V, LDO mode
VINx Input Voltage, Good Threshold VVIN_OK_RISE 3.75 3.9 4.0 V
Rising
VINx Falling VVIN_OK_FALL 3.6 3.7 V
VINx Input Overvoltage Threshold VVIN_OV 6.7 6.9 7.2 V
Hysteresis ΔVVIN_OV 0.1 V
VINx Transition Timing TVIN_RISE 10 µs Minimum rise time for VINx from 5 V to 20 V
TVIN_FALL 10 µs Minimum fall time for VINx from 4 V to 0 V
THERMAL CONTROL
Isothermal Charging Temperature TLIM 115 °C
Thermal Early Warning Temperature TSDL 130 °C
Thermal Shutdown Temperature TSD 140 °C TJ rising
110 °C TJ falling
THERMISTOR CONTROL
Thermistor Current
10,000 NTC INTC_10k 400 μA
100,000 NTC INTC_100k 40 μA
Thermistor Capacitance CNTC 100 pF
Cold Temperature Threshold TNTC_COLD 0 °C No battery charging occurs
Resistance Thresholds
Cool to Cold Resistance RCOLD_FALL 20,500 25,600 30,720 Ω
Cold to Cool Resistance RCOLD_RISE 24,400 Ω
Hot Temperature Threshold TNTC_HOT 60 °C No battery charging occurs
Hot to Typical Resistance RHOT_FALL 3700 Ω
Typical to Hot Resistance RHOT_RISE 2750 3350 3950 Ω
JEITA1 Li-ION BATTERY CHARGING
SPECIFICATION DEFAULTS 5
JEITA Cold Temperature TJEITA_COLD 0 °C No battery charging occurs
JEITA Cool Temperature TJEITA_COOL 10 °C Battery charging occurs at 50% of programmed
level
Typical to Cool Resistance RTYP_FALL 13,200 16,500 19,800 Ω
Cool to Typical Resistance RTYP_RISE 15,900 Ω
JEITA Warm Temperature TJEITA_WARM 45 °C Battery termination voltage (VTRM) is reduced by
100 mV
Warm to Typical Resistance RWARM_FALL 5800 Ω
Typical to Warm Resistance RWARM_RISE 4260 5200 6140 Ω
Data Sheet ADP5062
JEITA Hot Temperature TJEITA_HOT 60 °C No battery charging occurs
Hot to Warm Resistance RHOT_FALL 3700 Ω
Warm to Hot Resistance RHOT_RISE 2750 3350 3950 Ω
JEITA2 Li-ION BATTERY CHARGING
SPECIFICATION DEFAULTS5
JEITA Cold Temperature TJEITA_COLD 0 °C No battery charging occurs
JEITA Cool Temperature TJEITA_COOL 10 °C Battery termination voltage (VTRM) is reduced by
100 mV
Typical to Cool Resistance RTYP_FALL 13,200 16,500 19,800 Ω
Cool to Typical Resistance RTYP_RISE 15,900 Ω
JEITA Warm Temperature TJEITA_WARM 45 °C Battery termination voltage (VTRM) is reduced by
100 mV
Warm to Typical Resistance RWARM_FALL 5800 Ω
Typical to Warm Resistance RWARM_RISE 4260 5200 6140 Ω
JEITA Hot Temperature TJEITA_HOT 60 °C No battery charging occurs
Hot to Warm Resistance RHOT_FALL 3700 Ω
Warm to Hot Resistance RHOT_RISE 2750 3350 3950 Ω
BATTERY DETECTION
Sink Current ISINK 13 20 34 mA
Source Current ISOURCE 7 10 13 mA
Battery Threshold
Low VBATL 1.8 1.9 2.0 V
High VBATH 3.4 V
Battery Detection Timer tBATOK 333 ms
TIMERS
Clock Oscillator Frequency fCLK 2.7 3 3.3 MHz
Start Charging Delay tSTART 1 sec
Trickle Charge tTRK 60 min
Fast Charge tCHG 600 min
Charge Complete tEND 7.5 min VBAT_SNS = VTRM, ICHG < IEND
Deglitch tDG 31 ms Applies to VTRK_DEAD, VRCH, IEND, VWEAK, VVIN_OK_RISE, and
VVIN_OK_FALL
Watchdog2 tWD 32 sec
Safety tSAFE 36 40 44 min
Battery Short2 tBAT_SHR 30 sec
ILED OUTPUT PINS
Voltage Drop over ILED VILED 200 mV IILED = 20 mA
Maximum Operating Voltage over VMAXILED 5.5 V
ILED
SYS_EN OUTPUT PIN
SYS_EN FET On Resistance RON_SYS_EN 10 Ω ISYS_EN = 20 mA
ADP5062 Data Sheet
LOGIC INPUT PINS
Maximum Voltage on Digital Inputs VDIN_MAX 5.5 V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Maximum Logic Low Input Voltage VIL 0.5 V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Minimum Logic High Input Voltage VIH 1.2 V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Pull-Down Resistance 215 350 610 kΩ Applies to DIG_IO1, DIG_IO2, DIG_IO3
1
Undervoltage lockout generated normally from ISO_Sx or ISO_Bx; in certain transition cases, it can be generated from VINx.
2
These values are programmable via I2C. Values are given with default register values.
3
The output current during charging may be limited by the input current limit or by the isothermal charging mode.
4
During weak charging mode, the charger provides at least 20 mA of charging current via the trickle charge branch to the battery unless trickle charging is disabled.
Any residual current that is not required by the system is also used to charge the battery.
5
Either JEITA1 (default) or JEITA2 can be selected in I2C, or both JEITA functions can be enabled or disabled in I2C.
RECOMMENDED INPUT AND OUTPUT CAPACITANCES

Table 2.
CAPACITANCES
VINx CVINx 4 10 μF Effective capacitance
CBP CCBP 6 10 14 nF Effective capacitance
ISO_Sx CISO_Sx 10 22 100 μF Effective capacitance
ISO_Bx CISO_Bx 10 22 μF Effective capacitance
I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS

Table 3.
Parameter 1 Symbol Min Typ Max Unit
I2C-COMPATIBLE INTERFACE 2
Capacitive Load for Each Bus Line CS 400 pF
SCL Clock Frequency fSCL 400 kHz
SCL High Time tHIGH 0.6 µs
SCL Low Time tLOW 1.3 µs
Data Setup Time tSU, DAT 100 ns
Data Hold Time tHD, DAT 0 0.9 µs
Setup Time for Repeated Start tSU, STA 0.6 µs
Hold Time for Start/Repeated Start tHD, STA 0.6 µs
Bus Free Time Between a Stop and a Start Condition tBUF 1.3 µs
Setup Time for Stop Condition tSU, STO 0.6 µs
Rise Time of SCL/SDA tR 20 300 ns
Fall Time of SCL/SDA tF 20 300 ns
Pulse Width of Suppressed Spike tSP 0 50 ns
1
Guaranteed by design.
2
A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).
Data Sheet ADP5062
Timing Diagram
SDA
tF tSP tR tBUF
tLOW
tR tSU, DAT tF tHD, STA
SCL
tHIGH tSU, STA tSU, STO

S tHD, DAT Sr P S
10806-002
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Figure 2. I2C Timing Diagram
ADP5062 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4. Absolute Maximum Ratings Maximum Power Dissipation
Parameter Rating The maximum safe power dissipation in the ADP5062 package
VIN1, VIN2, VIN3 to AGND –0.5 V to +20 V is limited by the associated rise in junction temperature (TJ) on
All Other Pins to AGND –0.3 V to +6 V the die. At a die temperature of approximately 150°C (the glass
Continuous Drain Current, Battery Supple- 2.1 A transition temperature), the properties of the plastic change.
mentary Mode, from ISO_Bx to ISO_Sx Even temporarily exceeding this temperature limit may change
Storage Temperature Range –65°C to +150°C the stresses that the package exerts on the die, thereby perma-
Operating Junction Temperature Range –40°C to +125°C nently shifting the parametric performance of the ADP5062.
Soldering Conditions JEDEC J-STD-020 Exceeding a junction temperature of 175°C for an extended
period can result in changes in the silicon devices, potentially
Stresses above those listed under Absolute Maximum Ratings causing failure.
may cause permanent damage to the device. This is a stress ESD CAUTION
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is
specified for a device soldered in a circuit board for surface-
mount packages.
Table 5. Thermal Resistance

Package Type θJA θJC Unit
20-Lead LFCSP 35.6 3.65 °C/W
Data Sheet ADP5062
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYS_EN
AGND
SDA
CBP
THR
17
16
20
19
18
PIN 1
SCL 1 INDICATOR 15 ILED
DIG_IO3 2 14 ISO_B3
DIG_IO2 3 ADP5062 13 ISO_B2
BAT_SNS 4 TOP VIEW 12 ISO_B1
(Not to Scale)
DIG_IO1 5 11 ISO_S3
9
8
10
6
7
ISO_S1
ISO_S2
VIN1
VIN2
VIN3
NOTES
10806-003
1. CONNECTION OF THE EXPOSED PAD IS NOT REQUIRED. THE
EXPOSED PAD CAN BE CONNECTED TO ANALOG GROUND TO
IMPROVE HEAT DISSIPATION FROM THE PACKAGE TO BOARD.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions

Pin No. Name Type 1 Description
9, 10, 11 ISO_S1, ISO_S2, I/O Linear Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. High
ISO_S3 current input/output.
6, 7, 8 VIN1, VIN2, VIN3 I/O Power Connections to USB VBUS. These pins are high current inputs when in charging mode.
20 AGND G Analog Ground.
12, 13, 14 ISO_B1, ISO_B2, I/O Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET.
ISO_B3
1 SCL I I2C-Compatible Interface Serial Clock.
17 SDA I/O I2C-Compatible Interface Serial Data.
5 DIG_IO1 GPIO Set Input Current Limit. This pin sets the input current limit directly. When DIG_IO1 = low or
high-Z, the input limit is 100 mA. When DIG_IO1 = high, the input limit is 500 mA. 2, 3
3 DIG_IO2 GPIO Disable IC1. The DIG_IO2 pin sets the charger to the low current mode. When DIG_IO2 = low or
high-Z, the charger operates in normal mode. When DIG_IO2 = high, the LDO and the charger are
disabled and VINx current consumption is 280 µA (typical). In addition, when DIG_IO2 is high,
20 V VINx input protection is disabled and the VINx voltage level must fulfill the condition,
VISO_Bx < VVINx < 5.5 V.2, 3
2 DIG_IO3 GPIO Enable Charging. When DIG_IO3 = low or high-Z, charging is disabled. When DIG_IO3 = high,
charging is enabled.2, 3
18 THR I Battery Pack Thermistor Connection. If this pin is not used, connect a dummy 10 kΩ resistor from
THR to GND.
4 BAT_SNS I Battery Voltage Sense Pin.
15 ILED O Open-Drain Output to Indicator LED.
16 SYS_EN O System Enable. This pin is the battery OK flag/open-drain pull-down FET to enable the system
when the battery reaches the VWEAK level.
19 CBP I/O Bypass Capacitor Input.
N/A 4 EP N/A4 Exposed Pad. Connection of the exposed pad is not required. The exposed pad can be connected
to analog ground to improve heat dissipation from the package to the board.
1
I is input, O is output, I/O is input/output, G is ground, and GPIO is the factory programmable general-purpose input/output.
2
See the Digital Input and Output Options section for details.
3
The DIG_IOx setting defines the initial state of the ADP5062. If the parameter or the mode that is related to each DIG_IOx pin setting is changed (by programming an
equivalent I2C register bit or bits), the I2C register setting takes precedence over the DIG_IOx pin setting. VINx connection or disconnection resets control to the
DIG_IOx pin.
4
N/A means not applicable.
ADP5062 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS

VVINx = 5.0 V, CVINx = 10 µF, CISO_Sx = 44 µF, CISO_Bx = 22 µF, CCBP = 10 nF, all registers at default values, unless otherwise noted.
4.40 5.10
4.38 5.08
4.36 5.06
SYSTEM VOLTAGE (V)
SYSTEM VOLTAGE (V)

4.34 5.04
4.32 5.02
4.30 5.00
4.28 4.98
4.26 4.96
4.24 4.94
4.22 4.92
4.20 4.90
10806-004
10806-007
0.01 0.1 1 0.01 0.1 1
SYSTEM OUTPUT CURRENT (A) SYSTEM OUTPUT CURRENT (A)
Figure 4. System Voltage vs. System Output Current, LDO Mode, Figure 7. System Voltage vs. System Output Current, LDO Mode, VVINx = 6.0 V,
VSYSTEM[2:0] = 000 (Binary) = 4.3 V VSYSTEM[2:0] = 111 (Binary) = 5.0 V
4.5 5.4
LOAD = 100mA LOAD = 100mA
LOAD = 500mA LOAD = 500mA
4.4 LOAD = 1000mA 5.2
LOAD = 1000mA
4.3 5.0
SYSTEM VOLTAGE (V)
SYSTEM VOLTAGE (V)
4.2 4.8
4.1 4.6
4.0 4.4
3.9 4.2
3.8 4.0
3.7 3.8
3.6 3.6
3.5 3.4
10806-008
10806-005
4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
Figure 5. System Voltage vs. Input Voltage (in Dropout), LDO Mode, Figure 8. System Voltage vs. Input Voltage (in Dropout), LDO Mode,
VSYSTEM[2:0] = 000 (Binary) = 4.3 V VSYSTEM[2:0] = 111 (Binary) = 5.0 V
1000 700
900
600 WEAK
CHARGE
800
CHARGE CURRENT (mA)
CHARGE CURRENT (mA)
700 LIMIT = 900mA 500

LIMIT = 500mA
LIMIT = 100mA FAST CHARGE
600
400
500
300
400
300 200
200 TRICKLE CHARGE
100
100
0 0
10806-006
10806-009
2.7 3.2 3.7 4.2 2.3 2.8 3.3 3.8 4.3

BATTERY VOLTAGE (V) BATTERY VOLTAGE (V)
Figure 6. Input Current-Limited Charge Current vs. Battery Voltage Figure 9. Battery Charge Current vs. Battery Voltage, ICHG[4:0] = 01001
(Binary) = 500 mA, ILIM[3:0] = 1111 (Binary) = 2100 mA
Data Sheet ADP5062
70 70
ISOLATION FET RESISTANCE (mΩ)

ISOLATION FET RESISTANCE (mΩ)
65 65
60 60
55 55
50 50
45 45
40 40
10806-012
10806-010
2.7 3.2 3.7 4.2 0 0.5 1.0 1.5 2.0
BATTERY VOLTAGE (V) LOAD CURRENT (A)
Figure 10. Ideal Diode RON vs. Battery Voltage, IISO_Sx = 500 mA, VINx Open Figure 12. Ideal Diode RON vs. Load Current, VISO_Bx = 3.6 V
4.0 4.4 0.7

DEFAULT STARTUP VBAT_SNS
DIS_LDO = HIGH IISO_Bx
3.5 DIS_IC1 = HIGH 4.2 0.6
3.0
BATTERY VOLTAGE (A)

4.0 0.5
CHARGE CURRENT (A)

VINx CURRENT (mA)
2.5
3.8 0.4
2.0
3.6 0.3
1.5
3.4 0.2
1.0
0.5 3.2 0.1
0 3.0 0
10806-013
10806-011
0 2 4 6 8 0 50 100 150
VINx VOLTAGE (V) CHARGE TIME (min)
Figure 11. VINx Current vs. VINx Voltage, No Battery Figure 13. Charge Profile, ILIM[3:0] = 0110 (Binary) = 500 mA, Battery
Capacity = 925 mAh
ADP5062 Data Sheet
TEMPERATURE CHARACTERISTICS
1.5 0.5
VISO_Bx = 3.6V VISO_Sx = 4.3V
1.4 VISO_Bx = 4.2V VISO_Sx = 5.0V
VISO_Bx = 5.5V 0.4
1.3
SYSTEM VOLTAGE ACCURACY (%)

1.2 0.3
STANDBY CURRENT (µA)
1.1
0.2
1.0
0.9 0.1
0.8
0
0.7
0.6 –0.1
0.5
–0.2
0.4
0.3 –0.3
0.2
–0.4
0.1
0 –0.5
10806-017
10806-014
–40 –15 10 35 60 85 –40 –25 –10 5 20 35 50 65 80 95 110 125
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
Figure 14. Battery Leakage Current vs. Ambient Temperature Figure 17. System Voltage vs. Temperature, Trickle Charge Mode,
VISO_Sx = 4.3 V and VINx = 5.0 V, or VISO_Sx = 5.0 V and VINx = 6.0 V
0.50 5.0
VIN = 4.0V VIN = 4.0V
VIN = 5.0V VIN = 5.0V
0.45 VIN = 5.5V 4.5
VIN = 6.7V
VINx QUIESCENT CURRENT (mA)
VINx QUIESCENT CURRENT (mA)
0.40 4.0
0.35 3.5
0.30 3.0
0.25 2.5
0.20 2.0
0.15 1.5
0.10 1.0
0.05 0.5
0 0
10806-018
10806-015
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
Figure 15. VINx Quiescent Current vs. Ambient Temperature, DIS_IC1 = High Figure 18. VINx Quiescent Current vs. Ambient Temperature, LDO Mode
0.5 0.5
VISO_Sx = 4.3V VTRM = 3.8V
VISO_Sx = 5.0V 0.4 VTRM = 4.2V
0.4 VTRM = 4.5V
SYSTEM VOLTAGE ACCURACY (%)
VTRM VOLTAGE ACCURACY (%)
0.3 0.3
0.2 0.2
0.1 0.1
0 0
–0.1 –0.1
–0.2 –0.2
–0.3 –0.3
–0.4 –0.4
–0.5 –0.5
10806-019
10806-016
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
Figure 16. LDO Mode Voltage vs. Ambient Temperature, Figure 19. Termination Voltage vs. Ambient Temperature
Load = 100 mA, VVINx = 5.5 V
Data Sheet ADP5062
1.4 1.6
ICHG = 1300mA 1.5
1.3 ILIM = 1500mA
1.4
1.2 1.3
INPUT CURRENT LIMIT (A)

1.2
CHARGE CURRENT (A)
1.1 1.1
1.0
1.0
0.9 ILIM = 900mA
0.9 0.8
0.7
0.8
0.6
ICHG = 750mA
0.7 0.5 ILIM = 500mA
0.4
0.6 0.3
ICHG = 500mA 0.2
0.5 ILIM = 100mA
0.1
0.4 0
10806-022
10806-020
–40 –15 10 35 60 85 110 –40 –25 –10 5 20 35 50 65 80 95 110 125
Figure 20. Fast Charge CC Mode Current vs. Ambient Temperature Figure 22. Input Current Limit vs. Ambient Temperature
7.00
VIN OVERVOLTAGE THRESHOLD (V)
6.95
6.90
6.85
6.80
10806-021
–40 –25 –10 5 20 35 50 65 80 95 110 125

AMBIENT TEMPERATURE (°C)
Figure 21. VINx Overvoltage Threshold vs. Ambient Temperature
ADP5062 Data Sheet
TYPICAL WAVEFORMS
T T
VISO_Sx
VISO_Sx
VVINx
VVINx
4 4 IISO_Bx
1 1
IISO_Bx
2
IVINx
2
IVINx
3 3
10806-026
10806-023
CH1 2.00V CH2 200mA M1.00ms A CH2 120mA CH1 2.00V CH2 200mA M200.0µs A CH2 216mA
CH3 200mA CH4 2.00V T 1.00ms CH3 200mA CH4 2.00V T 0.00s
Figure 23. Charging Startup, VVINx = 5.0 V, ILIM[3:0] = 0110 (Binary) = 500 mA, Figure 26. USB VBUS Disconnect
ICHG[4:0] = 01110 (Binary) = 750 mA
T VISO_Sx T
VISO_Sx
1
3
IISO_Bx
1
IISO_Sx IISO_Sx
10806-027
10806-024
CH1 100mV CH2 500mA M1.00ms A CH2 820mA CH1 1.00V CH2 500mA M1.0ms A CH2 –610mA
T 3.00ms CH3 500mA T 3.00ms
Figure 24. Load Transient, IISO_Sx Load = 300 mA to 1500 mA to 300 mA Figure 27. Load Transient, IISO_Sx Load = 300 mA to 1500 mA to 300 mA,
EN_CHG = High, ILIM[3:0] = 0110 (Binary) = 500 mA
T T
VISO_Sx
2
VVINx
1
VISO_Bx
IISO_Bx
IISO_Bx
3
3
IVINx
4
10806-028
10806-025
CH1 200mV CH2 200mV M40.0µs A CH3 610mA CH2 2.00V M200ms A CH3 17.2mA
CH3 500mA CH4 500mA T 0.00s CH3 10.0mA T 0.00s
Figure 25. Input Current-Limit Transition from 100 mA to 900 mA, Figure 28. Battery Detection Waveform, VSYSTEM[2:0] = 000 (Binary) = 4.3 V,
ISO_Sx Load = 66 Ω, Charging = 750 mA No Battery
Data Sheet ADP5062
THEORY OF OPERATION
SUMMARY OF OPERATION MODES
Table 7. Summary of the ADP5062 Operation Modes
VINx Trickle LDO FET Battery System Voltage
Mode Name Condition Battery Condition Charge State Isolation FET ISO_Sx Additional Conditions 1
IC Off, Standby 0V Any battery condition Off Off On/Off Battery voltage Disable IC1
or 0 V
IC Off, Suspend 5V Any battery condition Off Off On Battery voltage Disable IC1
LDO Mode Off, Isolation 5V Any battery condition Off Off On Battery voltage Disable LDO and enable
FET On isolation FET
LDO Mode Off, Isolation 5V Any battery condition Off Off Off 0V Enable battery charging
FET Off (System Off)
LDO Mode, Charger Off 5V Any battery condition Off LDO Off 5.0 V Enable battery charging
Trickle Charge Mode 5V Battery < VTRK_DEAD On LDO Off 5.0 V Enable battery charging
Weak Charge Mode 5V VTRK_DEAD ≤ battery < VWEAK On CHG CHG 3.8 V Enable battery charging
Fast Charge Mode 5V Battery ≥ VWEAK Off CHG CHG 3.8 V (minimum) Enable battery charging
Charge Mode, No Battery 5V Open Off LDO Off 5.0 V Enable battery charging
Charge Mode, Battery 5V Shorted On LDO Off 5.0 V Enable battery charging
(ISO_Bx) Shorted
1
See Table 8 for details.
Table 8. Operation Mode Controls

Equivalent I2C
Pin Configuration DIG_IOx Address, Data Bit(s) Description
Enable Battery Charging DIG_IO3 0x07, D0 Low = all charging modes disabled (fast, weak, trickle).
High = all charging modes enabled (fast, weak, trickle).
Disable IC1 DIG_IO2 0x07, D6 VINx 1 Supply
Disable IC1 Connected LDO_FET ISO_FET
Low No Off On
Yes CHG CHG
High No 2 Off On
Yes Off On
Disable LDO and Enable Isolation FET 0x07, D3, D0 Low = LDO enabled.
High = LDO disabled. In addition, when EN_CHG = low, the
battery isolation FET is on; when EN_CHG = high, the battery
isolation FET is off.
1
When disable IC1 mode is active, the VINx supply must always be connected and the supply voltage level must fulfill the following condition: VISO_Bx < VINx < 5.5 V.
2
When disable IC1 mode is active, the back gate of the LDO FET is not controlled. If the VINx pins are not connected to any voltage supply, the body diode of the LDO
FET can become forward biased and the voltage at VINx is VISO_Bx – VF (VF is the forward voltage of the LDO FET body diode).
ADP5062 Data Sheet
INTRODUCTION by an external USB detection device, the ADP5062 can be set to
The ADP5062 is a fully-programmable I2C charger for single apply the correct current limit for optimal charging and USB
cell lithium-ion or lithium-polymer batteries suitable for a wide compliance. The USB charger permits correct operation under
range of portable applications. all USB compliant sources such as wall chargers, host chargers,
hub chargers, and standard host and hubs.
The linear charger architecture enables up to 2.1 A output
current at 4.3 V to 5.0 V (I2C programmable) on the system A processor can control the USB charger using the I2C to
power supply, and up to 1.3 A charge current into the battery program the charging current and numerous other parameters,
from a dedicated charger. including
The ADP5062 operates from an input voltage of 4 V up to 6.7 V • Trickle charge current level
but is tolerant of voltages of up to 20 V. The 20 V voltage tolerance • Trickle charge voltage threshold
alleviates the concerns of the USB bus spiking during discon- • Weak charge (constant current) current level
nection or connection scenarios. • Fast charge (constant current) current level
The ADP5062 features an internal FET between the linear charger • Fast charge (constant voltage) voltage level at 1% accuracy
output and the battery. This feature permits battery isolation • Fast charge safety timer period
and, hence, system powering under a dead battery or no battery • Watchdog safety timer parameters
scenario, which allows for immediate system function upon • Weak battery threshold detection
connection to a USB power supply. • Charge complete threshold
The ADP5062 is fully compliant with USB 3.0 and the USB • Recharge threshold
Battery Charging Specification 1.2. The ADP5062 is chargeable • Charge enable/disable
via the mini USB VBUS pin from a wall charger, car charger, or • Battery pack temperature detection and automatic charger
USB host port. Based on the type of USB source, which is detected shutdown
Data Sheet ADP5062
VIN1 HIGH VOLTAGE ISO_S1

6 BLOCKING 9
TO USB VBUS LDO FET
OR WALL TO SYSTEM
ADAPTER VIN2 ISO_S2 LOAD
7 10
VIN3 ISO_S3
8 + 11
+
6.85V – LDO FET VIN LIMIT
CONTROL –
VIN
OVERVOLTAGE
CBP BATTERY
19 ISOLATION FET
TRICKLE
CURRENT
+ SOURCE
3.9V – 3MHz OSC ISO_B1
12
VIN GOOD +
– EOC
ISO_B2
13
SCL
1
CHARGE CONTROL ISO_B3
SDA + 14
17
– CV MODE
RECHARGE
I2C INTERFACE
DIG_IO1 AND
5
CONTROL LOGIC +
DIG_IO2
3 – WEAK
DIG_IO3
2
+ BATTERY
DETECTION
– TRICKLE SINK
BATTERY:
OPEN BAT_SNS
SHORT + 4
3.4V
–
1.9V
SYS_EN
16 BATTERY DETECTION
+
SYS_EN OUTPUT +
LOGIC
– VIN – 150mV
BATTERY OVERVOLTAGE
ILED COLD
ISOTHERMAL 115°C
TSD DOWN 110°C
TSD 140°C
WARNING 130°C
15
COOL
ILED OUTPUT NTC CURRENT
LOGIC CONTROL
WARM
HOT
+ THR
18
–
0.5V
NTC
THERMAL CONTROL
AGND
20
10806-029
SINGLE
CELL
Li-Ion
Figure 29. Block Diagram
ADP5062 Data Sheet
The ADP5062 includes a number of significant features to Table 9. DIG_IO1 Operation
optimize charging and functionality including DIG_IO1 Function
• Thermal regulation for maximum performance. 0 100 mA input current limit or I2C programmed
value
• USB host current limit.
1 500 mA input current limit or I2C programmed
• Termination voltage accuracy: ±1%. value (or reprogrammed I2C value from 100 mA
• Battery thermistor input with automatic charger shutdown default)
in the event that the battery temperature exceeds limits
USB Compatibility
(compliant with the JEITA Li-Ion battery charging
temperature specification). The ADP5062 features an I2C-programmable input current
• Three external pins (DIG_IO1, DIG_IO2, and DIG_IO3) limit to ensure compatibility with the requirements listed in
that directly control a number of parameters. These pins Table 10. The current limit defaults to 100 mA to allow com-
are factory programmable for maximum flexibility. They patibility with a USB host or hub that is not configured.
can be factory programmed for functions such as The I2C register default is 100 mA. An I2C write command to
• Enable/disable charging. the ILIM register overrides the DIG_IOx pins and the I2C
• Control of 100 mA or 500 mA input current limit. register default value can be reprogrammed for alternative
• Control of 1500 mA input current limit. requirements.
• Control of the battery charge current. When the input current-limit feature is used, the available input
• Interrupt output pin. current may be too low for the charger to meet the programmed
See the Digital Input and Output Options section for details. charging current, ICHG, thereby reducing the rate of charge and
setting the VIN_ILIM flag.
CHARGER MODES
Input Current Limit When connecting voltage to VINx without the proper voltage
level on the battery side, the high voltage blocking mechanism
The VINx input current limit is controlled via the internal I2C is in a state wherein it draws only the current of <1 mA until
ILIM bits. The input current limit can also be controlled via the VIN reaches the VIN_OK level.
DIG_IO1 pin (if factory programmed to do so) as outlined in
Table 9. Any change in the I2C default from 100 mA takes The ADP5062 charger provides support for the following con-
precedence over the pin setting. nections through the single connector VINx pin, as shown in
Table 10.
Table 10. Input Current Compatibility with Standard USB Limits

Mode Standard USB Limit ADP5062 Function
USB (China Only) 100 mA limit for standard USB host or hub 100 mA input current limit or I2C programmed value
300 mA limit for Chinese USB specification 300 mA input current limit or I2C programmed value
USB 2.0 100 mA limit for standard USB host or hub 100 mA input current limit or I2C programmed value
500 mA limit for standard USB host or hub 500 mA input current limit or I2C programmed value
USB 3.0 150 mA limit for superspeed USB 3.0 host or hub 150 mA input current limit or I2C programmed value
900 mA limit for superspeed, high speed USB host or hub 900 mA input current limit or I2C programmed value
charger
Dedicated Charger 1500 mA limit for dedicated charger or low/full speed USB host 1500 mA input current limit or I2C programmed value
or hub charger
Data Sheet ADP5062
Trickle Charge Mode Fast Charge Mode (Constant Current)
A deeply discharged Li-Ion cell can exhibit a very low cell voltage When the battery voltage exceeds VTRK_DEAD and VWEAK, the
making it unsafe to charge the cell at high current rates. The charger switches to fast charge mode, charging the battery with
ADP5062 charger uses a trickle charge mode to reset the battery the constant current, ICHG. During fast charge mode (constant
pack protection circuit and lift the cell voltage to a safe level for current), the CHARGER_STATUS bits are set to 010.
fast charging. A cell with a voltage below VTRK_DEAD is charged During constant current mode, other features may prevent the
with the trickle mode current, ITRK_DEAD. During trickle charging current, ICHG, from reaching its full programmed value. Isothermal
mode, the CHARGER_STATUS bits are set. charging mode or input current limiting for USB compatibility
During trickle charging, the ISO_Sx node is regulated to VISO_STRK can affect the value of ICHG under certain operating conditions.
by the LDO and the battery isolation FET is off, which means The voltage on ISO_Sx is regulated to stay at VISO_SFC by the
that the battery is isolated from the system power supply. battery isolation FET when VISO_Bx < VISO_SFC.
Trickle Charge Mode Timer Fast Charge Mode (Constant Voltage)
The duration of trickle charge mode is monitored to ensure that As the battery charges, its voltage rises and approaches the termi-
the battery is revived from its deeply discharged state. If trickle nation voltage, VTRM. The ADP5062 charger monitors the voltage
charge mode runs for longer than 60 minutes without the cell on the BAT_SNS pin to determine when charging should end.
voltage reaching VTRK_DEAD, a fault condition is assumed and However, the internal ESR of the battery pack combined with
charging stops. The fault condition is asserted on the CHARGER_ the printed circuit board (PCB) and other parasitic series
STATUS bits, allowing the user to initiate the fault recovery resistances creates a voltage drop between the sense point at the
procedure specified in the Fault Recovery section. BAT_SNS pin and the cell terminal. To compensate for this and to
Weak Charge Mode (Constant Current) ensure a fully charged cell, the ADP5062 enters a constant voltage
charging mode when the termination voltage is detected on the
When the battery voltage exceeds VTRK_DEAD but is less than
BAT_SNS pin. The ADP5062 reduces charge current gradually as
VWEAK, the charger switches to intermediate charge mode.
the cell continues to charge, maintaining a voltage of VTRM on the
During the weak charge mode, the battery voltage is too low to BAT_SNS pin. During fast charge mode (constant voltage), the
allow the full system to power-up. Because of the low battery CHARGER_ STATUS[2:0] bits are set to 011.
level, the USB transceiver cannot be powered and, therefore,
Fast Charge Mode Timer
cannot enumerate for more current from a USB host. Conse-
quently, the USB limit remains at 100 mA. The duration of fast charge mode is monitored to ensure that
the battery is charging correctly. If the fast charge mode runs
The system microcontroller may or may not be powered by the for longer than tCHG without the voltage at the BAT_SNS pin
charger output voltage (VISO_SFC), depending upon the amount reaching VTRM, a fault condition is assumed and charging stops.
of current that the microcontroller and/or the system architecture The fault condition is asserted on the CHARGER_STATUS[2:0]
requires. When the ISO_Sx pins power the microcontroller, the bits, allowing the user to initiate the fault recovery procedure as
battery charge current (ICHG_WEAK) cannot be increased above specified in the Fault Recovery section.
20 mA to ensure microcontroller operation (if doing so), nor
can ICHG_WEAK be increased above the 100 mA USB limit. There- If the fast charge mode runs for longer than tCHG, and VTRM has
fore, set the battery charging current as follows: been reached on the BAT_SNS pin but the charge current has
not yet fallen below IEND, charging stops. No fault condition is
• Set the default 20 mA via the linear trickle charger branch (to asserted in this circumstance and charging resumes as normal if
ensure that the microprocessor remains alive if powered by the recharge threshold is breached.
the main charger output, ISO_Sx). Any residual current on
the main charger output, ISO_Sx, is used to charge the
Watchdog Timer
battery. The ADP5062 charger features a programmable watchdog timer
• During weak current mode, other features may prevent the function to ensure charging is under the control of the processor.
weak charging current from reaching its full programmed The watchdog timer starts running when the ADP5062 charger
value. Isothermal charging mode or input current limiting for determines that the processor should be operational, that is,
USB compatibility can affect the programmed weak charging when the processor sets the RESET_WD bit for the first time or
current value under certain operating conditions. During when the battery voltage is greater than the weak battery threshold,
weak charging, the ISO_Sx node is regulated to VISO_SFC by VWEAK. When the watchdog timer has been triggered, it must be
the battery isolation FET. reset regularly within the watchdog timer period, tWD.
While in charger mode, if the watchdog timer expires without
being reset, the ADP5062 charger assumes that there is a software
problem and triggers the safety timer, tSAFE. For more infor-
mation see the Safety Timer section.
ADP5062 Data Sheet
Safety Timer Battery Voltage Limit to Prevent Charging
While in charger mode, if the watchdog timer expires, the The battery monitor of the ADP5062 charger can be configured
ADP5062 charger initiates the safety timer, tSAFE (see the to monitor battery voltage and prevent charging when the battery
Watchdog Timer section). If the processor has programmed voltage is higher than VCHG_VLIM (typically 3.7 V) during charging
charging parameters by the time the charger initiates the safety start-up (enabled by EN_CHG or DIG_IO3). This function can
timer, the ILIM is set to the default value. Charging continues for prevent unnecessary charging of a half discharged battery and,
a period of tSAFE, and then the charger switches off and sets the as such, can extend the lifetime of the Li-Ion battery cell. Charging
CHARGER_STATUS [2:0] bits. starts automatically when the battery voltage drops below VCHG_VLIM
Charge Complete and continues through full charge cycle until the battery voltage
reaches VTRM (typically 4.2 V).
The ADP5062 charger monitors the charging current while
in constant voltage fast charge mode. If the current falls By default, the charging voltage limit is disabled and it can be
below IEND and remains below IEND for tEND, charging stops enabled from I2C Register Address 0x08, Bit 5 (EN_CHG_VLIM).
and the CHDONE flag is set. If the charging current falls below SYS_EN Output
IEND for less than tEND and then rises above IEND again, the tEND The ADP5062 features a SYS_EN open-drain FET to enable the
timer resets. system until the battery is at the minimum required level for
Recharge guaranteed system start-up. When there are minimum battery
After the detection of charge complete, and the cessation of voltage and/or minimum battery charge level requirements, the
charging, the ADP5062 charger monitors the BAT_SNS pin as operation of SYS_EN can be set by I2C programming. The SYS_EN
the battery discharges through normal use. If the BAT_SNS pin operation can be factory programmed to four different operating
voltage falls to VRCH, the charger reactivates charging. Under most conditions as described in Table 11.
circumstances, triggering the recharge threshold results in the Table 11. SYS_EN Mode Descriptions
charger starting directly into fast charge constant voltage mode.
SYS_EN Mode
The recharge function can be disabled in the I2C, but a status bit Selection Description
(Register Address 0x0C, Bit 3) informs the system that a recharge 00 SYS_EN is activated when LDO is active and
cycle is required. system voltage is available.
IC Enable/Disable 01 SYS_EN is activated by the ISO_Bx voltage, the
battery charging mode.
The ADP5062 IC can be disabled by the DIG_IO2 digital input
pin (if factory programmed to do so) or by the I2C registers. All 10 SYS_EN is activated and the isolation FET is
disabled when the battery drops below VWEAK.
internal control circuits are disabled when the IC is disabled. Dis-
This option is active when VINx = 0 V and the
abling the IC1 option can also control the states of the LDO FET battery monitor is activated from Register 0x07,
and the battery isolation FET. Bit 5 (EN_BMON).
It is critical to note that during the disable IC1 mode, a high 11 SYS_EN is active in LDO mode when the charger is
voltage at VINx passes to the internal supply voltage because all disabled.
of the internal control circuits are disabled. The VINx supply SYS_EN is active in charging mode when VISO_Bx ≥
voltage must fulfill the following condition: VWEAK.
VISO_Bx < VINx < 5.5 V Indicator LED Output (ILED)
Battery Charging Enable/Disable The ILED is an open-drain output for an indicator LED connec-
The ADP5062 charging function can be disabled by setting the tion. Optionally, the ILED output can be used as a status output
I2C EN_CHG bit to low. The LDO to the system still operates for a microcontroller. Indicator LED modes are listed in Table 12.
under this circumstance and can be set in I2C to the default or
Table 12. Indicator LED Operation Modes
I2C programmed system voltage from 4.3 V to 5.0 V (see Table 26
ADP5062 Mode ILED Mode On/Off Time
for details).
IC Off Off
The ADP5062 charging function can also be controlled via one LDO Mode Off Off
of the external DIG_IOx pins (if factory programmed to do so). LDO Mode On Off
Any change in the I2C EN_CHG bit takes precedence over the pin Charge Mode Continuously on
setting. Timer Error (tTRK, tCHG, tSAFE) Blinking 167 ms/833 ms
Overtemperature (TSD) Blinking 1 sec/1 sec
Data Sheet ADP5062
THERMAL MANAGEMENT BATTERY ISOLATION FET
Isothermal Charging The ADP5062 charger features an integrated battery isolation
The ADP5062 includes a thermal feedback loop that limits the FET for power path control. The battery isolation FET isolates a
charge current when the die temperature exceeds TLIM (typically deeply discharged Li-Ion cell from the system power supply in
115°C). As the on-chip power dissipation and die temperature both trickle and fast charge modes, thereby allowing the system
increase, the charge current is automatically reduced to maintain to be powered at all times.
the die temperature within the recommended range. As the die When VINx is below VVIN_OK_RISE, the battery isolation FET is in
temperature decreases due to lower on-chip power dissipation full conducting mode.
or ambient temperature, the charge current returns to the pro-
The battery isolation FET is off during trickle charge mode.
grammed level. During isothermal charging, the THERM_LIM
When the battery voltage exceeds VTRK_DEAD, the battery iso-
I2C flag is set to high.
lation FET switches to the system voltage regulation mode.
This thermal feedback control loop allows the user to set the During system voltage regulation mode, the battery isolation
programmed charge current based on typical rather than worst FET maintains the VISO_SFC voltage on the ISO_Sx pins. When
case conditions. the battery voltage exceeds VISO_SFC, the battery isolation FET is
The ADP5062 does not include a thermal feedback loop to limit in full conducting mode.
ISO_Sx load current in LDO mode. If the power dissipated on The battery isolation FET supplements the battery to support
chip during LDO mode causes the die temperature to exceed high current functions on the system power supply. When the
130°C, an interrupt is generated. If the die temperature continues voltage on ISO_Sx drops below VISO_Bx, the battery isolation FET
to rise beyond 140°C, the device enters thermal shutdown. enters into full conducting mode. When voltage on ISO_Sx
Thermal Shutdown and Thermal Early Warning rises above VISO_Bx, the isolation FET enters regulating mode or
full conduction mode, depending on the Li-Ion cell voltage and
The ADP5062 charger features a thermal shutdown threshold
the linear charger mode.
detector. If the die temperature exceeds TSD, the ADP5062 charger
is disabled, and the TSD 140°C bit is set. The ADP5062 charger BATTERY DETECTION
can be reenabled when the die temperature drops below the TSD Battery Voltage Level Detection
falling limit and the TSD 140°C bit is reset. To reset the TSD
The ADP5062 charger features a battery detection mechanism to
140°C bit, write to the I2C fault register, Register Address 0x0D
detect an absent battery. The charger actively sinks and sources
(Bit 0) or cycle the power.
current into the ISO_Bx node, and voltage vs. time is detected.
Before the die temperature reaches TSD, the early warning bit is The sink phase is used to detect a charged battery, whereas the
set if TSDL is exceeded. This allows the system to accommodate source phase is used to detect a discharged battery.
power consumption before thermal shutdown occurs.
The sink phase (see Figure 30) sinks ISINK current from the ISO_Bx
Fault Recovery pins for a time period, tBATOK. If ISO_Bx is below VBATL when the
Before performing the following operation, it is important to tBATOK timer expires, the charger assumes no battery is present and
ensure that the cause of the fault has been rectified. starts the source phase. If the ISO_Bx pin exceeds the VBATL voltage
when the tBATOK timer expires, the charger assumes the battery is
To recover from a charger fault (when CHARGER_STATUS[2:0] =
present and begins a new charge cycle.
110), cycle power on VINx or write high to reset the I2C fault bits
in the fault register (Register Address 0x0D). The source phase sources ISOURCE current to the ISO_Bx pins for
a time period, tBATOK. If If ISO_Bx exceeds VBATH before the tBATOK
timer expires, the charger assumes that no battery is present. If
the ISO_Bx pin does not exceed the VBATH voltage when the tBATOK
timer expires, the charger assumes that a battery is present and
begins a new charge cycle.
ADP5062 Data Sheet
SINK PHASE SOURCE PHASE
VBATL LOGIC VBATH LOGIC
ISOURCE
STATUS STATUS
tBAT_OK tBAT_OK
OPEN
OR OPEN
SHORT
ISO_Bx ISO_Bx
ISINK
OPEN
OPEN
10806-030
Figure 30. Sink Phase
SINK PHASE SOURCE PHASE TRICKLE CHARGE

VBATL VBATH VBAT_SHR
LOGIC LOGIC LOGIC
ITRK_DEAD
STATUS STATUS STATUS
ISOURCE
tBAT_OK tBAT_OK tBAT_SHR

SHORT
OPEN OR
OR SHORT
LOW
ISO_Bx SHORT ISO_Bx BATTERY ISO_Bx
ISINK
SHORT
SHORT
SHORT
10806-031
Figure 31. Trickle Charge
Battery (ISO_Bx) Short Detection The battery pack temperature sensing can be controlled by
A battery short occurs under a damaged battery condition or I2C, using the conditions shown in Table 13. Note that the
when the battery protection circuitry is enabled. I2C register default setting for EN_THR (Register Address 0x07)
is 0 = temperature sensing off.
On commencing trickle charging, the ADP5062 charger moni-
tors the battery voltage. If this battery voltage does not exceed Table 13. THR Input Function
VBAT_SHR within the specified timeout period, tBAT_SHR, a fault is Conditions
declared and the charger is stopped by turning the battery VINx VISO_Bx THR Function
isolation FET off, but the system voltage is maintained at Open or VIN = 0 V to 4.0 V <2.5 V Off
VISO_STRK by the linear regulator. Open or VIN = 0 V to 4.0 V >2.5 V Off, controlled by I2C
After source phase, if the ISO_Bx or BAT_SNS level remains 4.0 V to 6.7 V Don't care Always on
below VBATH, either the battery voltage is low or the battery node If the battery pack thermistor is not connected directly to the
is shorted. Because the battery voltage is low, trickle charging mode THR pin, a 10 kΩ (tolerance ±20%) dummy resistor must be
is initiated (see Figure 31). If the BAT_SNS level remains below connected between the THR input and GND. Leaving the THR
VBAT_SHR after tBAT_SHR has elapsed, the ADP5062 assumes that the pin open results in a false detection of the battery temperature
battery node is shorted. being <0°C and charging is disabled.
The trickle charge branch is active during the battery short The ADP5062 charger monitors the voltage in the THR pin and
scenario, and trickle charge current to the battery is main- suspends charging when the current is outside the range of less
tained until the 60-minute trickle charge mode timer expires. than 0°C or greater than 60°C.
BATTERY PACK TEMPERATURE SENSING The ADP5062 charger is designed for use with an NTC thermistor
Battery Thermistor Input in the battery pack with a nominal room temperature value of
The ADP5062 charger features battery pack temperature sensing either 10 kΩ at 25°C or 100 kΩ at 25°C, which is selected by
that precludes charging when the battery pack temperature is factory programming.
outside the specified range. The THR pin provides an on and The ADP5062 charger is designed for use with an NTC thermistor
off switching current source that should be connected directly in the battery pack with a temperature coefficient curve (beta).
to the battery pack thermistor terminal. The activation interval Factory programming supports eight beta values covering a
of the THR current source is 167 ms. range from 3150 to 4400 (see Table 43).
Data Sheet ADP5062
JEITA Li-Ion Battery Temperature Charging Specification Alternatively, the JEITA1 or JEITA2 can be set as enabled to
The ADP5062 is compliant with the JEITA1 and JEITA2 Li-Ion default by factory programming.
battery charging temperature specifications as outlined in Table 14 When the ADP5062 identifies a hot or cold battery condition,
and Table 16, respectively. the ADP5062 takes the following actions:
JEITA function can be enabled via the I2C interface and, optionally, • Stops charging the battery.
the JEITA1 or JEITA2 function can be selected in I2C. • Connects or enables the battery isolation FET such that the
ADP5062 continues in LDO mode.
Table 14. JEITA1 Specifications
Parameter Symbol Conditions Min Max Unit
JEITA1 Cold Temperature Limits IJEITA_COLD No battery charging occurs. 0 °C
JEITA1 Cool Temperature Limits IJEITA_COOL Battery charging occurs at approximately 50% of the programmed 0 10 °C
level. See Table 15 for specific charging current reduction levels.
JEITA1 Typical Temperature Limits IJEITA_TYP Normal battery charging occurs at the default/programmed levels. 10 45 °C
JEITA1 Warm Temperature Limits IJEITA_WARM Battery termination voltage (VTRM) is reduced by 100 mV from the 45 60 °C
programmed value.
JEITA1 Hot Temperature Limits IJEITA_HOT No battery charging occurs. 60 °C
Table 15. JEITA1 Reduced Charge Current Levels, Battery Cool Temperature
ICHG[4:0] (Default) ICHG JEITA1 ICHG[4:0] (Default) ICHG JEITA1
00000 = 50 mA 50 mA 01100 = 650 mA 300 mA
00001 = 100 mA 50 mA 01101 = 700 mA 350 mA
00010 = 150 mA 50 mA 01110 = 750 mA 350 mA
00011 = 200 mA 100 mA 01111 = 800 mA 400 mA
00100 = 250 mA 100 mA 10000 = 850 mA 400 mA
00101 = 300 mA 150 mA 10001 = 900 mA 450 mA
00110 = 350 mA 150 mA 10010 = 950 mA 450 mA
00111 = 400 mA 200 mA 10011 = 1000 mA 500 mA
01000 = 450 mA 200 mA 10100 = 1050 mA 500 mA
01001 = 500 mA 250 mA 10101 = 1100 mA 550 mA
01010 = 550 mA 250 mA 10110 = 1200 mA 600 mA
01011 = 600 mA 300 mA 10111 = 1300 mA 650 mA
Table 16. JEITA2 Specifications

Parameter Symbol Conditions Min Max Unit
JEITA2 Cold Temperature Limits IJEITA_COLD No battery charging occurs. 0 °C
JEITA2 Cool Temperature Limits IJEITA_COOL Battery termination voltage (VTRM) is reduced by 100 mV from the 0 10 °C
programmed value.
JEITA2 Typical Temperature Limits IJEITA_TYP Normal battery charging occurs at the default/programmed levels. 10 45 °C
JEITA2 Warm Temperature Limits IJEITA_WARM Battery termination voltage (VTRM) is reduced by 100 mV from the 45 60 °C
programmed value.
JEITA2 Hot Temperature Limits IJEITA_HOT No battery charging occurs. 60 °C
ADP5062 Data Sheet
POWER-ON RESET
RESET ALL
REGISTERS
NO
IC OFF
NO VIN_OK =
HIGH
SYSTEM
OFF
YES
YES ENABLE NO ENABLE

CHARGER LDO
YES LDO MODE
ENABLE NO
CHARGER
YES
LOW YES VBAT_SNS NO

BATTERY < VCHG_VLIM
CHG
NO YES
10806-032
TO
CHARGING MODE
Figure 32. Simplified Battery and VINx Connect Flowchart
Data Sheet ADP5062
TO CHARGING
MODE TO IC OFF
RUN YES
BATTERY
DETECTION
tSTART NO
EXPIRED
YES VBAT_SNS NO
< VTRK
POWER-DOWN
TRICKLE
CHARGE FAST CHARGE
VIN_OK = NO VIN_OK = NO
HIGH HIGH
YES YES
VBAT_SNS NO NO VIN_ILIM = HIGH

IVINx < ILIM
< VTRK IVINx = ILIM
YES YES
WATCHDOG
EXPIRED YES
START tSAFE tWD EXPIRED NO THERM_LIM = HIGH
TEMP < TLIM
IBUS = 100mA TEMP = TLIM
NO
YES
TIMER FAULT YES

OR tSAFE OR tTRK WATCHDOG
BAD BATTERY EXPIRED YES EXPIRED
tWD EXPIRED START tSAFE
IBUS = 100 mA
NO
NO
YES1 TIMER FAULT OR

tSAFE OR tCHG BAD BATTERY
EXPIRED 1SEE TIMER SPECS
RUN NO
BATTERY
DETECTION
VBAT_SNS = NO CC MODE
YES VTRM CHARGING
VBAT_SNS = YES
VRCH
NO CHARGE YES NO CV MODE

IOUT < IEND
10806-033
COMPLETE CHARGING
Figure 33. Simplified Charging Mode Flowchart
ADP5062 Data Sheet
I2C INTERFACE the master after the 8-bit data byte has been written (see Figure 34
The ADP5062 includes an I2C-compatible serial interface for for an example of the I2C write sequence to a single register).
control of the charging and LDO functions, as well as for a The ADP5062 increments the subaddress automatically and
readback of the system status registers. The I2C chip address starts receiving a data byte at the next register until the master
is 0x28 in write mode and 0x29 in read mode. sends an I2C stop as shown in Figure 35.
Register values are reset to the default values when the VINx Figure 36 shows the I2C read sequence of a single register.
supply falls below the falling voltage threshold, VVIN_OK_FALL. ADP5062 sends the data from the register denoted by the
The I2C registers also reset when the battery is disconnected and subaddress and increments the subaddress automatically,
VIN is 0 V. sending data from the next register until the master sends an
I2C stop condition, as shown in Figure 37.
The subaddress content selects which of the ADP5062 registers
is written to first. The ADP5062 sends an acknowledgement to
0 = WRITE MASTER STOP
ST 0 0 1 0 1 0 0 0 0 0 0 SP
ADP5062 ACK
ADP5062 ACK
ADP5062 ACK
CHIP ADDRESS SUBADDRESS ADP5062 RECEIVES
DATA
10806-034
Figure 34. I2C Single Register Write Sequence
0 = WRITE MASTER STOP
ST 0 0 1 0 1 0 0 0 0 0 0 0 0 SP
ADP5062 ACK
ADP5062 ACK
ADP5062 ACK
ADP5062 ACK
ADP5062 ACK
CHIP ADDRESS SUBADDRESS ADP5062 RECEIVES ADP5062 RECEIVES ADP5062 RECEIVES
REGISTER N DATA TO REGISTER N DATA TO REGISTER N + 1 DATA TO LAST REGISTER
10806-035
Figure 35. I2C Multiple Register Write Sequence
MASTER
0 = WRITE 1 = READ STOP
ST 0 0 1 0 1 0 0 0 0 0 ST 0 0 1 0 1 0 0 1 0 0 1 SP
MASTER ACK
ADP5062 ACK
ADP5062 ACK
ADP5062 ACK
CHIP ADDRESS SUBADDR ESS CHIP ADDRESS ADP5062 SEND

SDATA
10806-036
Figure 36. I2C Single Register Read Sequence
MASTER
0 = WRITE 1 = READ STOP
ST 0 0 1 0 1 0 0 0 0 0 ST 0 0 1 0 1 0 0 1 0 0 0 0 1 SP
MASTER ACK
MASTER ACK
ADP5062 ACK
ADP5062 ACK
ADP5062 ACK
MASTER ACK
CHIP ADDRESS SUBADDRESS CHIP ADDRESS ADP5062 SENDS ADP5062 SENDS ADP5062 SENDS
REGISTER N DATA OF REGISTER N DATA OF REGISTER DATA OF LAST
N+1 REGISTER
10806-037
Figure 37. I2C Multiple Register Read Sequence
Data Sheet ADP5062
I2C REGISTER MAP
See the Factory-Programmable Options section for programming option details. Note that a blank cell indicates a bit that is not used or is
reserved for future use.
Table 17. I2C Register Map

Register
Addr. Name D7 D6 D5 D4 D3 D2 D1 D0
0x00 Manufac- MANUF[3:0] Model[3:0]
turer and
model ID
0x01 Silicon REV[3:0]
revision
0x02 VINx pin ILIM[3:0] 1
settings
0x03 Termination VTRM[5:0]1, 2 CHG_VLIM[1:0]1, 2
settings
0x04 Charging ICHG[4:0]1, 2 ITRK_DEAD[1:0]1
current
settings
0x05 Voltage DIS_RCH1, 3 VRCH[1:0]1 VTRK_DEAD[1:0]1, 3 VWEAK[2:0]1
thresholds
0x06 Timer EN_TEND1 EN_CHG_TIMER1 CHG_TMR_PERIOD1 EN_WD1, 3 WD_PERIOD1 RESET_WD
settings
0x07 Functional DIS_IC11 EN_BMON1 EN_THR1 DIS_LDO1 EN_EOC1 EN_CHG1
Settings 1
0x08 Functional EN_JEITA1, 3 JEITA_SELECT1, 3 EN_CHG_VLIM1, 3 IDEAL_DIODE[1:0]1, 3 VSYSTEM[2:0]1, 3
Settings 2
0x09 Interrupt EN_THERM_LIM_INT EN_WD_INT EN_TSD_INT EN_THR_INT EN_BAT_INT EN_CHG_INT EN_VIN_INT
enable
0x0A Interrupt THERM_LIM_INT WD_INT TSD_INT THR_INT BAT_INT CHG_INT VIN_INT
active
0x0B Charger VIN_OV VIN_OK VIN_ILIM THERM_LIM CHDONE CHARGER_STATUS[2:0]
Status 1
0x0C Charger THR_STATUS[2:0] RCH_LIM_INFO BATTERY_STATUS[2:0]
Status 2
0x0D Fault BAT_SHR1 TSD 130°C1 TSD 140°C1
0x10 Battery TBAT_SHR[2:0]1 VBAT_SHR[2:0]1
short
0x11 IEND IEND[2:0]1, 3 C/20 EOC1 C/10 EOC1 C/5 EOC1 SYS_EN_SET[1:0]1, 3
1
These bits reset to default I2C values when VINx is connected or disconnected.
2
The default I2C values of these bits are partially factory programmable.
3
The default I2C values of these bits are fully factory programmable.
ADP5062 Data Sheet
REGISTER BIT DESCRIPTIONS
In Table 18 through Table 33, the following abbreviations are used: R is read only, W is write only, R/W is read/write, and N/A means not
applicable.
Table 18. Manufacturer and Model ID, Register Address 0x00

Bit No. Bit Name Access Default Description
[7:4] MANUF[3:0] R 0001 The 4-bit manufacturer identification bus
[3:0] MODEL[3:0] R 1001 The 4-bit model identification bus
Table 19. Silicon Revision, Register Address 0x01

[7:4] Not used R
[3:0] REV[3:0] R 0100/ADP5062ACPZ-1-R7 The 4-bit silicon revision identification bus
0111/ADP5062ACPZ-2-R7
Table 20. VINx Pin Settings, Register Address 0x02

[7:5] Not used R
4 RFU R/W 0 Reserved for future use.
[3:0] ILIM[3:0] R/W 0000 = 100 mA VINx input current-limit programming bus. The current into VINx can
be limited to the following programmed values:
0000 = 100 mA.
0001 = 150 mA.
0010 = 200 mA.
0011 = 250 mA.
0100 = 300 mA.
0101 = 400 mA.
0110 = 500 mA.
0111 = 600 mA.
1000 = 700 mA.
1001 = 800 mA.
1010 = 900 mA.
1011 = 1000 mA.
1100 = 1200 mA.
1101 = 1500 mA.
1110 = 1800 mA.
1111 = 2100 mA.
Data Sheet ADP5062
Table 21. Termination Settings, Register Address 0x03
[7:2] VTRM[5:0] R/W 100011 = 4.20 V Termination voltage programming bus. The values of the floating voltage can
be programmed to the following values:
000101 = 3.60 V.
000110 = 3.62 V.
000111 = 3.64 V.
001000 = 3.66 V.
001001 = 3.68 V.
001010 = 3.70 V.
001011 = 3.72 V.
001100 = 3.74 V.
001101 = 3.76 V.
001110 = 3.78 V.
001111 = 3.80 V.
010000 = 3.82 V.
010001 = 3.84 V.
010010 = 3.86 V.
010011 = 3.88 V.
010100 = 3.90 V.
010101 = 3.92 V.
010110 = 3.94 V.
010111 = 3.96 V.
011000 = 3.98 V.
011001 = 4.00 V.
011010 = 4.02 V.
011011 = 4.04 V.
011100 = 4.06 V.
011101 = 4.08 V.
011110 = 4.10 V.
011111 = 4.12 V.
100000 = 4.14 V.
100001 = 4.16 V.
100010 = 4.18 V.
100011 = 4.20 V.
100100 = 4.22 V.
100101 = 4.24 V.
100110 = 4.26 V.
100111 = 4.28 V.
101000 = 4.30 V.
101001 = 4.32 V.
101010 = 4.34 V.
101011 = 4.36 V.
101100 = 4.38 V.
101101 = 4.40 V.
101110 = 4.42 V.
101111 = 4.44 V.
110000 = 4.44 V.
110001 = 4.46 V.
110010 = 4.48 V.
110011 to 111111 = 4.50 V.
[1:0] CHG_VLIM[1:0] R/W 00 = 3.2 V Charging voltage limit programming bus. The values of the charging voltage
limit can be programmed to the following values:
00 = 3.2 V.
01 = 3.4 V.
10 = 3.7 V.
11 = 3.8 V.
ADP5062 Data Sheet
Table 22. Charging Current Settings, Register Address 0x04
7 Not used R
[6:2] ICHG[4:0] R/W 01110 = 750 mA Fast charge current programming bus. The values of the constant
current charge can be programmed to the the following values:
00000 = 50 mA.
00001 = 100 mA.
00010 = 150 mA.
00011 = 200 mA.
00100 = 250 mA.
00101 = 300 mA.
00110 = 350 mA.
00111 = 400 mA.
01000 = 450 mA.
01001 = 500 mA.
01010 = 550 mA.
01011 = 600 mA.
01100 = 650 mA.
01101 = 700 mA.
01110 = 750 mA.
01111 = 800 mA.
10000 = 850 mA.
10001 = 900 mA.
10010 = 950 mA.
10011 = 1000 mA.
10100 = 1050 mA.
10101 = 1100 mA.
10110 = 1200 mA.
10111 to 11111 = 1300 mA.
[1:0] ITRK_DEAD[1:0] R/W 10 = 20 mA Trickle and weak charge current programming bus. The values of
the trickle and weak charge currents can be programmed to the
following values:
00 = 5 mA.
01 = 10 mA.
10 = 20 mA.
11 = 80 mA.
Table 23. Voltage Thresholds, Register Address 0x05

7 DIS_RCH R/W 0 = recharge 0 = recharge enabled.
enabled 1 = recharge disabled.
[6:5] VRCH[1:0] R/W 11 = 260 mV Recharge voltage programming bus. The values of the recharge
threshold can be programmed to the following values (note that
the recharge cycle can be disabled in I2C by using the DIS_RCH bit):
00 = 80 mV.
01 = 140 mV.
10 = 200 mV.
11 = 260 mV.
Data Sheet ADP5062
[4:3] VTRK_DEAD[1:0] R/W 01 = 2.5 V Trickle to fast charge dead battery voltage programming bus. The
values of the trickle to fast charge threshold can be programmed to
the following values:
00 = 2.0 V.
01 = 2.5 V.
10 = 2.6 V.
11 = 2.9 V.
[2:0] VWEAK[2:0] R/W 011 = 3.0 V Weak battery voltage rising threshold.
000 = 2.7 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.1 V.
101 = 3.2 V.
110 = 3.3 V.
111 = 3.4 V.
Table 24. Timer Settings, Register Address 0x06

[7:6] Not used
5 EN_TEND R/W 1 0 = charge complete timer, tEND, disabled. A 31 ms deglitch timer
remains on.
1 = charge complete timer enabled.
4 EN_CHG_TIMER R/W 1 0 = trickle/fast charge timer disabled.
1 = trickle/fast charge timer enabled.
3 CHG_TMR_PERIOD R/W 1 Trickle and fast charge timer period.
0 = 30 sec trickle charge timer and 300 minute fast charge timer.
1 = 60 sec trickle charge timer and 600 minute fast charge timer.
2 EN_WD R/W 0 0 = watchdog timer is disabled even when BAT_SNS exceeds VWEAK.
1 = watchdog timer safety timer is enabled.
1 WD_PERIOD R/W 0 Watchdog safety timer period.
0 = 32 sec watchdog timer and 40 minute safety timer.
1 = 64 sec watchdog timer and 40 minute safety timer.
0 RESET_WD W 0 When RESET_WD is set to logic high by I2C, the watchdog safety
timer is reset.
Table 25. Functional Settings 1, Register Address 0x07

7 Not used
6 DIS_IC1 R/W 0 0 = normal operation.
1 = the ADP5062 is disabled; VVINx must be VISO_Bx < VVINx < 5.5 V.
5 EN_BMON R/W 0 0 = when VVINx < VVIN_OK_RISE or VVIN_OK_FALL, the battery monitor is
disabled. When VVINx = 4.0 V to 6.7 V, the battery monitor is enabled
regardless of the EN_BMON state.
1 = the battery monitor is enabled even when the voltage at the
VINx pins is below VVIN_OK.
4 EN_THR R/W 0 0 = when VVINx < VVIN_OK_RISE or VVIN_OK_FALL, the THR current source is
disabled. When VVINx = 4.0 V to 6.7 V, the THR current source is
enabled regardless of the EN_THR state.
1 = THR current source is enabled even when the voltage at the
VINx pins is below VVIN_OK_RISE or VVIN_OK_FALL.
3 DIS_LDO R/W 0 0 = LDO is enabled.
1 = LDO is off. In addition, if EN_CHG = low, the battery isolation
FET is on. If EN_CHG = high, the battery isolation FET is off.
ADP5062 Data Sheet
2 EN_EOC R/W 1 0 = end of charge not allowed.
1 = end of charge allowed.
1 Not used
0 EN_CHG R/W 0 0 = battery charging is disabled.
1 = battery charging is enabled.
Table 26. Functional Settings 2, Register Address 0x08

7 EN_JEITA R/W 0 = JEITA disabled 0 = JEITA compliance of the Li-Ion temperature battery charging
specifications is disabled.
1 = JEITA compliance enabled.
6 JEITA_SELECT R/W 0 = JEITA1 0 = JEITA1 is selected.
1 = JEITA2 is selected.
5 EN_CHG_VLIM R/W 0 0 = charging voltage limit disabled.
1 = voltage limit activated. The charger prevents charging until the
battery voltage drops below the VCHG_VLIM threshold.
[4:3] IDEAL_DIODE[1:0] R/W 00 00 = ideal diode operates constantly when VISO_Sx < VISO_Bx.
01 = ideal diode operates when VISO_Sx < VISO_Bx and VBAT_SNS > VWEAK.
10 = ideal diode is disabled.
11 = ideal diode is disabled.
[2:0] VSYSTEM[2:0] R/W See Table 41 for System voltage programming bus. The values of the system voltage
model specific can be programmed to the following values:
default value. 000 = 4.3 V.
001 = 4.4 V.
010 = 4.5 V.
011 = 4.6 V.
100 = 4.7 V.
101 = 4.8 V.
110 = 4.9 V.
111 = 5.0 V.
Table 27. Interrupt Enable, Register Address 0x09

7 Not used
6 EN_THERM_LIM_INT R/W 0 0 = isothermal charging interrupt is disabled.
1 = isothermal charging interrupt is enabled.
5 EN_WD_INT R/W 0 0 = watchdog alarm interrupt is disabled.
1 = watchdog alarm interrupt is enabled.
4 EN_TSD_INT R/W 0 0 = overtemperature interrupt is disabled.
1 = overtemperature interrupt is enabled.
3 EN_THR_INT R/W 0 0 = THR temperature thresholds interrupt is disabled.
1 = THR temperature thresholds interrupt is enabled.
2 EN_BAT_INT R/W 0 0 = battery voltage thresholds interrupt is disabled.
1 = battery voltage thresholds interrupt is enabled.
1 EN_CHG_INT R/W 0 0 = charger mode change interrupt is disabled.
1 = charger mode change interrupt is enabled.
0 EN_VIN_INT R/W 0 0 = VINx pin voltage thresholds interrupt is disabled.
1 = VINx pin voltage thresholds interrupt is enabled.
Data Sheet ADP5062
Table 28. Interrupt Active, Register Address 0x0A
7 Not used
6 THERM_LIM_INT R 0 1 = indicates an interrupt caused by isothermal charging.
5 WD_INT R 0 1 = indicates an interrupt caused by the watchdog alarm. The
watchdog timer expires within 2 sec or 4 sec, depending on the
watch dog period setting of 32 sec or 64 sec, respectively.
4 TSD_INT R 0 1 = indicates an interrupt caused by an overtemperature fault.
3 THR_INT R 0 1 = indicates an interrupt caused by THR temperature thresholds.
2 BAT_INT R 0 1 = indicates an interrupt caused by battery voltage thresholds.
1 CHG_INT R 0 1 = indicates an interrupt caused by a charger mode change.
0 VIN_INT R 0 1 = indicates an interrupt caused by VINx voltage thresholds.
Table 29. Charger Status 1, Register Address 0x0B

7 VIN_OV R N/A 1 = the voltage at the VINx pins exceeds VVIN_OV.
6 VIN_OK R N/A 1 = the voltage at the VINx pins exceeds VVIN_OK_RISE, VVIN_OK_FALL.
5 VIN_ILIM R N/A 1 = the current into a VINx pin is limited by the high voltage blocking
FET and the charger is not running at the full programmed ICHG.
4 THERM_LIM R N/A 1 = the charger is not running at the full programmed ICHG but is
limited by the die temperature.
3 CHDONE R N/A 1 = the end of a charge cycle has been reached. This bit latches on,
in that it does not reset to low when the VRCH threshold is breached.
[2:0] CHARGER_STATUS[2:0] R N/A Charger status bus.
000 = off.
001 = trickle charge.
010 = fast charge (CC mode).
011 = fast charge (CV mode).
100 = charge complete.
101 = LDO mode.
110 = trickle or fast charge timer expired.
111 = battery detection.
ADP5062 Data Sheet
Table 30. Charger Status 2, Register Address 0x0C
Bit No. Mnemonic Access Default Description
[7:5] THR_STATUS[2:0] R N/A THR pin status.
000 = off.
001 = battery cold.
010 = battery cool.
011 = battery warm.
100 = battery hot.
111 = thermistor OK.
4 Not used
3 RCH_LIM_INFO R N/A The recharge limit information function is activated when DIS_RCH
is logic high and the CHARGER_STATUS[2:0] = 100 (binary). The
status bit informs the system that a recharge cycle is required.
0 = VBAT_SNS > VRCH
1 = VBAT_SNS < VRCH
[2:0] BATTERY_STATUS[2:0] R Battery status bus.
000 = battery monitor off.
001 = no battery.
010 = VBAT_SNS < VTRK_DEAD.
011 = VTRK_DEAD ≤ VBAT_SNS < VWEAK.
100 = VBAT_SNS ≥ VWEAK.
Table 31. Fault, 1 Register Address 0x0D

[7:4] Not used
3 BAT_SHR R/W 0 1 = indicates detection of a battery short.
2 Not used R/W
1 TSD 130°C R/W 0 1 = indicates an overtemperature (lower) fault.
0 TSD 140°C R/W 0 1 = indicates an overtemperature fault.
1
To reset the fault bits in the fault register, cycle power on VINx or write high to the corresponding I2C bit.
Table 32. Battery Short, Register Address 0x10

[7:5] TBAT_SHR[2:0] R/W 100 = 30 sec Battery short timeout timer.
000 = 1 sec.
001 = 2 sec.
010 = 4 sec.
011 = 10 sec.
100 = 30 sec.
101 = 60 sec.
110 = 120 sec.
111 = 180 sec.
[4:3] Not used
[2:0] VBAT_SHR[2:0] R/W 100 = 2.4 V Battery short voltage threshold level.
000 = 2.0 V.
001 = 2.1 V.
010 = 2.2 V.
011 = 2.3 V.
100 = 2.4 V.
101 = 2.5 V.
110 = 2.6 V.
111 = 2.7 V.
Data Sheet ADP5062
Table 33. IEND, Register Address 0x11
[7:5] IEND[2:0] R/W 010 = 52.5 mA Termination current programming bus. The values of the termination current can
be programmed to the following values:
000 = 12.5 mA.
001 = 32.5 mA.
010 = 52.5 mA.
011 = 72.5 mA.
100 = 92.5 mA.
101 = 117.5 mA.
110 = 142.5 mA.
111 = 170.0 mA.
4 C/20 EOC R/W 0 The C/20 EOC bit has priority over the other settings (C/5 EOC, C/10 EOC, and
IEND[2:0]).
1 = the termination current is ICHG[4:0] ÷ 20 with the following limitations:
Minimum value = 12.5 mA.
Maximum value = 170 mA.
3 C/10 EOC R/W 0 The C/10 EOC bit has priority over the other termination current settings (C/5 EOC
and IEND[2:0]), but does not have priority over the C/20 EOC setting.
1 = the termination current is ICHG[4:0] ÷ 10, unless C/20 EOC is high. The
termination current is limited to the following values:
2 C/5 EOC R/W 0 The C/5 EOC bit has priority over the other termination current settings (IEND[2:0])
but does not have priority over the C/20 EOC setting or the C/10 EOC setting.
1 = the termination current is ICHG[4:0] ÷ 5, unless the C/20 EOC or the C/10 EOC
bit is high. The termination current is limited to the following values:
1:0 SYS_EN_SET[1:0] R/W 00 Selects the operation of the system enable pin (SYS_EN).
00 = SYS_EN is activated when LDO is active and the system voltage is available.
01 = SYS_EN is activated by the ISO_Bx voltage, the battery charging mode.
10 = SYS_EN is activated and the isolation FET is disabled when the battery drops
below VWEAK. 1
11 = SYS_EN is active in LDO mode when the charger is disabled. SYS_EN is active
in the charging mode when VISO_Bx ≥ VWEAK.
1
This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit 5 (EN_BMON).
ADP5062 Data Sheet
APPLICATIONS INFORMATION
EXTERNAL COMPONENTS Substituting these values in the equation yields
ISO_Sx (VOUT) Capacitor Selection CEFF = 16 μF × (1 − 0.15) × (1 − 0.1) ≈ 12.24 μF
To obtain stable operation of the ADP5062 in a safe way, the To guarantee the performance of the charger in various operating
combined effective capacitance of the ISO_Sx capacitor and the modes, including trickle charge, constant current charge, and
system capacitance must not be less than 10 µF and must not constant voltage charge, it is imperative that the effects of dc
exceed 100 µF at any point during operation. bias, temperature, and tolerances on the behavior of the capaci-
tors be evaluated for each application.
When choosing the capacitor value, it is also important to account
for the loss of capacitance caused by the output voltage dc bias. Splitting ISO_Sx Capacitance
Ceramic capacitors are manufactured with a variety of dielectrics, In many applications, the total ISO_Sx capacitance consists of a
each with a different behavior over temperature and applied number of capacitors. The system voltage node (ISO_Sx) usually
voltage. Capacitors must have a dielectric that is adequate to ensure supplies a single regulator or a number of ICs and regulators,
the minimum capacitance over the necessary temperature range each of which requires a capacitor close to its power supply
and dc bias conditions. X5R or X7R dielectrics with a voltage rating input (see Figure 39).
of 6.3 V or higher are recommended for best performance. Y5V
The capacitance close to the ADP5062 ISO_Sx output should be
and Z5U dielectrics are not recommended for use with any dc-
at least 5 µF, as long as the total effective capacitance is at least
to-dc converter because of their poor temperature and dc bias
10 µF at any point during operation.
characteristics.
The worst case capacitance accounting for capacitor variation ISO_Sx VIN1
CISO_Sx > 5µF
over temperature, component tolerance, and voltage is calcu- CIN1
IC1
lated using the following equation: ADP5062
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)

ISO_Bx
SUM OF EFFECTIVE
where: CAPACITANCES
ON ISO_Sx NODE > 10µF
CEFF is the effective capacitance at the operating voltage. + CISO_Bx
≥10µF
TEMPCO is the worst case capacitor temperature coefficient.
VIN2
TOL is the worst case component tolerance. CIN2
IC2
In this example, the worst case temperature coefficient (TEMPCO)
10806-038
over the range of −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed Figure 39. Splitting ISO_Sx Capacitance
to be 10%, and COUT is 16 μF at 4.2 V, as shown in Figure 38.
60
ISO_Bx and ISO_Sx Capacitor Selection
The ISO_Bx and the ISO_Sx effective capacitance (including
55
temperature and dc bias effects) must not be less than 10 µF at
50 any point during operation. Typically, a nominal capacitance of
22 µF is required to fullfill the condition at all points of
CAPACITANCE (µF)
45
operation. Suggestions for ISO_Bx and ISO_Sx capacitors are
40 listed in Table 34.
35 CBP Capacitor Selection
30
The internal supply voltage of the ADP5062 is equipped with a
noise suppressing capacitor at the CBP terminal. Do not allow CBP
25 capacitance to exceed 14 nF at any point during operation. Do
20
not connect any external voltage source, any resistive load, or
10806-041
0 1 2 3 4 5 any other current load to the CBP terminal. Suggestions for a

DC BIAS VOLTAGE (V)
CBP capacitor are listed in Table 35.
Figure 38. Murata GRM31CR61A226KE19 Capacitance vs. Bias Voltage
Data Sheet ADP5062
VINx Capacitor Selection Table 34. ISO_Bx and ISO_Sx Capacitor Suggestions
According to the USB 2.0 specification, USB peripherals have a Vendor Part Number Value Voltage Size
detectable change in capacitance on VBUS when they are attached Murata GRM31CR61A226KE19 22 μF 10 V 1206
to a USB port. The peripheral device VBUS bypass capacitance Murata GRM31CR60J226ME19 22 μF 6.3 V 1206
must be at least 1 µF but not larger than 10 µF. TDK C3216X5R0J226M 22 µF 6.3 V 1206
The VINx input of the ADP5062 is tolerant of voltages as high Taiyo- JMK316ABJ226KL 22 µF 6.3 V 1206
as 20 V; however, if an application requires exposing the VINx Yuden
input to voltages of up to 20 V, the voltage range of the capacitor
Table 35. CBP Capacitor Suggestions
must also be above 20 V. Suggestions for a VINx capacitor are
Vendor Part Number Value Voltage Size
given in Table 36.
Murata GRM15XR71C103KA86 10 nF 16 V 0402
When using ceramic capacitors, a higher voltage range is usually TDK C1005X7R1C103K 10 nF 16 V 0402
achieved by selecting a component with larger physical dimensions.
In applications where lower than 20 V at VINx input voltages can Table 36. VINx Capacitor Suggestions
be guaranteed, smaller output capacitors can be used accordingly. Vendor Part Number Value Voltage Size
Murata GRM21BR61E106MA73 10 µF 25 V 0805
TDK C2012X5R1E106K 10 µF 25 V 0805
ADP5062 Data Sheet
PCB LAYOUT GUIDELINES
VIN = 4V TO 7V
C4
10µF
GRM21BR6E106MA73
6 7 8
VIN1 TO VIN3 ADP5062
20-LEAD LFCSP
19 CBP ISO_S1 TO ISO_S3

9
C1
10nF 10
GRM15XR71C103KA8
C3
11 22µF
GRM31CR60J226ME19
VDDIO
R1 R2 CHARGER
1.5kΩ 1.5kΩ CONTROL
BLOCK
TO MCU 1 SCL
TO MCU 17 SDA 12
TO MCU/NC 5 DIG_IO1 13
TO MCU/NC 3 DIG_IO2 14 CONNECT

ISO_B1 TO ISO_B3 CLOSE TO
TO MCU/NC 2 DIG_IO3
BATTERY +
BAT_SNS 4
VDDIO
THR 18
R4 C2
10kΩ R5 NTC 10kΩ 22µF
(OPTIONAL) GRM31CR60J22ME19
TO MCU 16 SYS_EN
VLED 15 ILED
AGND
20
10806-040
Figure 40. Reference Circuit Diagram
C1 – 10nF
CBP
16V/X7R
0402
PGND ISO_Bx
C2 – 22µF
16V/X5R
1206
ISO_Sx
PGND
VINx PGND
C4 – 10µF
25V/X5R C3 – 22µF
0805 16V/X5R
1206
10806-100
Figure 41. Reference PCB Floor Plan
Data Sheet ADP5062
POWER DISSIPATION AND THERMAL CONSIDERATIONS

CHARGER POWER DISSIPATION is higher and the power dissipation must be calculated using
Equation 3. When the battery voltage level reaches VISO_SFC, the
When the ADP5062 charger operates at high ambient tempera- power dissipation can be calculated using Equation 4.
tures and at maximum current charging and loading conditions,
the junction temperature can reach the maximum allowable PISOFET = RDSON_ISO × ICHG (4)
operating limit of 125°C. where:
When the junction temperature exceeds 140°C, the ADP5062 RDSON_ISO is the on resistance of the battery isolation FET
turns off, allowing the device to cool down. When the die (typically 110 mΩ during charging).
temperature falls below 110°C and the TSD 140°C fault bit in ICHG is the battery charge current.
Register 0x0D is cleared by an I2C write, the ADP5062 resumes The thermal control loop of the ADP5062 automatically limits
normal operation. the charge current to maintain a die temperature below TLIM
This section provides guidelines to calculate the power dissi- (typically 115°C).
pated in the device to ensure that the ADP5062 operates below The most intuitive and practical way to calculate the power
the maximum allowable junction temperature. dissipation in the ADP5062 device is to measure the power
To determine the available output current in different operating dissipated at the input and all of the outputs. Perform the
modes under various operating conditions, use the following measurements at the worst case conditions (voltages, currents,
equations: and temperature). The difference between input and output
power is the power that is dissipated in the device.
PD = PLDOFET + PISOFET (1)
JUNCTION TEMPERATURE
where:
PLDOFET is the power dissipated in the input LDO FET. In cases where the board temperature, TA, is known, the
PISOFET is the power dissipated in the battery isolation FET. thermal resistance parameter, θJA, can be used to estimate the
junction temperature rise. TJ is calculated from TA and PD using
Calculate the power dissipation in the LDO FET and the battery
the formula
isolation FET using Equation 2 and Equation 3.
TJ = TA + (PD × θJA) (5)
PLDOFET = (VIN – VISO_Sx) × (ICHG + ILOAD) (2)
The typical θJA value for the 20-lead LFCSP is 35.6°C/W (see
PISOFET = (VISO_Sx – VISO_Bx) × ICHG (3)
Table 5). A very important factor to consider is that θJA is based
where: on a 4-layer, 4 in × 3 in, 2.5 oz. copper board as per JEDEC
VIN is the input voltage at the VINx pins. standard, and real-world applications may use different sizes
VISO_Sx is the system voltage at the ISO_Sx pins. and layers. It is important to maximize the copper to remove the
VISO_Bx is the battery voltage at the ISO_Bx pins. heat from the device. Copper exposed to air dissipates heat
ICHG is the battery charge current. better than copper used in the inner layers.
ILOAD is the system load current from the ISO_Sx pins.
If the case temperature can be measured, the junction
LDO Mode temperature is calculated by
The system regulation voltage is user-programmable from 4.3 V TJ = TC + (PD × θJC) (6)
to 5.0 V. In LDO mode (charging disabled, EN_CHG = low),
where TC is the case temperature and θJC is the junction-to-case
calculation of the total power dissipation is simplified, assuming
thermal resistance provided in Table 5.
that all current is drawn from the VINx pins and the battery is
not shared with ISO_Sx. The reliable operation of the charger can be achieved only if the
estimated die junction temperature of the ADP5062 (Equation 5)
PD = (VIN – VISO_Sx) × ILOAD
is less than 125°C. Reliability and mean time between failures
Charging Mode (MTBF) are greatly affected by increasing the junction temperature.
In charging mode, the voltage at the ISO_Sx pins depends on Additional information about product reliability can be found in
the battery level. When the battery voltage is lower than VISO_SFC the ADI Reliability Handbook located at the following URL:
(typically 3.8 V), the voltage drop over the battery isolation FET www.analog.com/reliability_handbook.
ADP5062 Data Sheet
FACTORY-PROGRAMMABLE OPTIONS
CHARGER OPTIONS
Table 37 to Table 49 list the factory-programmable options of the ADP5062. In each of these tables, the selection column represents the
default setting of Model ADP5062ACPZ-1-R7 and Model ADP5062ACPZ-2-R7.
Table 37. Default Termination Voltage Table 41. Default System Voltage
Option Selection Option Selection
000 = 4.20 V 000 = 4.20 V 000 = 4.3 V 000 = 4.3 V/ADP5062ACPZ-2-R7
010 = 3.70 V 001 = 4.4 V
011 = 3.80 V 010 = 4.5 V
100 = 3.90 V 011 = 4.6 V
101 = 4.00 V 100 = 4.7 V
110 = 4.10 V 101 = 4.8 V
111 = 4.40 V 110 = 4.9 V
Table 38. Default Fast Charge Current 111 = 5.0 V 111 = 5.0 V/ADP5062ACPZ-1-R7
Option Selection Table 42. Thermistor Resistance

000 = 500 mA Option Selection
001 = 300 mA 0 = 10 kΩ 0 = 10 kΩ
010 = 550 mA 1 = 100 kΩ
011 = 600 mA
100 = 750 mA 100 = 750 mA Table 43. Thermistor Beta Value
101 = 900 mA Option Selection
110 = 1300 mA 0100 = 3150 0100 = 3150
111 = 1300 mA 0101 = 3350
0110 = 3500
Table 39. Default End of Charge Current 0111 = 3650
Option Selection 1000 = 3850
000 = 52.5 mA 000 = 52.5 mA 1001 = 4000
001 = 72.5 mA 1010 = 4200
010 = 12.5 mA 1011 = 4400
011 = 32.5 mA
100 = 142.5 mA Table 44. DIS_IC1 Mode Select
101 = 167.5 mA Option Selection
110 = 92.5 mA 0 = DIC_IC1 mode select, VINx current = 280 µA, 0
111 = 117.5 mA ISO_Bx can float, no leak to ISO_Bx
1 = DIC_IC1 mode select, VINx current = 110 µA,
Table 40. Default Trickle to Fast Charge Threshold supply switch leaks from VINx to ISO_Bx
Option Selection
Table 45. Trickle or Fast Charge Timer Fault Operation
00 = 2.5 V 00 = 2.5 V
Option Selection
01 = 2.0 V
0 = after timeout LDO off, charging off
10 = 2.9 V
1 = after timeout LDO mode active, charging off 1 = LDO
11 = 2.6 V
mode
active
Data Sheet ADP5062
I2C REGISTER DEFAULTS
Table 46. I2C Register Default Settings
Bit Name I2C Register Address, Bit Location Option Selection
CHG_VLIM[1:0] Address 0x03, Bits[1:0] 0 = limit 3.2 V 0 = limit 3.2 V
1 = limit 3.7 V
DIS_RCH Address 0x05, Bit 7 0 = recharge enabled 0 = recharge enabled
1 = recharge disabled
EN_WD Address 0x06, Bit 2 0 = watchdog disabled 0 = disabled
1 = watchdog enabled
DIS_IC1 Address 0x07, Bit 6 0 = not activated 0 = not activated
1 = activated
EN_CHG Address 0x07, Bit 0 0 = charging disabled 0 = charging disabled
1 = charging enabled
EN_JEITA Address 0x08, Bit 7 0 = JEITA disabled 0 = JEITA disabled
1 = JEITA enabled
JEITA_SELECT Address 0x08, Bit 6 0 = JEITA1 charging 0 = JEITA1 charging
1= JEITA2 charging
EN_CHG_VLIM Address 0x08, Bit 5 0 = limit disabled 0 = limit disabled
1 = limit enabled
IDEAL_DIODE[1:0] Address 0x08, Bits[4:3] 00 = ideal diode operates when VISO_Sx < VISO_Bx 00 = VISO_Sx < VISO_Bx
01 = ideal diode operates when VISO_Sx < VISO_Bx
and VBAT_SNS > VWEAK
10 = ideal diode is disabled
11 = ideal diode is disabled
DIGITAL INPUT AND OUTPUT OPTIONS

Table 47. I2C Address 0x11, Bits[1:0] SYS_EN Output Default
Option Selection (Default)
00 = SYS_EN is activated when LDO is active and system voltage is available 00
01 = SYS_EN is activated by ISO_Bx voltage; battery charging mode
10 = SYS_EN is activated and the isolation FET is disabled when the battery drops below VWEAK 1
11 = SYS_EN is active in LDO mode when the charger is disabled. SYS_EN is active in charging mode when VISO_Bx ≥ VWEAK
1
This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit D5 (EN_BMON).
ADP5062 Data Sheet
DIG_IO1, DIG_IO2, and DIG_IO3 Options
Table 48. DIG_IO1 Polarity
Option Selection
0 = DIG_IO1 polarity, high active operation 0 = high active
1 = DIG_IO1 polarity, low active operation
Table 49. DIG_IOx Options

Option DIG_IO1 Function DIG_IO2 Function DIG_IO3 Function Selection
0000 IVINx limit Disable IC1 Charging disable/enable 0000
Low = 100 mA Low = not activated Low = charging disable
High = 500 mA High = activated High = charging enabled
0010 IVINx limit IVINx limit Disable IC1
Low = 100 mA N/A Low = not activated
High= 500 mA High = IVINx limit 1500 mA High = activated
0011 IVINx limit IVINx limit Fast charge current
Low = 100 mA N/A Low = ICHG[4:0]
High= 500 mA High = IVINx limit 1500 mA High = ICHG[4:0] ÷ 2
0100 IVINx limit IVINx limit LDO
Low = 100 mA N/A Low = LDO active
High= 500 mA High = IVIN limit 1500 mA High = LDO disabled
0101 IVINx limit IVINx limit Charging
Low = 100 mA N/A Low = charging disabled
High= 500 mA High = IVINx limit 1500 mA High = charging enabled
0110 IVINx limit Recharge Charging
Low = 100 mA N/A Low = charging disabled
High= 500 mA High = disable recharge High = charging enabled
0111 Charging Disable IC1 Recharge
Low = charging disabled Low = not activated N/A
High = charging enabled High = activated High = disable recharge
1000 IVINx limit IVINx limit Interrupt output
Low = 100 mA N/A N/A
High= 500 mA High = IVINx limit 1500 mA N/A
1001 IVINx limit Charging Interrupt output
Low = 100 mA Low = charging disabled N/A
High= 500 mA High = charging enabled N/A
1010 IVINx limit Disable IC1 Interrupt output
Low = 100 mA Low = not activated N/A
High= 500 mA High = activated N/A
1011 IVINx limit Recharge Interrupt output
Low = 100 mA N/A N/A
High= 500 mA High = disable recharge N/A
1100 IVINx limit Fast charge current Interrupt output
Low = 100 mA Low = ICHG N/A
High= 500 mA High = ICHG[4:0] ÷ 2 N/A
1101 IVINx limit LDO Interrupt output
Low = 100 mA Low = LDO active N/A
High= 500 mA High = LDO disabled N/A
1110 IVINx limit Charging Interrupt output
N/A Low = charging disabled N/A
High = IVINx limit 1500 mA High = charging enabled N/A
1111 Disable IC1 Charging Interrupt output
Low = not activated Low = charging disabled N/A
High = activated High = charging enabled N/A
Data Sheet ADP5062
PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS
4.10 0.30
4.00 SQ 0.25
PIN 1 3.90 0.18
INDICATOR PIN 1
16 20 INDICATOR
0.50 15 1
BSC
EXPOSED 2.75
PAD
2.60 SQ
2.35
11 5
10 6
0.50 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.30
0.80 FOR PROPER CONNECTION OF
0.75 THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70 FUNCTION DESCRIPTIONS
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING 0.08
PLANE 0.20 REF
020509-B
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 42. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range (Junction) Package Description Package Option
ADP5062ACPZ-1-R7 –40°C to +125°C 20-Lead LFCSP_WQ CP-20-8
ADP5062ACPZ-2-R7 –40°C to +125°C 20-Lead LFCSP_WQ CP-20-8
ADP5062CP-EVALZ ADP5062 Evaluation Board
1
Z = RoHS Compliant Part.
2
For additional factory-programmable options, contact an Analog Devices local sales or distribution representative.
ADP5062 Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D10806-0-10/13(B)

Linear Li-Ion Battery Charger With Power Path and USB Compatibility in LFCSP

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TYPICAL APPLICATION CIRCUIT

Rev. B Document Feedback

COMPARABLE PARTS DESIGN RESOURCES

RECOMMENDED INPUT AND OUTPUT CAPACITANCES

I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS

tHIGH tSU, STA tSU, STO

Figure 2. I2C Timing Diagram

Table 5. Thermal Resistance

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

SYSTEM VOLTAGE (V)

CHARGE CURRENT (mA)

700 LIMIT = 900mA 500

2.7 3.2 3.7 4.2 2.3 2.8 3.3 3.8 4.3

ISOLATION FET RESISTANCE (mΩ)

4.0 4.4 0.7

BATTERY VOLTAGE (A)

CHARGE CURRENT (A)

0.5 3.2 0.1

SYSTEM VOLTAGE ACCURACY (%)

VTRM VOLTAGE ACCURACY (%)

INPUT CURRENT LIMIT (A)

–40 –25 –10 5 20 35 50 65 80 95 110 125

Figure 21. VINx Overvoltage Threshold vs. Ambient Temperature

Table 8. Operation Mode Controls

VIN1 HIGH VOLTAGE ISO_S1

Figure 29. Block Diagram

Table 10. Input Current Compatibility with Standard USB Limits

VBATL LOGIC VBATH LOGIC

SINK PHASE SOURCE PHASE TRICKLE CHARGE

tBAT_OK tBAT_OK tBAT_SHR

Table 16. JEITA2 Specifications

YES ENABLE NO ENABLE

YES LDO MODE

LOW YES VBAT_SNS NO

Figure 32. Simplified Battery and VINx Connect Flowchart

VBAT_SNS NO NO VIN_ILIM = HIGH

TIMER FAULT YES

YES1 TIMER FAULT OR

NO CHARGE YES NO CV MODE

Figure 33. Simplified Charging Mode Flowchart

0 = WRITE MASTER STOP

CHIP ADDRESS SUBADDR ESS CHIP ADDRESS ADP5062 SEND

Figure 36. I2C Single Register Read Sequence

Figure 37. I2C Multiple Register Read Sequence

Table 17. I2C Register Map

Table 18. Manufacturer and Model ID, Register Address 0x00

Table 19. Silicon Revision, Register Address 0x01

Table 20. VINx Pin Settings, Register Address 0x02

Table 23. Voltage Thresholds, Register Address 0x05

Table 24. Timer Settings, Register Address 0x06

Table 25. Functional Settings 1, Register Address 0x07

Table 26. Functional Settings 2, Register Address 0x08