The 8086 is an enhanced 16-bit microprocessor developed by Intel in 1976. It has a 16-bit data bus and 20 address lines, allowing it to access up to 1MB of memory. It features a powerful instruction set, pipelining, and supports two operating modes. The 8086 architecture separates processing into an Execution Unit and Bus Interface Unit. It has 14 registers organized into general purpose, pointer/index, segment, and flag registers.
The 8086 is an enhanced 16-bit microprocessor developed by Intel in 1976. It has a 16-bit data bus and 20 address lines, allowing it to access up to 1MB of memory. It features a powerful instruction set, pipelining, and supports two operating modes. The 8086 architecture separates processing into an Execution Unit and Bus Interface Unit. It has 14 registers organized into general purpose, pointer/index, segment, and flag registers.
The 8086 is an enhanced 16-bit microprocessor developed by Intel in 1976. It has a 16-bit data bus and 20 address lines, allowing it to access up to 1MB of memory. It features a powerful instruction set, pipelining, and supports two operating modes. The 8086 architecture separates processing into an Execution Unit and Bus Interface Unit. It has 14 registers organized into general purpose, pointer/index, segment, and flag registers.
The 8086 is an enhanced 16-bit microprocessor developed by Intel in 1976. It has a 16-bit data bus and 20 address lines, allowing it to access up to 1MB of memory. It features a powerful instruction set, pipelining, and supports two operating modes. The 8086 architecture separates processing into an Execution Unit and Bus Interface Unit. It has 14 registers organized into general purpose, pointer/index, segment, and flag registers.
Microprocessor LEC. 3: 8086 INTEL MICROPROCESSOR OMAR ZYAD Outlines Introduction Feature of 8086 8085 vs. 8086 8086 Architecture Register Organization INTRODUCTION 8086 is an enhanced version of 8085 that has been developed by Intel in 1976. 16 bit Microprocessor. 20 address lines >> So it can access up to 1 MB of memory. It has a powerful instruction set and it is capable to providing multiplication and division operations directly. Feature of 8086 It is 16 bit processor: ◦ 16 bit ALU ◦ 16 bit registers ◦ internal data bus and 16 bit external data bus. ◦ It make s faster processing.
It has 256 vectored interrupts.
It uses a memory banking system. ◦ It means entire data is not stored sequentially in a single memory of 1 MB but memory is divided into two banks of 512KB. Feature of 8086 It supports two modes of operation: ◦ First is maximum mode and Second is minimum mode. ◦ Minimum mode is applicable for system that have a single processor and maximum mode is used for the multiprocessor system.
Pipelining: 8086 uses two stage of pipelining. First is Fetch Stage and the second is Execute Stage. It has three version based on the frequency of operation: ◦ 8086 -> 5MHz ◦ 8086-2 ->8MHz ◦ 8086-1 ->10 MHz 8085 vs. 8086 8085 8086
Data Bus 8 bit 16 bit
Address Bus 16 bit 20 bit
Memory 64 KB 1 MB
Instruction Without instruction queue. With instruction queue.
Pipelining Doesn't support Support
I/O 256 64 K 8086 Architecture 8086 Microprocessor is divided into two functional units: ◦ EU (Execution Unit) ◦ BIU (Bus Interface Unit). 8086 Architecture The BIU handles all transactions of data and addresses on the buses for EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. 8086 Architecture Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. EXECUTION UNIT (EU) Decodes instructions fetched by the BIU Generate control signals, Executes instructions.
The main parts are:
◦ Control Circuitry ◦ Instruction decoder ◦ ALU BUS INTERFACE UNIT (BIU) • 6-byte Instruction Queue (Q) • The Segment Registers (CS, DS, ES, SS). • The Instruction Pointer (IP). • The Address Summing block (Σ) REGISTER ORGANISATION The 14 registers of 8086 microprocessor are categorized into four groups. ◦ General purpose data registers ◦ Pointer & Index registers ◦ Segment registers ◦ and Flag register. REGISTER ORGANISATION REGISTER ORGANISATION General purpose registers: ◦ There are four 16-bit 4 general purpose registers namely (AH, AL);(BH,BL); (CH,CL); (and DH,DL) which are part of Execution unit. ◦ These registers can be used individually for storing 16-bit data temporarily . ◦ The AL register is also called the accumulator. ◦ The pairs of registers can be used together to store 16-bit data words. ◦ It is always advantageous to store the data in these registers because the data can be accessed much more easily as these registers are already in the execution unit. ◦ Here L indicates the lower byte and H indicates the higher byte. X indicates the extended register. ◦ The general purpose data registers are used for data manipulations.. REGISTER ORGANISATION Pointer Registers : ◦ They are Stack Pointer register and Base Pointer register. ◦ The pointer registers contain the offset within a particular segment. ◦ The BP & SP registers holds the offsets within the data and stack segments respectively. REGISTER ORGANISATION Index Registers : ◦ The Index registers are used as general purpose registers as well as for holding the offset in case of indexed based and relative indexed addressing modes ◦ The source Index register is generally used to store the offset of source data in data segment ◦ While the Destination Index register used to store the offset of destination in data or extra segment. ◦ These index registers are specifically used in string manipulations. REGISTER ORGANISATION Segment Registers ◦ There are four 16-bit segment registers namely code segment register(CS),Stack segment register(SS),Data segment register(DS) and Extra segment register(ES). ◦ The code segment register is used for addressing the 64kB memory location in the code segment of the memory ,where the code of the executable program is stored. ◦ The DS register points to the data segment of the 64kB memory where the data is stored. ◦ The Extra segment register also refers to essentially another data segment of the memory space. ◦ The SS register is useful for addressing stack segment of memory. REGISTER ORGANISATION Instruction Pointer Register: ◦ It is a 16-bit register which always points to the next instruction to be executed within the currently executing code segment. ◦ So, this register contains the 16-bit offset address pointing to the next instruction code within the 64KB of the code segment area. ◦ Its content is automatically incremented as the execution of the next instruction takes place. . REGISTER ORGANISATION Flag Register: ◦ This register is also called status register. ◦ It is a 16 bit register which contains six status flags and three control flags. So, only nine bits of the 16 bit register are defined and the remaining seven bits are undefined. ◦ Normally this status flag bits indicate the status of the ALU after the arithmetic or logical operations. ◦ The Flag register contains Carry flag, Parity flag, Auxiliary flag Zero flag, Sign flag ,Trap flag, Interrupt flag, Direction flag and overflow flag as shown in the diagram. The CF,PF,AF,ZF,SF,OF are the status flags and the TF,IF and CF are the control flags. REGISTER ORGANISATION Flag Register: ◦ CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction. ◦ PF - Parity Flag : This flag is set to 1, if the lower byte of the result contains even number of 1’s else (for odd number of 1s ) set to zero. ◦ AF- Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during addition, or borrow for the lowest nibble. ◦ ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous instruction is zero ◦ SF- Sign Flag : This flag is set, when the result of any computation is negative ◦ TF - Tarp Flag: If this flag is set, the processor enters the single step execution mode. REGISTER ORGANISATION Flag Register: ◦ IF- Interrupt Flag: If this flag is set, the maskable interrupt INTR of 8086 is enabled and if it is zero ,the interrupt is disabled. It can be set by using the STI instruction and can be cleared by executing CLI instruction. ◦ DF- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the string is processed beginning from the lowest address to the highest address, i.e., auto incrementing mode. Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto incrementing mode. ◦ OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, then the overflow will be set.
