Subhash Patel
Personal Data
Address A-2, Aarti So.
Payalnagar Road, Naroda, 382330-Ahmedabad
Email subhashpatel9@googlemail.com, subhash.bvm@gmail.com
Phone +91-9408590009
Education
February 2010 Master of Science in Microelectronics & Microsystems
Hamburg University of Technology (TUHH), Hamburg, Germany
Grade 1.4 (Very good) | Major: Microelectronics
June 2006 Bachelor of Engineering Electronics
Sardar Patel University, Vallabhvidyanagar, India
Result 81.79% (First class with distinction)
Work Experience
Since September-2010 Assistant Professor in Indus College of Engineering, Ahmedabad
April-2009 to Internship and Thesis at IPGEN Rechte GmbH, Bochum, Germany
February 2010 Field :- Analog and Mixed signal integrated circuit design
Designed IP of CDR-PLL and Synthesizer PLL (Design, simulation, layout & verification)
Optimized area of Resistive DAC
Designed Analog multiplexer
July-2006 to Engineer at Bombardier Transportation, India
July-2007 Field :- Electronics testing and design
Developed Train control and Management System for Indian Railways Locomotive
Involved in testing of traction converter control electronics
Expertise
• Experience in Verilog RTL coding, synthesis and simulation
• Experience in CMOS analog and mixed signal circuit design (ASIC) with Cadence DFII and Mentor
Graphics IC design environment
• Knowledge of Digital signal processing (DSP), semiconductor device physics, USB protocol
Master of Science Dissertation (Thesis)
February 2010 A Test-bench driven, automated design approach for high performance PLL for
serial communication application
Advisors : Prof. Dr-Ing W Krautschneider (Hamburg University of Technology, Germany)
Dipl-Ing. Reimund Wittmann (IPGEN Rechte GmbH, Bochum, Germany)
Designed and implemented CDR-PLL and Synthesizer PLL in 180nm CMOS Technology
Developed and verified time efficient automated design approach for both PLLs
Developed configurable IP of both PLLs
Designed technology independent and configurable layouts of PLL
EDA tool used : Mentor Graphics, Eldo simulator, 1STONE design management tool, MATLAB
Computer Skills
Programming C, C++ ,Verilog, VHDL, AMPLE, MATLAB-script, JAVA(learning)
Operating systems Windows XP & Vista, Linux (Ubuntu and Mandriva)
EDA tools Cadence IC DFII, Mentor Graphics, MATLAB, Electric, Hspice, ELDO,
Xilinx ISE
Academic Projects
January 2009 Digital control for DC-offset suppression with D/A Converter in biomedical ASIC
Advisor : Dr-Ing D. Schröder (Hamburg University of Technology, Germany)
System level design in MATLAB and RTL implementation using Verilog-HDL coding
Synthesis and verification of design using Cadence IC DFII, Technology CMOS 350nm
Summer 2009 RTL design using Verilog-HDL of Currency coveter ASIC
Summer 2009 Design and simulation of acceleration sensor.
Summer 2009 Fabrication of Integrated Optical Fiber and diodes
Winter 2008 Design, simulation and implementation of Two stage Op-amp in 350nm CMOS technology
winter 2005 Sun-tracker
Scholarships, Certificates and Awards
April 2008 Scholarship for the students with an excellent academic performance at TUHH
December 2006 Gold medal from Sardar Patel university and BVM Engineering college
for securing highest rank at end of Bachelor study in Electronics branch
2002-2006 5 Gold/Silver Medals for excellent academic performance during Bachelor study
2006 GATE Examination : 88 percentile
Languages
Gujarati Mother tongue
English Fluent
Hindi Fluent
German Basic Knowledge, Learning intermediate German
Subhash Patel
January 11, 2011
