PAMANTASAN NG CABUYAO

Katapatan Subd., Banay-banay, Cabuyao, Laguna

COLLEGE OF ENGINEERING
DEPARTMENT OF COMPUTER ENGINEERING

Course Code : CPE 112

Course Title : Digital Signal Processing
Number of Units : 3 hours lecture and 3 hours Lab /week
Revision No. : 1
Date Last Revised : July 3, 2015

Description : The course includes the fundamental concepts and practical applications of Digital Signal Processing

General Objectives :
1. Understand the fundamental concept of Digital Signal Processing
2. Learn the Practical application of DSP systems
3. Have a broad foundation on basic DSP theory to prepare the students in their specialization studies

PRELIMINARY PERIOD
Time Teaching-Learning
Specific Objectives Topic Tools/Aids Evaluative Measures
Table Strategies
1st week Introduction of DSP
To describes a typical design cycle in Digital Systems
the implementation of a signal - Principle Recitation
2nd week processing - Multi-core systems Homewok
Application. Black Board
Seatwork
Components of a Digital Design Lecture Presentation
To examine the scope of the subject of Quizzes
Process Multimedia
digital design, let us consider an Case Study
- Design
embedded signal processing system of Laboratory
- Verification
medium complexity - Implementation

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3rd week Laboratory
To understand the design as
Black Board Homewok
Synthesized for better timing means Synchronous Digital Hardware
Lecture Presentation Seatwork
shorter critical paths, the design may Systems
Multimedia Quizzes
result in a larger area.
Case Study
4th week To understand the design of a few boxes
and take major design decisions like
algorithm partitioning and target Recitation
DESIGN Strategies
th
5 week technology selection. Black Board Homewok
- Algorithms
To discover partitioning of the Lecture Presentation Laboratory
Using Hardware Description
algorithm into hardware (HW) and Multimedia Quizzes
Language
6th week software (SW), and its subsequent Case Study
mapping on different platforms,
algorithm design and coding techniques

MIDTERM
Time Teaching-Learning
Specific Objectives Topic Tools/Aids Evaluative Measures
Table Strategies
1st week To understand different design System Design Flow
implementations in DSP LOGIC Synthesis
2nd week To discover design constraints and the Four Levels of Abstraction Recitation
target technology in the form of a - Modules Homewok
3rd week standard cell library. - Design Partitioning Lecture Black Board Seatwork
To understand the different levels of - Hierarchical Design Presentation Quizzes
design which can be coded in a mix of - Logic Values Case Study
levels moving from the lowest - Data Types Laboratory
abstraction of switch level to the highly - Variable Declaration
abstract model of behavioral level - Constants
4th week
To understand the limited scope for VERIFICATION of Hardware Laboratory
verification in Verilog and to add more - Introduction to Verification Recitation
Black Board
5th week advanced features for HW design, the - Testing Approaches Lecture Homewok
Presentation
EDA vendors constituted a consortium - Levels of testing in the Seatwork
To experiment and understand the development cycle Quizzes

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6th week

different methods for generating test Case Study

cases. The particular choice depends on Methods in generating class
the size of the design and the level at Transaction Level Modelling
FINALS
Time Teaching-Learning
Specific Objectives Topic Tools/Aids Evaluative Measures
Table Strategies
1st week Unfolding and Folding of
To know the sampling clock is specific Architectures Recitation
2nd week to an application and is derived from the - Introduction Homewok
NY Quist sampling criteria or band pass - Unfolding Seatwork
sampling constraint - Sampling Rate Considerations Quizzes
- NY Quist Sampling Theorem Black Board Case Study
To discover the effects created by the Lecture
and Design Options Presentation Laboratory
sampling clocks specific to an - Software-defined Radio
application and is based on NY Quist Architecture and Band-pass
sampling criteria or band pass sampling Sampling
techniques - A/D Converter Bandwidth and
Band-pass Sampling
3rd week To grasp the concept of technique Unfolding Techniques
widely used by compilers for reducing - Loop Unrolling
4th week the loop overhead in code written in - Unfolding Transformation
high level languages - Loop Unrolling for Mapping SW
Recitation
5th week to HW
Homewok
To understand that the architect should - Unfolding to Maximize Use of a
Black Board Seatwork
explore the design space by unrolling Compression Tree Lecture
Presentation Quizzes
different loops in the nesting and also - Unfolding for Effective Use of
Case Study
try merging a few FPGA Resources
6th week Laboratory
Nested loops together to find an - Unfolding and Retiming in
effective design. Feedback Designs
Project Integration with CpE
111( Control System )

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Course Requirements

Lecture: Laboratory:
I. Term Examination - 50% I. Oral Examinations - 60%
II. Quizzes/Exercises - 20% II. Quizzes/Exercises - 40%
III. Class Participation - 10% _____
IV. Attendance - 10% 100%
V. Others - 10%
_____
100% Term Grade = Lecture Grade (60%) + Laboratory Grade (40%)

Grading System

Midterm Standing = Prelim Grade + Midterm Grade

(50%) (50%)

Final Grade = Prelim Grade + Midterm Grade + Final Grade

(30%) (30%) (40%)

Classroom Policies

 Tardiness will not be tolerated. Being late for 15 minutes in a 1 ½ hour class or 30 minutes for a 3 hour class is considered absent.
 Students who are causing disruptions during class hours will be punished as defined in the student manual.
 Special exams will only be given to students who were able to secure an excuse slip from the OSA as defined in the student manual.

References

Digital Signal Processing , Monson H. Hayes , McGraw Hill , 1999

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 Digital Signal Processing ,SanjitMitra , McGraw Hill Companies , 2006
Understanding Digital Signal Processing, Richard Lyons , Prentice Hall , 2010

Required Readings

Due to the Complexity of the subject matter Hand-outs will be given to the student to support their study…
Project Implementation will play a huge part of their LABORATORY GRADE as CASE STUDY.

Consultation Schedule

Monday 7am – 10am / ECE LAB

Prepared by: Reviewed & Checked by:

Engr. Oliver A. Medina Engr. Anna-liza M. Fabello

Instructor / CpE Department Instructor / CpE Department Chair

Recommending Approval

Engr. Mary Grace P. Beaño Prof. Marilou R. Tayao

Dean, College of Engineering VP for Academic Affairs

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