See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/317555750

WIP. Open-source standard cell characterization process flow on 45 nm

(FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm

Conference Paper · May 2017

DOI: 10.1109/MSE.2017.7945072

CITATION READS

1 353

3 authors:

Rabin Thapa Samira Ataei

Oklahoma State University - Stillwater Yale University
1 PUBLICATION   1 CITATION    19 PUBLICATIONS   64 CITATIONS   

SEE PROFILE SEE PROFILE

James Stine
Oklahoma State University - Stillwater
76 PUBLICATIONS   1,170 CITATIONS   

SEE PROFILE

Some of the authors of this publication are also working on these related projects:

OpenRAM : An Open-Source Memory Compiler View project

AMC: An Asynchronous Memory Compiler View project

All content following this page was uploaded by Samira Ataei on 24 October 2017.

The user has requested enhancement of the downloaded file.

 WIP: Open-Source Standard Cell Characterization
Process Flow on 45 nm (FreePDK45), 0.18 µm,
0.25 µm, 0.35 µm and 0.5 µm
Rabin Thapa and Samira Ataei and James E. Stine
Electrical and Computer Engineering Department, VLSI Computer Architecture Research Group,
Oklahoma State University, Stillwater, OK 74078
{rabin.thapa, ataei, james.stine}@okstate.edu

Abstract—This paper describes the design flow of the standard new cells for their flows 1 . The tools used for characterization
cell characterization on five different technologies and integration for this proposed work is Virtuoso Liberate from Cadence
of its results with other VLSI tools processes that can be Design Systems (CDS). To the best of our knowledge, this
duplicated and implemented for the research and education in
the academia. In this proposed work, one design flow is on non- is the only open source standard cell characterization process
fabricable technology of open-source false-technology FreePDK45 flows available to the public that works on this tool.
of 45 nm CMOS technology [1]. The other design flows are
in the fabricable technology in 0.18 µm, 0.25 µm, 0.35 µm II. T HE P ROCESS F LOW
and 0.5 µm. The design flow are automated to simplify the
students with intricacy of the tools. This design flows in this A. Characterization Flow
work are automated for the tool, Virtuoso Liberate from
Cadence Design Systems and students can easily adopt it as part The standard cell characterization flow begins with three
of the VLSI design class curriculum. This characterization flow basic input files. First, a netlist layout of the cell in SPICE
precisely models the electrical characteristics of the cell that has format is required. The layout tool, magic was used to generate
been subjected to different input variables as explained below. the files in this work. Second, information on the device
The characterized models are of high demand in other design
tools used in between RTL to GDSII process flow. technology that is dependent on the specific technology and
the process utilized is required. Finally, a file is required that
consists of information on the operational temperature and
voltage used on the cells along with the two dimensional
I. I NTRODUCTION table with input slew on one axis and output capacitive
load on another. For this work, open-source non-fabricable
FreePKD45 of 45 nm CMOS technology [1] and the fabricable
Many in the academia find it difficult to characterize stan- standard cells in 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm are
dard cells, mostly because there are very few open source included in this characterization flow. Each of these libraries
standard-cells libraries available to begin with. Many of the are characterized for at least three process corners: typical,
IC Companies have their own standard-cell libraries which best and worst cases.
they use for their own internal purposes. The use of these li- Upon characterization of the cells, detailed views on the
braries outside the companies are restricted due the proprietary electrical behavior of each of the cells are generated. These
information contained within. So, an open source standard- views of the cell differ when exposed to different processes
cell library on various technologies, which would be very and environmental variations, the variation of the input slew
helpful for the research and education in the academia, is the and the various output load capacitance. The database is
need of the time. With this objective in mind, a previously created by the tool and stores all these informations and
introduced standard-cell library in 0.5 µm technology [2], [3] generates the characterization reports. The characterization
was introduced. Couple of years later, in 2007, the same author report models the electrical behavior of the standard cell; it
along with a joint team from Oklahoma State University and consists of timing, power and signal integrity (noise) results
North Carolina State University jointly published the open based on variation of input parameters. One of the generated
source FreePDK 45nm Standard cells [1]. Each library for files is an electric view of Non-Linear Delay model (NLDM).
each technologies consists of multiple cells of different drive The NLDM with timing/power information are further used as
strength. This proposed work has borrowed the standard cells
for characterization from these works. The main purpose here 1 The original FreePDK45 standard-cell library from Oklahoma State Uni-

is to provide an updated mechanism for characterization for versity had some issues with its characterization despite detailed scripts
available within the library. Although researchers could have realized these
these standard-cell libraries. Moreover, repeatable characteri- errors and rerun the characterization, this work fixes some of those errors and
zation scripts are given to help researchers redo or characterize updates the scripts with the new characterization tool.
 TABLE I TABLE II
I NPUT FILES USED FOR THE CHARACTERIZATION S TANDARD CELLS LIST IN CHARACTERIZATION FLOW.

Directory or File Contains Information on Cells

MODELS Device technology INVX1, INVX2, INVX4, INVX8
NETLIST Transistor netlist in SPICE format OR2X1, OR2X2, NOR2X1,NOR3X1,
TEMPLATE Slew, output load, cell names AND2X1, AND2X1, AND2X2, NAND2X1, NAND3X1,
.tcl Various files with tcl commands XNOR2X1, XOR2X1,
BUFX2, BUFX4, CLKBUF1, CLKBUF2, CLKBUF3
FAX1, HAX1,
OAI21X1, OAI22X1, AOI21X1, AOI22X1,
a baseline for other delay models such as Composite Current
DFFNEGSQ, DFFPOSSQ, DFFSRSQ, LATCHSQ
Source, (CCS) and Effective Current Source (ECS) models. Xn indicates drive strength, where n=1, 2, 3, 4
Although standard-cell libraries are useful, they are difficult SQ indicates sequential circuit
to integrate into design flows because most of the electronic
design automation softwares are complex. However, the in-
nate educational value to have a design flow along with • Within the NETLIST sub folder, netlists contains the
standard-cell libraries and memories is paramount to educat- layout netlist in SPICE format.
ing future engineers. Therefore, the process designed here • Within the TEMPLATE sub folder, the template OSU.tcl
would be incomplete without any design flow integration. The file contains all the input signal slew and output capacitive
methodology is to integrate both the characterized standard- loads, the lower and upper slew values, the name of the
cell libraries, along with the work from OpenRAM [4], to cell used.
create a complete element that can be manipulated by different • Within the char.tcl file, all the environmental variables
Universities and research programs. OpenRAM is an open- like voltage, temperature are included. Some Tcl scripts
source, portable and flexible memory compiler that generates provided by the CDS have been modified and reused to
different size and configuration of SRAMs for FreePDK45 [1] create the necessary results.
and Scalable CMOS [5] technologies. Figure 1 shows a sample • Next, the CCS and/or ECSM results are created. The file
design that has been placed and routed using the library. The rechar.tcl has been modified to accomodate this. CCS and
design flow and all scripts are available for free academic use ECSM related files are placed in separate folders to create
at http://vlsiarch.ecen.okstate.edu. separate results.
• A Makefile has been created to hide the intricacy of
III. C HARACTERIZATION F LOW WITH AN EXAMPLE calling different commands and making it easy to run the
The input files are summarized in Table I and list of cells complete process.
used are illustrated in Table II. Below, steps are introduced for
creating standard cell characterization of an inverter in 45nm IV. C ONCLUSIONS
technology. These steps can be duplicated for any cells in any This paper introduces the design flow of the characterization
technology by using proper related files. The base files can be and integration with other VLSI tools for academia. The first
downloaded from http://vlsiarch.ecen.okstate.edu. part is the characterization flow for non-fabricable FreePDK45
• Within the MODELS sub folder, the file with .sp ex- standard cells using the Virtuoso Liberate tool from Cadence.
tension has the correct device technology file with the The fabricable standard cells from other technologies (0.5 µm,
process corners used for both pMOS and nMOS CMOS 0.35 µm, 0.25 µm and 0.18 µm) are also included in this char-
transistors. acterization flow. The main motivation behind this open-source
standard cells characterization process flow and integration is
to promote research and education in academia.
R EFERENCES
[1] J. Stine, I. Castellanos, M. Wood, J. Henson, F. Love, W. Davis,
P. Franzon, M. Bucher, S. Basavarajaiah, J. Oh, and R. Jenkal, “FreePDK:
An open-source variation-aware design kit,” in International Conference
on Microelectronic Systems Education, pp. 173–174, June 2007.
[2] J. Grad and J. E. Stine, “A standard cell library for student projects,”
2003.
[3] J. Grad, J. E. Stine, and D. D. Neiman, “Real world SoC experience for
the classroom,” in 2005 IEEE International Conference on Microelec-
tronic Systems Education (MSE’05), pp. 49–50, June 2005.
[4] M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, and M. Sarwar,
“Openram: An open-source memory compiler,” in 2016 IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), pp. 1–
6, Nov 2016.
[5] MOSIS, “MOSIS scalable CMOS (SCMOS) design rules.” https://www.
mosis.com/files/scmos/scmos.pdf, 2017.
Fig. 1. FreePDK45 Placement and Routing.

View publication stats