Name:_________________ Roll No:__________
Lab: Computer Architecture (8th Term)
LAB # 4
Strengthening of concepts of behavioural modelling with deep
familiarization with FPGA board.
Note : All modules are attached at the end of manual.
Procedure:
1. Launch the Xilinx ISE 7.1 software as follows:
Start >> Programs >> Xilinx ISE 7.1 >> Project Navigator
2. Start a new project as follows:
File >> New Project
3. Give the project name as: Counter_disp
4. Select the project location as follows:
C:\CA05\2005_E_205
5. Select the top level module type as : HDL
6. Click Next.
7. In the next window of ‘Select Device and Design Flow for the Project’:
Select the simulator as : ISE simulator
In the Device Family option,
Select Spartan3
In the Device option
Select xc3s200
In the Package option
Select ft256
In the Speed Grade option
Select -5
In the Top Level Module Type option
Select HDL
In the Synthesis Tool option
Select XST(VHDL/Verilog)
In the Simulator option
Select ISE Simulator
In the Generated Simulation Language option
Select Verilog
Then, select Next.
8. In the next window of ‘Create a new source’:
Simply click Next. We shall not use this option for the time
being.
9. In the next window of ‘Add Existing Sources’:
Simply click Next. We shall not use this option for the time
being.
10. In the next window, click Finish.
11. Just right click in the “sources in project” space and select “add copy
of Source”.
And copy all the files present in Lab4 folder present in desktop.
Synthesis the code and see its behavioural simulation on test bench.
Implement the counter on FPGA using the following instructions.
1) See the attached file for pin configuration of seven segment display.
2) Assign the pin package in user constraints according to the above
configuration.
3) Assign clk (input) to T9 pin in the package.
After saving the pin package assignment. Just implement the design and generate
programming file and see the output.
Note : You will be graded only if you are able to run the 16 bit HEX counter on the
FPGA Board.
Assignment:
a) Implement a 16 bit decimal counter.
Code
// Final Code
module final (clk, seven,out);
input clk;
output [6:0] seven;
output [3:0] out;
wire [3:0] temp;
wire [1:0] sel;
wire clk_2;
clkdiv2 f1 (clk, clk_2);
cldiv f2 (clk,sel);
counter_mux f3 (clk_2,temp,sel);
seven f4 (temp,sel,seven,out);
endmodule
// clkdiv
module cldiv(clk, out);
input clk;
output [1:0]out;
reg [30:0]temp = 31'b0000000000000000000000000000000;
always @(posedge clk)
begin
temp <= temp +1;
end
assign out = {temp[18],temp[17]};
endmodule
// clkdiv2
module clkdiv2(clk, out);
input clk;
output out;
reg [24:0] temp = 25'b0000000000000000000000000;
always @ (posedge clk)
begin
temp <= temp + 1;
end
assign out = temp[22];
endmodule
// counter_mux
module counter_mux(clk, out, sel);
input clk;
output [3:0] out;
input [1:0] sel;
wire [15:0] temp;
counter_1 f1 (clk , temp);
mux_1 f2 (temp[3:0],temp[7:4],temp[11:8],temp[15:12],out,sel);
endmodule
// counter
module counter_1(clk,b);
input clk;
output [15:0] b;
reg [15:0] c = 16'b0000000000000000;
always @(posedge clk)
begin
c <= c +1'b1;
end
assign b = c;
endmodule
// 4bit 4X1 Mux
module mux_1(a, b, c, d, out, sel);
input [3:0] a, b, c, d;
output reg [3:0] out;
input [1:0] sel;
always @ (a or b or c or d or sel)
case (sel)
0: out <= a;
1: out <= b;
2: out <= c;
3: out <= d;
endcase
endmodule
//Seven segment display
module seven(sev, sel, out, toto);
input [3:0] sev ;
output reg [6:0] out;
input [1:0]sel;
output reg [3:0] toto;
always @ (sel)
begin
case(sel)
0: toto = 4'b1110;
1: toto = 4'b1101;
2: toto = 4'b1011;
3: toto = 4'b0111;
endcase
end
always @ (sev)
begin
case (sev)
4'b0000: out = 7'b0000001;
4'b0001: out = 7'b1001111;
4'b0010: out = 7'b0010010;
4'b0011: out = 7'b0000110;
4'b0100: out = 7'b1001100;
4'b0101: out = 7'b0100100;
4'b0110: out = 7'b0100000;
4'b0111: out = 7'b0001111;
4'b1000: out = 7'b0000000;
4'b1001: out = 7'b0000100;
4'b1010: out = 7'b0001000;
4'b1011: out = 7'b1100000;
4'b1100: out = 7'b0110001;
4'b1101: out = 7'b1000010;
4'b1110: out = 7'b0110000;
4'b1111: out = 7'b0111000;
endcase
end
endmodule
Modules Definitions:
Final
final : A 16 bit Hex counter displays the counting on 4 digit 7 segment display.
cldiv
Clk clkdiv2 counter_mux seven
clkdiv2 : Divides the internal clock of 50 M Hz so that digits can be seen on
seven segment display.
cldiv : It also divides the clock in a such a way so that multiplexing of 4 digits
can be seen.
Counter_mux : Includes a 16 bit HEX counter and a 4 bit 4X1 Mux to
multiplex individual 4 bits on the 4 digits.
Seven : Just a HEX to seven segment converter.
Counter_1 4 bit 4X1 Mux
