4Gb: x4, x8, x16 DDR3L SDRAM

Description

1.35V DDR3L SDRAM

MT41K1G4 – 128 Meg x 4 x 8 banks
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks

Description • TC of 0°C to +95°C

– 64ms, 8192-cycle refresh at 0°C to +85°C
DDR3L SDRAM (1.35V) is a low voltage version of the – 32ms at +85°C to +95°C
DDR3 SDRAM (1.5V). • Self refresh temperature (SRT)
• Automatic self refresh (ASR)
Features
• Write leveling
• VDD = V DDQ = 1.35V (1.283–1.45V)
• Multipurpose register
• Backward compatible to V DD = V DDQ = 1.5V ±0.075V
• Output driver calibration
– Supports DDR3L devices to be backward com-
patible in 1.5V applications Options Marking
• Differential bidirectional data strobe • Configuration
• 8n-bit prefetch architecture – 1 Gig x 4 1G4
• Differential clock inputs (CK, CK#) – 512 Meg x 8 512M8
• 8 internal banks – 256 Meg x 16 256M16
• Nominal and dynamic on-die termination (ODT) • FBGA package (Pb-free) – x4, x8
for data, strobe, and mask signals – 78-ball (10.5mm x 12mm) Rev. D RA
• Programmable CAS (READ) latency (CL) – 78-ball (9mm x 10.5mm) Rev. E, J RH
• Programmable posted CAS additive latency (AL) • FBGA package (Pb-free) – x16
• Programmable CAS (WRITE) latency (CWL) – 96-ball (10mm x 14mm) Rev. D RE
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 – 96-ball (9mm x 14mm) Rev. E HA
(via the mode register set [MRS]) • Timing – cycle time
• Selectable BC4 or BL8 on-the-fly (OTF) – 1.071ns @ CL = 13 (DDR3-1866) -107
• Self refresh mode – 1.25ns @ CL = 11 (DDR3-1600) -125
– 1.5ns @ CL = 9 (DDR3-1333) -15E
– 1.87ns @ CL = 7 (DDR3-1066) -187E
• Operating temperature
– Commercial (0°C ≤ T C ≤ +95°C) None
– Industrial (–40°C ≤ T C ≤ +95°C) IT
• Revision :D/:E/:J

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-1071, 2, 3 1866 13-13-13 13.91 13.91 13.91
-1251, 2 1600 11-11-11 13.75 13.75 13.75
-15E1 1333 9-9-9 13.5 13.5 13.5
-187E 1066 7-7-7 13.1 13.1 13.1

Notes: 1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-107).

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Products and specifications discussed herein are subject to change by Micron without notice.
 4Gb: x4, x8, x16 DDR3L SDRAM
Description

Table 2: Addressing

Parameter 1 Gig x 4 512 Meg x 8 256 Meg x 16

Configuration 128 Meg x 4 x 8 banks 64 Meg x 8 x 8 banks 32 Meg x 16 x 8 banks
Refresh count 8K 8K 8K
Row address 64K (A[15:0]) 64K (A[15:0]) 32K (A[14:0])
Bank address 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0])
Column address 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0])
Page size 1KB 1KB 2KB

Figure 1: DDR3L Part Numbers

Example Part Number: MT41K512M8RH-125:E

- :

MT41K Configuration Package Speed Revision

{
:D/:E/:J Revision

Configuration Temperatu re
1 Gig x 4 1G4 Commercial None
512 Meg x 8 512M8 Industrial temperature IT
256 Meg x 16 256M16
Speed Grade
Package Rev. Mark -107 tCK = 1.071ns, CL = 13
78-ball 10.5mm x 12mm FBGA D RA -125 tCK = 1.25ns, CL = 11
78-ball 9mm x 10.5mm FBGA E, J RH -15E tCK = 1.5ns, CL = 9
96-ball 10.0mm x 14mm FBGA D RE tCK
-187E = 1.87ns, CL = E
96-ball 9mm x 14mm FBGA E HA

Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions

Ball Assignments and Descriptions

Figure 2: 78-Ball FBGA – x4, x8 (Top View)

1 2 3 4 5 6 7 8 9

A
VSS VDD NC NF, NF/TDQS# VSS VDD

B
VSS VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ

C
VDDQ DQ2 DQS DQ1 DQ3 VSSQ

D
VSSQ NF, DQ6 DQS# VDD VSS VSSQ

E
VREFDQ VDDQ NF, DQ4 NF, DQ7 NF, DQ5 VDDQ

F
NC VSS RAS# CK VSS NC

G
ODT VDD CAS# CK# VDD CKE

H
NC CS# WE# A10/AP ZQ NC

J
VSS BA0 BA2 A15 VREFCA VSS

K
VDD A3 A0 A12/BC# BA1 VDD

L
VSS A5 A2 A1 A4 VSS

M
VDD A7 A9 A11 A6 VDD

N
VSS RESET# A13 A14 A8 VSS

Notes: 1. Ball descriptions listed in Table 3 (page 5) are listed as “x4, x8” if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).

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 4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions

Figure 3: 96-Ball FBGA – x16 (Top View)

1 2 3 4 5 6 7 8 9

A
VDDQ DQ13 DQ15 DQ12 VDDQ VSS

B
VSSQ VDD VSS UDQS# DQ14 VSSQ

C
VDDQ DQ11 DQ9 UDQS DQ10 VDDQ

D
VSSQ VDDQ UDM DQ8 VSSQ VDD

E
VSS VSSQ DQ0 LDM VSSQ VDDQ

F
VDDQ DQ2 LDQS DQ1 DQ3 VSSQ

G
VSSQ DQ6 LDQS# VDD VSS VSSQ

H
VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ

J
NC VSS RAS# CK VSS NC

K
ODT VDD CAS# CK# VDD CKE

L
NC CS# WE# A10/AP ZQ NC

M
VSS BA0 BA2 NC VREFCA VSS

N
VDD A3 A0 A12/BC# BA1 VDD

P
VSS A5 A2 A1 A4 VSS

R
VDD A7 A9 A11 A6 VDD

T
VSS RESET# A13 A14 A8 VSS

Note: 1. A slash defines a selectable function.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

[15:13], A12/BC#, Input Address inputs: Provide the row address for ACTIVATE commands, and the column
A11, A10/AP, A[9:0] address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in
the DDR3 SDRAM data sheet.
BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW)
internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/
disabled is dependent upon the DDR3 SDRAM configuration and operating mode.
Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle), or active power-down (row active in any bank). CKE is synchronous
for power-down entry and exit and for self refresh entry. CKE is asynchronous for
self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-
bled during SELF REFRESH. CKE is referenced to VREFCA.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
DM Input Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with the input data during a write access.
Although the DM ball is input-only, the DM loading is designed to match that of the
DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on
the x8.
ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is
ignored if disabled via the LOAD MODE command. ODT is referenced to REFCA.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re-
ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol Type Description

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are
referenced to REFDQ.
DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to VREFDQ.
DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write
data. Center-aligned to write data.
TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is
enabled, DM is disabled, and the TDQS and TDQS# balls provide termination
resistance.
VDD Supply Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VDDQ Supply DQ power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VREFCA Supply Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ Supply Reference voltage for data:REFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ Reference External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
NC – No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
NF – No function: When configured as a x4 device, these balls are NF. When configured
as a x8 device, these balls are defined as TDQS#, DQ[7:4].

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 4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

[14:13], A12/BC#, Input Address inputs: Provide the row address for ACTIVATE commands, and the column
A11, A10/AP, A[9:0] address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in
the DDR3 SDRAM data sheet.
BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-
pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for power-
down entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to VREFCA.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS# pro-
vides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is
designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to VREFCA.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.

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© 2011 Micron Technology, Inc. All rights reserved.
 4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions

Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)

Symbol Type Description

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re-
ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-
byte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
VDD Supply Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VDDQ Supply DQ power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VREFCA Supply Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ Reference External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
NC – No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).

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 4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions

Package Dimensions

Figure 4: 78-Ball FBGA – x4, x8 (RA)

0.155

Seating plane

A 0.12 A

1.8 CTR
Nonconductive
overmold

78X Ø0.45
Dimensions apply
Ball A1 ID Ball A1 ID
to solder balls post-
reflow on Ø0.35 SMD
ball pads. 9 8 7 3 2 1

A
B
C
D
E
F
12 ±0.1 G
H
9.6 CTR
J
K
L
M
0.8 TYP
N

0.8 TYP 1.1 ±0.1

6.4 CTR 0.25 MIN

10.5 ±0.1

Note: 1. All dimensions are in millimeters.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions

Figure 5: 78-Ball FBGA – x4, x8 (RH)

0.155

Seating plane

A 0.12 A
1.8 CTR
Nonconductive
78X Ø0.45 overmold
Dimensions apply
to solder balls post- Ball A1 ID Ball A1 ID
reflow on Ø0.35 SMD (covered by SR)
ball pads. 9 8 7 3 2 1
A
B
C
D
E
F
10.5 ±0.1
G
9.6 CTR H
J
K
L
M
N

0.8 TYP
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1

Note: 1. All dimensions are in millimeters.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions

Figure 6: 96-Ball FBGA – x16 (RE)

0.155

Seating plane

A 0.12 A
1.8 CTR
Nonconductive
overmold

96X Ø0.45
Dimensions apply
to solder balls Ball A1 ID Ball A1 ID
post-reflow on
Ø0.35 SMD ball pads
9 8 7 3 2 1

A
B
C
D
E
F
14 ±0.1 G
H
12 CTR J
K
L
M
N
P
R
0.8 TYP
T

0.8 TYP 1.1 ±0.1

6.4 CTR 0.25 MIN

10 ±0.1

Note: 1. All dimensions are in millimeters.

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© 2011 Micron Technology, Inc. All rights reserved.
 4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions

Figure 7: 96-Ball FBGA – x16 (HA)

0.155

Seating plane

1.8 CTR A 0.12 A

Nonconductive
overmold
96X Ø0.45
Dimensions
apply to solder
balls post-reflow Ball A1 Index Ball A1 Index
on Ø0.35 SMD 9 8 7 3 2 1 (covered by SR)
ball pads.
A
B
C
D
E
F
G
H
12 CTR 14 ±0.1
J
K
L
M
N
P
R
0.8 TYP
T

0.8 TYP 1.1 ±0.1

6.4 CTR 0.25 MIN
9 ±0.1

Note: 1. All dimensions are in millimeters.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics – 1.35V operating IDD Specifications

Electrical Characteristics – 1.35V operating IDD Specifications

Table 5: IDD Maximum Limits - Die Rev. D

Speed Bin
Parameter Symbol Width DDR3L-1066 DDR3L-1333 DDR3L-1600 Units
Operating current 0: One bank IDD0 x4, x8 60 65 75 mA
ACTIVATE-to-PRECHARGE x16 75 80 90 mA
Operating current 1: One bank IDD1 x4 70 75 80 mA
ACTIVATE-to-READ-to-PRE- x8 77 82 87 mA
CHARGE
x16 105 110 115 mA
Precharge power-down current: IDD2P0 All 20 20 20 mA
Slow exit
Precharge power-down current: IDD2P1 All 30 32 37 mA
Fast exit
Precharge quiet standby current IDD2Q All 39 44 47 mA
Precharge standby current IDD2N All 42 45 50 mA
Precharge standby ODT current IDD2NT x4, x8 40 45 50 mA
x16 45 50 55 mA
Active power-down current IDD3P All 53 58 63 mA
Active standby current IDD3N x4, x8 52 57 62 mA
x16 68 73 77 mA
Burst read operating current IDD4R x4 135 155 175 mA
x8 147 164 187 mA
x16 220 240 280 mA
Burst write operating current IDD4W x4 115 135 155 mA
x8 125 145 165 mA
x16 180 200 225 mA
Burst refresh current IDD5B All 205 210 220 mA
Room temperature self refresh IDD6 All 22 22 22 mA
Extended temperature self re- IDD6ET All 28 28 28 mA
fresh
All banks interleaved read cur- IDD7 x4, x8 210 250 290 mA
rent x16 260 285 320 mA
Reset current IDD8 All IDD2P + 2mA IDD2P + 2mA IDD2P + 2mA mA

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics – 1.35V operating IDD Specifications

Table 6: IDD Maximum Limits Die Rev. E, J

Speed Bin
Parameter Symbol Width DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Units
Operating current 0: One IDD0 x4, x8 44 47 55 62 mA
bank ACTIVATE-to-PRE- x16 55 58 66 73 mA
CHARGE
Operating current 1: One IDD1 x4 53 57 61 65 mA
bank ACTIVATE-to-READ-to- x8 59 62 66 70 mA
PRECHARGE
x16 80 84 87 91 mA
Precharge power-down cur- IDD2P0 All 18 18 18 18 mA
rent: Slow exit
Precharge power-down cur- IDD2P1 All 26 28 32 37 mA
rent: Fast exit
Precharge quiet standby cur- IDD2Q All 27 28 32 35 mA
rent
Precharge standby current IDD2N All 28 29 32 35 mA
Precharge standby ODT cur- IDD2NT x4, x8 32 35 39 42 mA
rent x16 35 39 42 45 mA
Active power-down current IDD3P All 32 35 38 41 mA
Active standby current IDD3N x4, x8 32 35 38 41 mA
x16 41 45 47 49 mA
Burst read operating current IDD4R x4 113 130 147 164 mA
x8 123 140 157 174 mA
x16 185 202 235 252 mA
Burst write operating current IDD4W x4 87 103 118 133 mA
x8 95 110 125 141 mA
x16 137 152 171 190 mA
Burst refresh current IDD5B All 144 148 155 162 mA
Room temperature self re- IDD6 All 20 20 20 20 mA
fresh
Extended temperature self IDD6ET All 25 25 25 25 mA
refresh
All banks interleaved read IDD7 x4, x8 160 190 220 251 mA
current x16 198 217 243 274 mA
Reset current IDD8 All IDD2P + 2mA IDD2P + 2mA IDD2P + 2mA IDD2P + 2mA mA

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Electrical Specifications

Table 7: Input/Output Capacitance

Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Capacitance DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Parameters Symbol Min Max Min Max Min Max Min Max Min Max Units
Single-end I/O: DQ, DM CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF
Differential I/O: DQS, CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF
DQS#, TDQS, TDQS#
Inputs (CTRL, CI 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF
CMD,ADDR)

Table 8: DC Electrical Characteristics and Operating Conditions – 1.35V Operation

All voltages are referenced to VSS
Parameter/Condition Symbol Min Nom Max Units Notes
Supply voltage VDD 1.283 1.35 1.45 V 1, 2, 3, 4
I/O supply voltage VDDQ 1.283 1.35 1.45 V 1, 2, 3, 4

Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average
of VDD/VDDQ(t) over a very long period of time (for example, 1 sec).
2. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is
in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 8 (page 27)).

Table 9: DC Electrical Characteristics and Operating Conditions – 1.5V Operation

All voltages are referenced to VSS
Parameter/Condition Symbol Min Nom Max Units Notes
Supply voltage VDD 1.425 1.5 1.575 V 1, 2, 3
I/O supply voltage VDDQ 1.425 1.5 1.575 V 1, 2, 3

Notes: 1. If the minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifi-
cations under the same speed timings as defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is
in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 8 (page 27)).

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Table 10: Input Switching Conditions – Command and Address

Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866 Units

Input high AC voltage: Logic 1 VIH(AC160)min 1 160 160 – mV
Input high AC voltage: Logic 1 VIH(AC135)min 1 135 135 135 mV
Input high AC voltage: Logic 1 VIH(AC125)min1 – – 125 mV
Input high DC voltage: Logic 1 VIH(DC90)min 90 90 90 mV
Input low DC voltage: Logic 0 VIL(DC90)min –90 –90 –90 mV
Input low AC voltage: Logic 0 VIL(AC125)min 1 – – –125 mV
Input low AC voltage: Logic 0 VIL(AC135)min1 –135 –135 –135 mV
Input low AC voltage: Logic 0 VIL(AC160)min 1 –160 –160 – mV

Note: 1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3L-800, two input AC levels are defined: VIH(AC160),min and
VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDRL-800, the address/
command inputs must use either VIH(AC160),min with tIS(AC160) of 215ps or VIH(AC135),min
with tIS(AC135) of 365ps; independently, the data inputs may use either VIH(AC160),min or
VIH(AC135),min.

Table 11: Input Switching Conditions – DQ and DM

Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866 Units

Input high AC voltage: Logic 1 VIH(AC160)min 1 160 160 – mV
Input high AC voltage: Logic 1 VIH(AC135)min 1 135 135 135 mV
Input high AC voltage: Logic 1 VIH(AC130)min 1 – – 130 mV
Input high DC voltage: Logic 1 VIH(DC90)min 90 90 90 mV
Input low DC voltage: Logic 0 VIL(DC90)min –90 –90 –90 mV
Input low AC voltage: Logic 0 VIL(AC130)min 1 – – –130 mV
Input low AC voltage: Logic 0 VIL(AC135)min 1 –135 –135 –135 mV
Input low AC voltage: Logic 0 VIL(AC160)min1 –160 –160 – mV

Note: 1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3L-800, two input AC levels are defined: VIH(AC160),min and
VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDRL-800, the data in-
puts must use either VIH(AC160),min with tIS(AC160) of 90ps or VIH(AC135),min with tIS(AC135)
of 140ps; independently, the address/command inputs may use either VIH(AC160),min or
VIH(AC135),min.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Table 12: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)

Parameter/Condition Symbol Min Max Units

Differential input logic high – slew VIH,diff(AC)slew 180 N/A mV
Differential input logic low – slew VIL,diff(AC)slew N/A –180 mV
Differential input logic high VIH,diff(AC) 2 × (VIH(AC) - VREF) VDD/VDDQ mV
Differential input logic low VIL,diff(AC) VSS/VSSQ 2 × (VIL(AC) - VREF) mV
Single-ended high level for strobes VSEH VDDQ/2 + 160 VDDQ mV
Single-ended high level for CK, CK# VDD/2 + 160 VDD mV
Single-ended low level for strobes VSEL VSSQ VDDQ/2 - 160 mV
Single-ended low level for CK, CK# VSS VDD/2 - 160 mV

Table 13: Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback

DDR3L-800/1066/1333/1600 DDR3L-1866
tDVAC at tDVAC at tDVACat tDVACat tDVACat
Slew Rate (V/ns) 320mV (ps) 270mV (ps) 270mV (ps) 250mV (ps) 260mV (ps)
>4.0 189 201 163 168 176
4.0 189 201 163 168 176
3.0 162 179 140 147 154
2.0 109 134 95 105 111
1.8 91 119 80 91 97
1.6 69 100 62 74 78
1.4 40 76 37 52 55
1.2 Note1 44 5 22 24
1.0 Note1 Note1 Note1 Note1 Note1
<1.0 Note1 Note1 Note1 Note1 Note1

Note: 1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input
signal shall become equal to or less than VIL(ac) level.

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Electrical Specifications

Table 14: RTT Effective Impedance

Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
MR1
[9, 6, 2] RTT Resistor VOUT Min Nom Max Units
0, 1, 0 120Ω RTT,120PD240 0.2 × VDDQ 0.6 1.0 1.15 RZQ/1
0.5 × VDDQ 0.9 1.0 1.15 RZQ/1
0.8 × VDDQ 0.9 1.0 1.45 RZQ/1
RTT,120PU240 0.2 × VDDQ 0.9 1.0 1.45 RZQ/1
0.5 × VDDQ 0.9 1.0 1.15 RZQ/1
0.8 × VDDQ 0.6 1.0 1.15 RZQ/1
120Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/2
0, 0, 1 60Ω RTT,60PD120 0.2 × VDDQ 0.6 1.0 1.15 RZQ/2
0.5 × VDDQ 0.9 1.0 1.15 RZQ/2
0.8 × VDDQ 0.9 1.0 1.45 RZQ/2
RTT,60PU120 0.2 × VDDQ 0.9 1.0 1.45 RZQ/2
0.5 × VDDQ 0.9 1.0 1.15 RZQ/2
0.8 × VDDQ 0.6 1.0 1.15 RZQ/2
60Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/4
0, 1, 1 40Ω RTT,40PD80 0.2 × VDDQ 0.6 1.0 1.15 RZQ/3
0.5 × VDDQ 0.9 1.0 1.15 RZQ/3
0.8 × VDDQ 0.9 1.0 1.45 RZQ/3
RTT,40PU80 0.2 × VDDQ 0.9 1.0 1.45 RZQ/3
0.5 × VDDQ 0.9 1.0 1.15 RZQ/3
0.8 × VDDQ 0.6 1.0 1.15 RZQ/3
40Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/6
1, 0, 1 30Ω RTT,30PD60 0.2 × VDDQ 0.6 1.0 1.15 RZQ/4
0.5 × VDDQ 0.9 1.0 1.15 RZQ/4
0.8 × VDDQ 0.9 1.0 1.45 RZQ/4
RTT,30PU60 0.2 × VDDQ 0.9 1.0 1.45 RZQ/4
0.5 × VDDQ 0.9 1.0 1.15 RZQ/4
0.8 × VDDQ 0.6 1.0 1.15 RZQ/4
30Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/8
1, 0, 0 20Ω RTT,20PD40 0.2 × VDDQ 0.6 1.0 1.15 RZQ/6
0.5 × VDDQ 0.9 1.0 1.15 RZQ/6
0.8 × VDDQ 0.9 1.0 1.45 RZQ/6
RTT,20PU40 0.2 × VDDQ 0.9 1.0 1.45 RZQ/6
0.5 × VDDQ 0.9 1.0 1.15 RZQ/6
0.8 × VDDQ 0.6 1.0 1.15 RZQ/6
20Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/12

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Table 15: Reference Settings for ODT Timing Measurements

Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Measured
Parameter RTT,nom Setting RTT(WR) Setting VSW1 VSW2
tAON RZQ/4 (60Ω) N/A 50mV 100mv
RZQ/12 (20Ω) N/A 100mV 200mV
tAOF RZQ/4 (60Ω) N/A 50mV 100mv
RZQ/12 (20Ω) N/A 100mV 200mV
tAONPD RZQ/4 (60Ω) N/A 50mV 100mv
RZQ/12 (20Ω) N/A 100mV 200mV
tAOFPD RZQ/4 (60Ω) N/A 50mV 100mv
RZQ/12 (20Ω) N/A 100mV 200mV
tADC RZQ/12 (20Ω) RZQ/2 (20Ω) 200mV 250mV

Table 16: 34Ω Driver Impedance Characteristics

Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
MR1
[5, 1] RON Resistor VOUT Min Nom Max1 Units
0, 1 34.3Ω RON,34PD 0.2 × VDDQ 0.6 1.0 1.15 RZQ/7
0.5 × VDDQ 0.9 1.0 1.15 RZQ/7
0.8 × VDDQ 0.9 1.0 1.45 RZQ/7
RON,34PU 0.2 × VDDQ 0.9 1.0 1.45 RZQ/7
0.5 × VDDQ 0.9 1.0 1.15 RZQ/7
0.8 × VDDQ 0.6 1.0 1.15 RZQ/7
Pull-up/pull-down mismatch (MMPUPD) VIL(AC) to VIH(AC) –10 N/A 10 %

Note: 1. A larger maximum limit will result in slightly lower minimum currents.

Table 17: 40Ω Driver Impedance Characteristics

Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
MR1
[5, 1] RON Resistor VOUT Min Nom Max1 Units
0, 0 40Ω RON,40PD 0.2 × VDDQ 0.6 1.0 1.15 RZQ/6
0.5 × VDDQ 0.9 1.0 1.15 RZQ/6
0.8 × VDDQ 0.9 1.0 1.45 RZQ/6
RON,40PU 0.2 × VDDQ 0.9 1.0 1.45 RZQ/6
0.5 × VDDQ 0.9 1.0 1.15 RZQ/6
0.8 × VDDQ 0.6 1.0 1.15 RZQ/6
Pull-up/pull-down mismatch (MMPUPD) VIL(AC) to VIH(AC) –10 N/A 10 %

Note: 1. A larger maximum limit will result in slightly lower minimum currents.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Table 18: Single-Ended Output Driver Characteristics

Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Parameter/Condition Symbol Min Max Units
Output slew rate: Single-ended; For rising and falling SRQse 1.75 6 V/ns
edges, measure between VOL(AC) = VREF - 0.09 × VDDQ
and VOH(AC) = VREF + 0.09 × VDDQ

Table 19: Differential Output Driver Characteristics

Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Parameter/Condition Symbol Min Max Units
Output slew rate: Differential; For rising and falling SRQdiff 3.5 12 V/ns
edges, measure between VOL,diff(AC) = –0.18 × VDDQ and
VOH,diff(AC) = 0.18 × VDDQ
Output differential crosspoint voltage VOX(AC) VREF - 135 VREF + 135 mV

Table 20: Electrical Characteristics and AC Operating Conditions

Note 1 applies to base timing specifications
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Units
DQ Input Timing
Data setup Base tDS 90 – 40 – N/A – N/A – N/A – ps
time to DQS, (specification) (AC160)
DQS# VREF @ 1 V/ns 250 – 200 – N/A – N/A – N/A – ps
Data setup Base tDS 140 – 90 – 45 – 25 – N/A – ps
time to DQS, (specification) (AC135)
DQS# VREF @ 1 V/ns 275 – 225 – 180 – 160 – N/A – ps
Data hold Base tDH 160 – 110 – 75 – 55 – N/A – ps
time from (specification) (DC90)
DQS, DQS# VREF @ 1 V/ns 250 – 200 – 165 – 145 – N/A – ps
Data setup Base tDS N/A – N/A – N/A – N/A – 70 – ps
time to DQS, (specification) (AC130)
DQS# VREF @ 2 V/ns N/A – N/A – N/A – N/A – 135 – ps
Data hold Base tDH N/A – N/A – N/A – N/A – 75 – ps
time from (specification) (DC90)
DQS, DQS# VREF @ 2 V/ns N/A – N/A – N/A – N/A – 110 – ps
Command and Address Timing
CTRL, CMD, Base tIS 215 – 140 – 80 – 60 – N/A – ps
ADDR setup (specification) (AC160)
to CK, CK# VREF @ 1 V/ns 375 – 300 – 240 – 220 – N/A – ps
CTRL, CMD, Base tIS 365 – 290 – 205 – 185 – 65 – ps
ADDR setup (specification) (AC135)
to CK, CK# VREF @ 1 V/ns 500 – 425 – 340 – 320 – 200 – ps

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Table 20: Electrical Characteristics and AC Operating Conditions (Continued)

Note 1 applies to base timing specifications
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Units
CTRL, CMD, Base tIS N/A – N/A – N/A – N/A – 150 – ps
ADDR setup (specification) (AC125)
to CK, CK# VREF @ 1 V/ns N/A – N/A – N/A – N/A – 275 – ps
CTRL, CMD, Base tIH 285 – 210 – 150 – 130 – 110 – ps
ADDR hold (specification) (DC90)
from CK, CK# V
REF @ 1 V/ns 375 – 300 – 240 – 220 – 200 – ps

Notes: 1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC160),min and
VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDR3-800, the address/
command inputs must use either VIH(AC160),min with tIS(AC160) of 215ps or VIH(AC135),min
with tIS(AC135) of 365ps; independently, the data inputs must use either VIH(AC160),min
with tDS(AC160) of 90ps or VIH(AC135),min with tDS(AC135) of 140ps.
2. When DQ single-ended slew rate is 1V/ns, the DQS differential slew rate is 2V/ns; when
DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns;

Table 21: Derating Values for tIS/tIH – AC160/DC90-Based

ΔtIS, ΔtIH Derating (ps) – AC/DC-Based

CK, CK# Differential Slew Rate
CMD/ADDR
Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
V/ns ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95
1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 –1 –3 –1 –3 –1 –3 7 5 15 13 23 21 31 31 39 47
0.8 –3 –8 –3 –8 –3 –8 5 1 13 9 21 17 29 27 37 43
0.7 –5 –13 –5 –13 –5 –13 3 –5 11 3 19 11 27 21 35 37
0.6 –8 –20 –8 –20 –8 –20 0 –12 8 –4 16 4 24 14 32 30
0.5 –20 –30 –20 –30 –20 –30 –12 –22 –4 –14 4 –6 12 4 20 20
0.4 –40 –45 –40 –45 –40 –45 –32 –37 –24 –29 –16 –21 –8 –11 0 5

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Table 22: Derating Values for tIS/tIH – AC135/DC90-Based

ΔtIS, ΔtIH Derating (ps) – AC/DC-Based

CK, CK# Differential Slew Rate
CMD/ADDR
Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
V/ns ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 95
1.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 2 –3 2 –3 2 –3 10 5 18 13 26 21 34 31 42 47
0.8 3 –8 3 –8 3 –8 11 1 19 9 27 17 35 27 43 43
0.7 6 –13 6 –13 6 –13 14 –5 22 3 30 11 38 21 46 37
0.6 9 –20 9 –20 9 –20 17 –12 25 –4 33 4 41 14 49 30
0.5 5 –30 5 –30 5 –30 13 –22 21 –14 29 –6 37 4 45 20
0.4 –3 –45 –3 –45 –3 –45 6 –37 14 –29 22 –21 30 –11 38 5

Table 23: Derating Values for tIS/tIH – AC125/DC90-Based

ΔtIS, ΔtIH Derating (ps) – AC/DC-Based

CK, CK# Differential Slew Rate
CMD/ADDR
Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
V/ns ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 63 45 63 45 63 45 71 53 79 61 87 69 95 79 103 95
1.5 42 30 42 30 42 30 50 38 58 46 66 54 74 64 82 80
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 3 –3 3 –3 3 –3 11 5 19 13 27 21 35 31 43 47
0.8 6 –8 6 –8 6 –8 14 1 22 9 30 17 38 27 46 43
0.7 10 –13 10 –13 10 –13 18 –5 26 3 34 11 42 21 50 37
0.6 16 –20 16 –20 16 –20 24 –12 32 –4 40 4 48 14 56 30
0.5 15 –30 15 –30 15 –30 23 –22 31 –14 39 –6 47 4 55 20
0.4 13 –45 13 –45 13 –45 21 –37 29 –29 37 –21 45 –11 53 5

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Table 24: Minimum Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD Transition

DDR3L-800/1066/1333/1600 DDR3L-1866
Slew Rate (V/ns) tVAC at 160mV (ps) tVAC at 135mV (ps) tVAC at 135mV (ps) tVAC at 125mV (ps)
>2.0 70 209 200 205
2.0 53 198 200 205
1.5 47 194 178 184
1.0 35 186 133 143
0.9 31 184 118 129
0.8 26 181 99 111
0.7 20 177 75 89
0.6 12 171 43 59
0.5 Note 1 164 Note 1 18
<0.5 Note 1 164 Note 1 18

Note: 1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input
signal shall become equal to or less than VIL(AC) level.

Table 25: Derating Values for tDS/tDH – AC160/DC90-Based

ΔtDS, ΔtDH Derating (ps) – AC/DC-Based

DQS, DQS# Differential Slew Rate

DQ Slew 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Rate V/ns ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 80 45 80 45 80 45
1.5 53 30 53 30 53 30 61 38
1.0 0 0 0 0 0 0 8 8 16 16
0.9 –1 –3 –1 –3 7 5 15 13 23 21
0.8 –3 –8 5 1 13 9 21 17 29 27
0.7 –3 –5 11 3 19 11 27 21 35 37
0.6 8 –4 16 4 24 14 32 30
0.5 4 6 12 4 20 20
0.4 –8 –11 0 5

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 4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications

Table 26: Derating Values for tDS/tDH – AC135/DC90-Based

ΔtDS, ΔtDH Derating (ps) – AC/DC-Based

DQS, DQS# Differential Slew Rate

DQ Slew 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Rate V/ns ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 68 45 68 45 68 45
1.5 45 30 45 30 45 30 53 38
1.0 0 0 0 0 0 0 8 8 16 16
0.9 2 –3 2 –3 10 5 18 13 26 21
0.8 3 –8 11 1 19 9 27 17 35 27
0.7 14 –5 22 3 30 11 38 21 46 37
0.6 25 –4 33 4 41 14 49 30
0.5 39 –6 37 4 45 20
0.4 30 –11 38 5

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Table 27: Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns

Shaded cells indicate slew rate combinations not supported
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQS, DQS# Differential Slew Rate
DQ Slew Rate V/ns

8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

4.0 33 23 33 23 33 23
3.5 28 19 28 19 28 19 28 19
3.0 22 15 22 15 22 15 22 15 22 15
2.5 13 9 13 9 13 9 13 9 13 9
2.0 0 0 0 0 0 0 0 0 0 0
1.5 –22 –15 –22 –15 –22 –15 –22 –15 –14 –7
1.0 –65 –45 –65 –45 –65 –45 –57 –37 –49 –29
0.9 –62 –48 –62 –48 –54 –40 –46 –32 –38 –24
25

0.8 –61 –53 –53 –45 –45 –37 –37 –29 –29 –19
0.7 –49 –50 –41 -42 –33 –34 –25 –24 –17 –8
0.6 –37 -49 –29 –41 –21 –31 –13 –15
Micron Technology, Inc. reserves the right to change products or specifications without notice.

0.5 –31 –51 –23 –41 –15 –25

0.4 –28 –56 –20 –40

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications
© 2011 Micron Technology, Inc. All rights reserved.
 4Gb: x4, x8, x16 DDR3L SDRAM
Initialization

Table 28: Minimum Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition

Slew Rate (V/ns) tVAC at 160mV (ps) tVAC at 135mV (ps) tVAC at 130mV (ps)
>2.0 165 113 95
2.0 165 113 95
1.5 138 90 73
1.0 85 45 30
0.9 67 30 16
0.8 45 11 Note1
0.7 16 Note1 –
0.6 Note1 Note1 –
0.5 Note1 Note1 –
<0.5 Note1 Note1 –

Note: 1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input
signal shall become equal to or less than VIL(AC) level.

Initialization
If the SDRAM is powered up and initialized for the 1.35V operating voltage range, volt-
age can be increased to the 1.5V operating range provided that:
• Just prior to increasing the 1.35V operating voltages, no further commands are issued,
other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
• The 1.5V operating voltages are stable prior to issuing new commands, other than
NOPs or COMMAND INHIBITs.
• The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to
any READ command.
• The ZQ calibration is performed. tZQinit must be satisfied after the 1.5V operating
voltages are stable and prior to any READ command.
If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage
can be reduced to the 1.35V operation range provided that:
• Just prior to reducing the 1.5V operating voltages, no further commands are issued,
other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
• The 1.35V operating voltages are stable prior to issuing new commands, other than
NOPs or COMMAND INHIBITs.
• The DLL is reset and relocked after the 1.35V operating voltages are stable and prior to
any READ command.
• The ZQ calibration is performed. tZQinit must be satisfied after the 1.35V operating
voltages are stable and prior to any READ command.

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 4Gb: x4, x8, x16 DDR3L SDRAM
Initialization

VDD Voltage Switching

After the DDR3L DRAM is powered up and initialized, the power supply can be altered
between the DDR3L and DDR3 levels, provided the sequence in Figure 8 is maintained.

Figure 8: VDD Voltage Switching

Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk

(( (( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) )) ))
CK, CK# (( (( (( (( (( ((
(( (( (( ((
)) )) )) )) )) )) )) )) )) ))

tCKSRX
TMIN = 10ns
VDD, VDDQ (DDR3) (( ((
(( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) ))
VDD, VDDQ (DDR3L) (( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) ))

TMIN = 10ns

TMIN = 200µs

T = 500µs

(( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) ))
RESET# ((
))
tIS
(( TMIN = 10ns (( (( (( (( (( (( ((
)) )) )) )) )) )) )) ))
CKE Valid
(( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) ))

tDLLK

tXPR tMRD tMRD tMRD tMOD tZQinit

tIS
(( ((
(( (( (( (( (( ((
((
)) )) )) )) )) )) )) )) ))
Command Note 1 MRS MRS MRS MRS ZQCL Note 1 Valid
(( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) ))
)) ))

(( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) ))
BA (( MR2 (( MR3 (( MR1 (( MR0 (( (( ((
Valid
(( ((
)) )) )) )) )) )) )) )) ))

tIS tIS
(( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) ))
ODT Static LOW in case RTT,nom is enabled at time Tg, otherwise static HIGH or LOW Valid
(( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) ))

RTT (( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) ))

((
))
Time break Don’t Care
((
))

Note: 1. From time point Td until Tk, NOP or DES commands must be applied between MRS and
ZQCL commands.

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www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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© 2011 Micron Technology, Inc. All rights reserved.