AN EFFICIENT RECONFIGURABLE SoC SYSTEM DESIGN

WITH NIOS II PROCESSOR

R.Balakumar1 S.Kalimuthukumar2
1 2
PG Student Assistant Professor-I
Electrical and Electronics Engineering Electrical and Electronics Engineering
Kalasalingam University Kalasalingam University
Krishnankoil, Tamilnadu, India-626126 Krishnankoil, Tamilnadu, India-626126
srivibala@gmail.com kali.12eee@gmail.com

ABSTRACT (SoC). The processor cores can be designed to be dedicated for a SoC
and reusing of generic processors is often preferred due to time to
The purpose of the paper is to reduce memory and power of an market constraints. The processor core which is adaptable to many
embedded system. In earlier, embedded processors to perform different things. It can be completely applied using logic synthesis
the task whereas power and energy constraints should be lower. [5]. The Nios II processor which is provided by Altera family to be
There are several tools available for improving the power and implemented in FPGA and also lots of softcore processors available
energy for low level processors. With the evolution of technology, in the market. Nowadays, growing complexity of applications has
the system complexity get increased and the application fields of made design of challenging. The most effective way to implement
the embedded system expanded. The need of high performance area and power consumption for efficient architectures is to design
applications has led to the development of System on Chip (SoC). fully dedicated ones. It provides options for configure the softcore
This paper presents the design of SoC (System on Chip) for the processor. The several softcore processors are Nios II, Microblaze,
required hardware. Analyze the energy and power for the design Picoblaze, Xtensa are the softcore processors provided by Altera,
in Quartus II. The evolution of technologies is enabling to the Xilinx, Tensilica respectively. There are several use of softcore
integration of complex platforms in a single chip (called system- processors available for the developer of an embedded system. The
on-chip, SoC) including one or several CPU subsystems to softcore processors which is flexible, hence it can be customized for
execute software and sophisticated interconnect in addition to for a specific application need [2].
specific hardware subsystems. The Hardware level design is to be Field Programmable Gate Array (FPGA) is configured by the end
done in the Quartus II and Qsys. The design of SoC is to be done user. In FPGA, We can test and validate our design. Instead of ASIC,
in the Qsys System Integration for the VGA display. The power it is useful for low production, simple design cycle and time to
tool to obtain power/energy estimation of complete system of market.
SoC. The power / energy accuracy trade-offs for the SoC is to be The Organisation of the paper is as follows: Section I provides
measured. Then analyse the power and energy measures using Design cycles for FPGA and ASIC Section II gives Hardware &
power analyzer tool. Reduce the unnecessary logic and reduce Software Codesign. Section III Advantages and Disadvantages of
memory access. It will reduces the power usage in the using IP. In Section IV gives the Implementation of Hardware &
application. The usefulness and the effectiveness of the proposed Software Codesign. We conclude in Section V and with some
system is achieved by using FPGA cyclone board with the help of comments on future work.
Computer Aided Design Tools. The CAD tools are Quartus
Altera II, Qsys, and Nios IDE Eclipse. 1.DESIGN CYCLES FOR FPGA AND ASIC

GENERAL TERMS Due to the efficient design cycle of FPGAs, it is considered

for developing rapid prototypes during the embedded system
SoC (System on Chip), CAD (Computer Aided Design), VGA design process. With the use of prototypes, it is also important
(Video Graphics Array), Quartus II, Qsys. that simulations be performed to further speed up the design
process. Simulations are useful even before developing a
prototype of the device or system. It is preferable that both are
INTRODUCTION
used when developing. FPGA should be used instead of
All Embedded Systems which is the combination of both hardware ASICs. FPGA have simple design cycle compared to ASIC. It
and software components working together to perform a specific is faster time to market. The functionality of the FPGA can be
application. Nowadays, the design of embedded systems is become customized in the field.
difficult due to the constraints on accessing area, usage of memory
size, power consumption and performance of the system [1]. Added I. HARDWARE AND SOFTWARE CODESIGN
with designers facing time to market deadlines. Altera's Nios II
processor is the world's most versatile processor [18]. It is more The Hardware and software codesign of today’s systems to
suitable for wide range of embedded computing applications. The Trade-off performance, power and dependability in multi-core
embedded processor cores are integrated into most System on Chip processors. In Software based techniques are severely limited
by observability and control ability of the hardware due to The Nios II IDE is based on the open, extensible Eclipse
strict abstraction layers. This gives rise to the problem of IDE project and the Eclipse C/C++ Development Tools
matching the performance requirements of a specific Project [16]. The project manager automates setup of the
application of a processor. C/C++ application project and system library projects. Nios II
The application design consists of three types of development: IDE provides software code examples (in the form of project
hardware design and software design and System Design. templates) to bring up working systems as quickly as possible.
Each template is a collection of software files and project
1.1 Hardware Design settings. Custom source code can be added to the project by
The hardware design which is done by Qsys Builder placing the code in the project directory or importing the files
available in the Quartus II. Using Qsys Builder we can specify into the project. Full-featured source editor and C/C++
the Nios II processor cores, memory, and required other compiler is within the Nios II software.
components. It interconnect the logic automatically to The Nios II IDE build environment automatically produces
integrate the components in the hardware system. The Qsys a make file based on the specific system configuration.
Builder which is nothing but system integration tool [14]. It Changes made in the Nios II IDE compiler/linker settings are
saves significant time & effort in the FPGA design process by automatically reflected in this auto-generated make file. The
automatically generating interconnect logic to connect IP Nios II IDE Debugger contains basic debug features such as
functions and subsystems software breakpoints, disassembly code view, debug
1.1.1 Qsys Builder information view, and Instruction Set Simulator (ISS) target.
The Qsys builder which is used to integrates the Advanced debugging capabilities are also supported.
components in the hardware system. The Qsys which allows Hardware breakpoint functionality for decoding code in the
the users to put together a system using already available and ROM or flash is available. Data triggers and instruction trace
or custom components. After interconnecting components get are also useful for debugging the embedded system software.
downloaded into the target board. Below Fig. 3. Represents
the general system which contains processor and several I/O That file which was included in the Nios II IDE for creating
components in the design then the system is bulky and costly. the software application. Hence, the file included in Nios II
In Fig.4. It represents the small system of hardware IDE and after that create BSP (Board Support Package)
components. The system gets reduced by using Qsys builder. settings for the application. Then develop the application by
This small system will give optimized performance. The writing C/C++ program for our application. After that build
errors also get reduced and debugged easily because of this the project in Nios II IDE. If it successfully build means it will
small system. create .elf file i.e Executable and Linkable file. The successful
creation of .elf file only run the application. Otherwise debug
the application if it shows the error.
CPU
SDRAM SDRAM 1.3 System Design
I/O The System Design is the integrating of both hardware and
FPGA software. The CAD design tools such as Quartus II, Qsys, and
Flash Nios II IDE used to develop the application with high
I/O Flash
FPGA performance. In this design we can assign memory for our
application. In normally processors can’t able to change the
size of memory. It is difficult for running the complex task. In
I/O DSP
SoC design it is easy to change the memory size and also
Fig. 3 General System Fig. 4.Qsys System
reduce the memory access. In Fig. 5 It shows the hardware
and software codesign. The hardware portion of the design
1.2 Software Design process consists of using Verilog or VHDL to define custom
The Nios II Integrated Development Environment (IDE) is hardware, using parts from the library, or gate level parts.
the main softwaretool provided by Altera when designing Often a design environment or board contains intellectual
using Altera FPGAs. This software tool is mainly used when property that can be integrated into the design. Configurable
the FPGA has the capability of housing a softcore, Nios, regions or parts are developed and available in design
embedded processor. The Nios II IDE contains the following environments. These are used for commonly used components
main functions for software development such as arithmetic functions. The use of embedded processors
 Project Manager in the design is a major decision. The decision depends on the
 Editor and Compiler application and design parameters.
 Debugger The software process choices depend on the tools available
to the designer. Using a supported processor core assist when
 C-to-Hardware (C2H) Acceleration Compiler
designing the software for the embedded system because of
 Flash Programmer the software tools that come with the processor.
 Nios II Software Build Tools
 Three Phases of using IP

Analyze System Requirements Unplaced-and- Places-and-

Specifications RTL Level (a) Unrouted Routed
Netlist(b) Netlist(c)
Custom design. cycle-accurate
Nios II
Instruction & C/C++ model
cores & Define & Generate System in
Custom for functional
Standard SOPC Builder
Peripheral verification
Peripherals Expensive
Logic
and hard to
Placement for
find. Cannot remove
elements may
Altera HAL & Implementati unwanted
Custom Integrate Qsys be absolute
Develop Software Peripheral on is less Functionality
Hardware Builder System into Cannot
with the Nios II IDE Disadvantages efficient in Device tied to
Modules Quartus II Project Drivers modify the
terms of FPGA vendor
code to
resource and device
remove extra
requirements family
functionality
Assign Pin, User C/C++ and
Locations, Timing Application performance
Requirements and Code &
Run/Debug Software
other Design Custom
using ISS in Nios II
Constraints Libraries 2.1.1 Stages of Software Development
IDE
When beginning software development, five key tasks
are performed along the design path to a final product. These
five stages, in order of development, are software design and
Download Software entry, compilations and/ or assembly, linking, and execution.
Compile Hardware
Executable to Nios II
Design for Target
System on Target
Board
Board 3 IMPLEMENTATION
The Prototyping platform using FPGA Altera DE0
development board has the cyclone III FPGA chip.The CAD
Run/Debug Software on Target tools that are available for the Altera DE0 board are Altera
Board Quartus, Qsys builder and Nios IDE. The Quartus is the
Fig. 5 Hardware & Software Codesign [16]
foundation for FPGA logic design. The Qsys (system on
integration) Builder is accessed through Quartus and it is to
When completing the software part, it can also be seen as a customize the Nios II soft processor core. Once the hardware
hardware block with inputs and outputs. The external has been specified, the C/C++ software application can be
connections to the software block either connect to an external developed using Nios II IDE.
port of the embedded system or there are interconnections The peripherals of the development board range from the
between the hardware and software parts of the system. JTAG programming interface to the VGA ports. The board
consists of internal clock as 50 MHz oscillator are part of the
development board. The Cyclone series of FPGAs all contain
2 ADVANTAGES AND DISADVANTAGES OF USING IP CORE Nios II embedded processors, graphics hardware acceleration,
There are three phases of FPGA development where IP can memory interface and the Avalon switch fabric (ASF). The
be used in the design. The phases which are from lowest level embedded processor available for the cyclone III FPGA is a
to highest level, Register Transfer Level (RTL), Unplaced and softcore processor. Nios II processors implement a 32-bit
Unrouted Netlist Netlist Level (UUNL), and Placed and instruction set based on a RISC architecture. It is a soft-core
Routed Netlist Level (PRNL). The advantages and processor, the designer can choose from a countless of system
disadvantages of using the IP at the three phases are shown in configurations, choose the best CPU IP core as well as
selecting peripherals.
The Design flow consists of two stages Hardware design
TABLE I. and software design.
Three Phases of using IP
3.1 Hardware Design
Unplaced-and- Places-and- The hardware design by using the Qsys Builder. The Qsys
Specifications RTL Level (a) Unrouted Routed
Netlist(b) Netlist(c)
consists of IP core several components which is already
Can modify Optimal Obtain available in the Qsys builder. The hardware is broken into
code to implementation highest level three components namely Nios II system, SDRAM, VGA
remove in terms of of controller. The Fig. 8 which shows that SoC for hardware
Advantages
unnecessary resource performance
functions utilization and IP vendor
design.
motivated by performance provides
3.1.1 Nios II processor VGA, it means that 40 characters can be displayed per line
The Nios II processor is the world’s most versatile and the VGA core can support up to 30 lines. The fig. 8 which
processor. There are three types of Nios II CPU cores shows the SoC design for character get displayed on the VGA
available. The choice of the CPU core provides the designer monitor while the SoC design get successful in the Qsys
with the opportunity to change the design to the application integration tools.
demands. In [15], the table below summarizes the types of Reset Clock Pixel Clock
cores and the features of each one.
TABLE II.

Nios II Processor DAC

Avalon VGA Controller
Switch Module
Nios II/f (fast) Niod II/e (economy) Nios II/s (standard)
Designed to Fabric
Designed for Signals
Designed for smallest maintain a balance
maximum
possible logic utilization between
performance at the
of FPGAs performance and
expense of core size. Pixel Buffer Character Buffer
cost.

3.1.2 Avalon Switch Interface Fig. 7 Block Diagram of VGA core [8]
Nios II uses the Avalon switch fabric as the interface to its In Pixel mode, the VGA core uses the RGB color model, it
embedded peripherals. When compared to a traditional bus in have the following color space settings are available. It is 16-
a normal processor based system it only gives one bus master bit color mode that is Red and blue have 5-bit color spaces.
access the bus at a time. But in Avalon switch fabric, using a Whereas green has a 6-bit color space. Then it have 8-bit color
slave side arbitration so multiple masters operate mode for grayscale [8].
simultaneously. The major hardware circuit is designed based on the
Host Computer resources of DE0 development board. The Cyclone
VGA
Monitor
EP3C16F484 FPGA as the main chip [13]. The Qsys builder
USB Blaster achieves the connections of various IP core then it is
Interface
integrated with Quartus II, it completes the work of Nios II
softcore processor and connected peripherals. The Nios II
processor was set up using the Qsys builder. The processor
VGA Nios II JTAG Debug JTAG UART components are selected and added as shown in Fig. 10.
Controller Processor module interface

Avalon Switch fabric

CYCLONE III
FPGA Chip
On-Chip memory SDRAM controller

Nios II Processor

SDRAM Chip

Fig. 6 Hardware level design VGA controller core

3.1.3 VGA Controller Core

The VGA core supports 640 x 480 resolution, it can support
SDRAM controller core
three display modes pixel mode, character mode, and
character overlay mode. In a 640 by 480 pixel mode and 60
Hz refresh rate, there is approximately 40 ns per pixel. In our
design first analysis with character buffer it is used to display
the characters on VGA then after that with pixel buffer, the
VGA core uses the RGB color model to the VGA display. In
character mode it is used to display the characters. Two sizes
are supported in the character buffer. They are 8x8 here the
character occupies an 8x8 in VGA which means that 80
characters can be displayed per line and the VGA core can
support up to 60 lines. At last 16x16 it occupies 16x16 in Fig. 8 SoC Design for Character Display
3.2 Integration of SoC into Quartus II The software for the application is written in the Nios II
The SoC design which is integrated into the HDL in IDE. It is written using C or C++. The Nios II library functions
Quartus II. The HDL means using VHDL, Verilog or were used to implement the VGA controller core and SDRAM.
schematic. But here Verilog was used to implement the SoC The C code for application was written then performed
design. The programmer allows us to configure all Altera compilation and debug. The successful compilation of the
devices supported by the Quartus II software with files application generated the .elf file. The .elf file get downloaded
generated by the compiler. The Quartus II compiler generates to the DE0 Board through USB blaster cable. Then after that
programming files that the programmer can use to program or run the application it was successfully runs in our design.
configure a device with Altera programming hardware. The
USB Blaster is used to interface with DE0 board and PC. In
JTAG programming mode is used to program the device. The Fig. 12 Final implementaion of VGA display
hardware design get loaded to the FPGA device. It will not run
the application. It get runs the application only after the Fig. 10 shows the implementation of VGA monitor interfaced
software part for the application loads to the board then if it is with FPGA board using CAD tools. It shows the result of our
successful design means it will run the application. research and experiment.
3.3 Software Design
The main function of the software is to initialize and
control the peripherals. The software aspect is straightforward,
but the uncertainty is present when using the HAL and direct
register functions. In Fig. 9 it shows the software design flow,
in these software design which is developed in the Nios II IDE
Eclipse.
The VGA controller that is available for the DE0 board
contains a limited amount of function support. It is unclear as
to how to control the VGA, but during implementation a better
understanding can be gained. Once experience is gained in
using the functions and libraries within the Nios II IDE,
implementation of the application software will be get quickly
completed.

Import .SOPC info file

The softcore processor using FPGA is designed and
implemented for VGA Monitor to interface with FPGA board.
Create BSP for CPU file

Write C Code for our application

Build the application code

Debug

Run the application code on the target board

VGA functions are used to display each pixel

to the VGA monitor
Fig. 9 Software Design Flow Fig. 11 Design analysis report
 [3] Bertrand Le Gal, Christophe Jego “Softcore Processor
Optimization According to Real-Application Requirements”
IEEE Embedded Systems Letters, Vol.5, No.1, March 2013.
[4] Mike Dyer, Amit Kumar Gupta and Natalie Galin “Nios II
Processor-BasedHardware/Software Co-Design of the JPEG
2000 Standard” Nios II Embedded Processor Design contest-
2005.
[5] Jason G.Tong, Ian D.L.Anderson and Mohammed A.S.Khalid
“Soft-Core Processors for Embedded Systems” The 18th
International Conference on Microelectronics (ICM) 2006.
[6] PONG P.CHU” Embedded SoPC design with Nios II processor
and Verilog examples” A John Wiley & Sons, Inc., Publication
2012.
[7] “VGA CORE for Altera DE1/DE2 Boards” Altera Corporation
University Programs, Oct 2006.
[8] Jerraya, A. “Long Term Trends for Embedded System Design”
IEEE Euromicro symposium On Digital System Design, Sep
2004.
[9] Maxfield, C. “The Design Warrior’s Guide to FPGAs.” Elsevier.
2004.
[10] “Quartus II Version 7.2 Handbook Volume 5: Altera Embedded
Peripherals.” Altera Corporation.
[11] Altera “DE0_User_Manual for DE0 series Board” Terasic, May
2009.
[12] “Embedded Software.” Altera Corporation.
Fig. 12 Powerplay power analyzer report
[13] “DE0 Development and Education Board”, Altera Corporation.
DE0 CD-ROM. DE0 Schematics PDF.
In Fig 11 and Fig. 12 shows the analyses report of resources
[14] “Quartus II Version 13 Handbook: Introduction to the Altera
used and also thermal power dissipation of our design. Qsys System Integration Tool.” Altera Corporation.
[15] “Nios II 7.1 Processor Reference Handbook. “Altera
4 CONCLUSION
Corporation.
This paper demonstrated the hardware and software [16] “Nios II 7.1 Software Developer’s Handbook.” Altera
codesign of using Nios II processor was done. The design of an Corporation.
embedded system is implemented on FPGA with the help of [17] “Cyclone III Device Handbook.” Altera Corporation.
HDL. While designing of an embedded system the memory [18] Altera Corporation Website, www.altera.com.
and power of an application get optimized. It utilized only [19] Maxfield, C. “The Design Warrior’s Guide to FPGAs.” Elsevier.
about 26% resources. The VGA core function to draw pixels 2004.
across the screen was tested. The Altera DE0 board used a SD
card to store the image that test image was displayed on the
VGA was successful.
ACKNOWLEDGMENT
This research project would not have been possible without
the support of my guide, teachers and friends. The authors are
grateful to the management and the head of the Institution of
Kalasalingam University for giving all necessary support and
providing facilities for making this research paper a successful
one. This knowledgably guidance helped me to complete up
to this stage and hope will continue in further research.

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