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RCViewer

This document describes RCViewer+, a tool for analyzing reversible and quantum circuits. It supports various quantum gates and allows inputting circuits, calculating costs, decomposing gates, and more. The tool has been updated over time to support additional gates and features.

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0% found this document useful (0 votes)
295 views7 pages

RCViewer

This document describes RCViewer+, a tool for analyzing reversible and quantum circuits. It supports various quantum gates and allows inputting circuits, calculating costs, decomposing gates, and more. The tool has been updated over time to support additional gates and features.

Uploaded by

Girija
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

RCViewer+ Description:

Version 2.5 (May 7, 2013) Download.

Authors: Mona Arabzadeh/ Mehdi Saeedi .

RCViewer+ is a viewer/analyzer for working with reversible and quantum circuits from textual
input file. RCViewer+ supports NCT and NCTSF gate libraries and generalized Toffoli/Fredkin
gates with both positive and negative controls. In addition, Hadamard, Controlled-V, Controlled-
V+, Peres, T , T † , and S gates are supported. The first idea for producing this viewer was gotten
from RCViewer software with an extension of displaying negative controls as well as supporting
various quantum gates. For background on reversible circuits and different synthesis techniques
refer to Synthesis and Optimization of Reversible Circuits - A Survey.
——————————————————————————————————————————–
RCViewer+ Features:
• Support generalized Toffoli and Fredkin gates with both positive and negative controls. Ex-
amples include NOT, CNOT, Toffoli and SWAP gates.
• Support Hadamard, Controlled-V, Controlled-V+, Peres, T , T † , and S gates.

• Get input circuit in .tfc format


• Save displayed circuit in bitmap format
• Calculate the quantum cost

• Count the number of 1- and 2-qubit gates based on the cost model by Maslov and Saeedi
• Show a compact form of the given circuit
• Decompose a given circuit into 1- and 2-qubit gates based on papers by Barenco et al, and
Maslov et al, and Figure 4.9 (decomposition into Clifford+T gates) of the book by Nielsen
& Chuang.

• Show the truth table (in binary or decimal) and its cycle representation for the active circuit
• Support PLA verification
• Support equivalence checking

• Support latex q-circuit output


• Support real format version 1.0 in input and output
• For a given circuit with generalized Toffoli gates, RCViewer+ can suggest an optimization
based on the result of this paper

Input Format:
The .tfc input format is used in RCViewer+. Positive controls are displayed with the name of
desired variable (e.g., x) and negative controls are displayed with Apostrophe (’) notation over the
variable (e.g., x’). Negative control is supported for NCTSF library. RCViewer+ also supports
input circuit in real format version 1.0.

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Quantum Cost Calculation:

Quantum cost: For quantum cost calculation, the latest quantum cost table is used. For cal-
culating quantum cost for gates with negative controls a recent paper is used. Based on it, the
quantum cost of generalized Toffoli gates with at least one positive control is the same as those
with all positive controls. The quantum cost of generalized Toffoli gates with all negative controls
is increased by 2. The quantum cost of CNOT gates with negative control and Toffoli gates with
only negative controls is 3 and 6, respectively. The quantum cost of a generalized Fredkin gate
(with any number of positive or negative controls) is equal to the cost of a generalized Toffoli
gate with positive controls plus 2. Peres gate (with cost 4) is also considered in quantum cost
calculation. Controlled-V (unit-cost), Controlled-V+ (unit-cost) and Hadamard (with cost 0) are
also supported. Quantum cost calculation will be updated whenever new cost model is proposed.

2-qubit cost model: A single-number cost model based on the number of two-qubit operations
required to simulate a given gate, as described in this paper where costs of both n-qubit Toffoli
and n-qubit Fredkin gates (and n ≥ 3) are estimated as 10n − 25. QC of a circuit is calculated by
a summation over the QCs of its gates.

Future plans:
• A better PLA verification, truth table representation and equivalence checking to support
large functions (n>20) as well as constant and garbage lines and quantum gates
• A better optimization tool
• A better compact form representation

• An interactive user interface to draw circuit manually


• Supporting macros to define subcircuits
• Supporting various cost models in this survey.
Version History:
• 1.0: Support Toffoli gates with positive and negative controls, bitmap files for image saving
and quantum cost calculation.
• 1.1: Support Fredkin gates with both positive and negative controls.
• 1.11: quantum cost calculation was updated for Peres and Fredkin gates.

• 1.22: tfc parser was updated to support all tfc options (e.g. comments, .i, .o, .c). In-
put/output labels were displayed.
• 1.42: An optimization tool was added to RCViewer+ based on the result of this paper.
Using this tool, researchers can see the effect of negative controls in optimization of reversible
circuits with generalized Toffoli gates.
• 1.52: Hadamard, Controlled-V and Controlled-V+ were supported.
• 1.62: Compact form representation was supported.
• 1.82: PLA verification and truth table representation were included.

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• 1.83: Truth table representation was updated to ignore constant and garbage lines. Minor
modifications were made to improve circuit visualization.
• 1.84: Equivalence checking was included for reversible gates.

• 1.85: Peres gate was supported in input tfc. Active circuit can be exported in tfc and truth
table (text) format.
• 1.851: Minor bugs in negative controls were fixed.
• 1.861: Latex q-circuit output was supported. Compact form representation was updated.

• 1.87: Compact form representation was improved.


• 1.88 (April 07, 2011): Compact form representation was further improved. The current algo-
rithm is similar to the proposed greedy method in this paper without its template application.
Further optimization may be possible by applying the templates.

• 2.3 (July 03, 2011): Technology mapping (decomposition into 1- and 2-qubit gates) was
included. Optimization tool was further improved. Specification can be exported in truth
table (decimal) and cycle representation. Real format version 1.0 (see www.RevLib.org) for
circuit representation was supported. For this update, constants and garbage lines in real
format are ignored and all lines are considered as the main qubits.

• 2.31 (July 12, 2011): A few bugs in the optimization tool and circuit representation were
fixed.
• 2.41 (December 3, 2011): A new cost model based on the result of this paper was added.
A few revisions were applied to improve runtime. A new feature was included to reverse a
given circuit.

• 2.42 (February 2, 2013): A bug in the compact form representation for SWAP gate was fixed.
• 2.43 (April 6, 2013): A problem in Win XP was fixed. Thanks to Dr. Ahmed Younes for his
comment.
• 2.5 (May 7, 2013): T , T † , S gates were supported. Toffoli decomposition into Clifford+T
gates based on Figure 4.9 of the book by Nielsen & Chuang was added. Thanks to Maryam
Yazdani for an initial version of the code.
——————————————————————————————————————————–
Acknowledgment:

The authors acknowledge Dr. Dmitri Maslov for his very helpful comments.
Suggestions are welcome.
——————————————————————————————————————————–
If you use RCViewer+ in your research article, please refer/acknowledge in the fol-
lowing way:
Mona Arabzadeh, Mehdi Saeedi, RCViewer+, version ≺number, ≺year, available at
http://ceit.aut.ac.ir/QDA/RCV.htm
——————————————————————————————————————————–

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A complete example:
.v a,b,c,d,e,f
.i a,b,c,d,e
.o f
.c 0

BEGIN

T1 c
T1 d
T2 d’,b
T3 a’,c,b
T2 a,c
T2 b,e
f3 a’,b,c
ha
V b,c
p3 a,c,e
T3 b,e,f
T2 c’,e
T2 a,c
V+ d,f
f5 a’,b,c,e,f
T6 a’,b,c’,d,e,f
Hd

END

Figure 1: Standard form

4
Figure 2: Compact form

Figure 3: Decomposed circuit (into Toffoli, w/o optimization)

5
Figure 4: Decomposed circuit (into 1- and 2-qubit gates, w/o optimization)

6
Figure 5: Decomposed circuit (into Clifford+T gates, w/o optimization)

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