Computer Architecture - - Unit 11 - Week 10 - Pr... https://onlinecourses.nptel.ac.in/noc18_cs29/uni...
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Unit 11 - Week
10 - Principles of Pipelining
Course
outline
Assignment 10
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the portal assignment.
Week 1 - 1) How many latches are required in an n-stage pipelined processor. 1 point
Introduction &
Language of Bits n
Week 2 - n-1
Assembly
2n
Language
n/2
Week 3 -
Assembly No, the answer is incorrect.
Language Score: 0
Accepted Answers:
Week 4 - ARM &
n-1
x86 Assembly
Language 2) When multiple instructions are processed simultaneously during the execution of a 1 point
program, this is called
Week 5 - x86
Assembly
Multitasking
Language
Multiprogramming
Week 6 - A
Primer on Digital Hardwired control
Logic
Pipelining
Week 7 - No, the answer is incorrect.
Computer Score: 0
Arithmetic
Accepted Answers:
Week 8 - Pipelining
Computer
3) An instruction pipeline can be implemented using a: 1 point
Arithmetic
Week 9 - LIFO buffer
Processor
FIFO buffer
Design
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Week of
A project 10 - In association with
Principles of None of the above
Pipelining
No, the answer is incorrect.
Principles of Score: 0
Funded by
Pipelining Part-I Accepted Answers:
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Computer Architecture - - Unit 11 - Week 10 - Pr... https://onlinecourses.nptel.ac.in/noc18_cs29/uni...
Principles of FIFO buffer Powered by
Pipelining
Part-II 4) Which of the following is not a pipeline stage? 1 point
Quiz : Operand fetch
Assignment 10
Execute
Week 11 -
Principles of Pipeline flush
Pipelining
Memory Access
Week 12 - The No, the answer is incorrect.
Memory Score: 0
Systems
Accepted Answers:
TRANSCRIPTS Pipeline flush
5) The following code snippet wil have which hazard? 1 point
add r1, r2, r3
sub r3, r1, r4
RAW hazard
WAW hazard
WAR hazard
NO hazard
No, the answer is incorrect.
Score: 0
Accepted Answers:
RAW hazard
6) The notion of stopping a pipeline stage from accepting and processing new data is called 1 point
Pipeline pre-processing
Pipeline flush
Pipeline interlock
None of the above
No, the answer is incorrect.
Score: 0
Accepted Answers:
Pipeline interlock
7) Pipelining increases CPU instruction ___________ 1 point
Size
Throughput
Cycle rate
Complexity
No, the answer is incorrect.
Score: 0
Accepted Answers:
Throughput
8) Forwarding allows us to avoid costly pipeline interlocks. True or False? 1 point
True
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Computer Architecture - - Unit 11 - Week 10 - Pr... https://onlinecourses.nptel.ac.in/noc18_cs29/uni...
False
No, the answer is incorrect.
Score: 0
Accepted Answers:
True
9) A branch instruction is known as a _________ if the processor assumes that all the 1 point
succceeding instructions that are fetched before its outcome has been determined, are on the correct
path.
Taken branch
Frozen branch
Delayed branch
None of the above
No, the answer is incorrect.
Score: 0
Accepted Answers:
Delayed branch
10)If some combination of instructions cannot be accommodated because of resource 1 point
conflicts, the processor is said to have a
Data hazard
Structural hazard
Pipeline hazard
Stall
No, the answer is incorrect.
Score: 0
Accepted Answers:
Structural hazard
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