Smart Octal Low-Side Switch: Logic
Smart Octal Low-Side Switch: Logic
Smart Octal Low-Side Switch: Logic
Application
• µC Compatible Power Switch for 12 V and 24V Applications
• Switch for Automotive and Industrial Systems
• Solenoids, Relays and Resistive Loads P-DSO 36-12
• Robotic Controls Ordering Code:
Q67006-A9329
General description
Octal Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and
eight open drain DMOS output stages. The TLE 6230 GP is protected by embedded protection func-
tions and designed for automotive and industrial applications. The output stages are controlled via an
SPI Interface. Additionally four channels can be controlled direct in parallel for PWM applications.
Therefore the TLE 6230 GP is particularly suitable for engine management and powertrain systems.
Block Diagram
VBB
IN1 Protection
Functions
IN2 as Ch. 1 LOGIC
IN3 as Ch. 1
OUT1
Output Stage
IN4 as Ch. 1
16 1 4
SCLK 8 8
Output Control
SI Serial Interface
SPI Buffer OUT8
CS
SO
GND
RESET FAULT VS
Channel 1
Normal function
GND VS SCB/Overload
PRG
Open load
short to ground
IN1
&
Output Stage
OUT1
IN2 OUT2
& Channel 2
IN3
& Channel 3 OUT3
IN4
& Channel 4 OUT4
Channel 5 OUT5
SO Channel 6 OUT6
SPI
SI Interface
16 bit Channel 7 OUT7
SCLK
Channel 8 OUT8
CS
GND
1)
RI=internal resistance of the load dump test pulse generator LD200
2)
VLoadDump is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839.
3)
Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output cur-
rent has to be calculated using RthJA according mounting conditions.
Electrical Characteristics
Parameter and Conditions Symbol Values Unit
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H min typ max
(unless otherwise specified)
2. Power Outputs
ON Resistance VS = 5 V; ID = 500 mA TJ = 25°C RDS(ON) -- 0.8 1 Ω
TJ = 150°C -- -- 1.7
Output Clamping Voltage Output OFF VDS(AZ) 40 -- 55 V
Current Limit ID(lim) 1 1.5 2 A
3. Digital Inputs
Input Low Voltage VINL - 0.3 -- 1.0 V
Input High Voltage VINH 2.0 -- -- V
Input Voltage Hysteresis VINHys 50 100 200 mV
Input Pull Down/Up Current (IN1 ... IN4) IIN(1..4) 20 50 100 µA
PRG, Reset Pull Up Current IIN(PRG,Res) 20 50 100 µA
Input Pull Down Current (SI, SCLK) IIN(SI,SCLK) 10 20 50 µA
Input Pull Up Current ( CS ) IIN(CS) 10 20 50 µA
4
For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched
off. This undervoltage reset gets active at VS = 3V (typ. value) and is guaranteed by design.
5
For Reset = H.
5. Diagnostic Functions
Open Load Detection Voltage VDS(OL) VS -2.5 VS -2 VS -1.3 V
Output Pull Down Current IPD(OL) 50 90 150 µA
Fault Delay Time td(fault) 50 100 200 µs
Short to Ground Detection Voltage VDS(SHG) VS –3.3 VS -2.9 VS -2.5 V
Short to Ground Detection Current ISHG -50 -100 -150 µA
Current Limitation; Overload Threshold Current ID(lim) 1...8 1 1.5 2 A
6
Overtemperature Shutdown Threshold Tth(sd) 170 -- 200 °C
Hysteresis6 Thys -- 10 -- K
6. SPI-Timing
Serial Clock Frequency (depending on SO load) fSCK DC -- 5 MHz
Serial Clock Period (1/fclk) tp(SCK) 200 -- -- ns
Serial Clock High Time tSCKH 50 -- -- ns
Serial Clock Low Time tSCKL 50 -- -- ns
Enable Lead Time (falling edge of CS to rising edge of tlead 250 -- -- ns
CLK)
Enable Lag Time (falling edge of CLK to rising edge of CS ) tlag 250 --- -- ns
Data Setup Time (required time SI to falling of CLK) tSU 20 -- -- ns
Data Hold Time (falling edge of CLK to SI) tH 20 -- -- ns
6
Disable Time @ CL = 50 pF tDIS -- -- 150 ns
7
Transfer Delay Time tdt 200 -- -- ns
( CS high time between two accesses)
Data Valid Time CL = 50 pF6 tvalid -- 110 160 ns
CL = 100 pF6 -- 120 170
CL = 220 pF6 -- 150 200
6
This parameter will not be tested but guaranteed by design
7
This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay
time has to be extended to the maximum fault delay time td(fault)max = 200µs.
Functional Description
The TLE 6230 GP is an octal-low-side power switch which provides a serial peripheral inter-
face (SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power
transistors are protected against short to VBB, overload, overtemperature and against over-
voltage by an active zener clamp.
The diagnostic logic recognizes a fault condition which can be read out via the serial diagnos-
tic output (SO).
Circuit Description
Output Stage Control
Each output is independently controlled by an output latch and a common reset line, which
disables all eight outputs. Serial data input (SI) is read on the falling edge of the serial clock. A
logic high input data bit turns the respective output channel ON, a logic low data bit turns it
OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition
of CS transfers the serial data input bits to the output buffer.
PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 4 are high active
PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active.
If the parallel input pins are not connected (independent of high or low activity) it is guaranteed
that the channels 1 to 4 are switched OFF.
PRG pin itself is internally pulled up when it is not connected.
Each of the eight output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 1 A. The continuous current for each channel is 500 mA
(all channels ON).
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protection
level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shut-
down with restart) to prevent critical chip temperatures.
CS - Chip Select. The system microcontroller selects the TLE 6230 GP by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition: - diagnostic status information is transferred from the power
outputs into the shift register.
- serial input data can be clocked in from then on
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits
CS Low to High transition: - transfer of SI bits from shift register into output buffers
- reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS . When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6230 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select CS makes any transition. The number of clock pulses will be counted during a
chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were
counted during CS is active.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-
mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of two bytes - a "control byte” followed by a "data byte". The control
byte contains the information as to whether the data byte will be accepted or ignored (see di-
agnostics section). The data byte contains the input information for the eight channels. A logic
8)
The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or perma-
nently
high level at this pin (within the data byte) will switch on the power switch, provided that the
corresponding parallel input is also switched on (AND-operation for channel 1 to 4).
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
Diagnostics
FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transi-
tion as soon as an error occurs for any one of the eight channels. This fault indication can be
used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called
after this fault indication. This saves processor time compared to a cyclic reading of the SO
information.
As soon as a fault occurs, the fault information is latched into the diagnosis register. A new
error will over-write the old error report. Serial data out pin (SO) is in a high impedance state
when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially.
The rising edge of CS will reset all error registers.
HH Normal function
HL Overload, Shorted Load or Overtemperature
LH Open Load
LL Shorted to Ground
Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal
function.
Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current
limitation gets active, i.e. there is a overload, short to supply or overtemperature condition.
Open load: An open load condition is detected when the drain voltage decreases below 3 V
(typ.). LH bit combination is set.
Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current
exceeds 100 µA, short to ground is detected and the LL bit combination is set.
A definite distinction between open load and short to ground is guaranteed by design.
Control byte is set to FFhex: Data byte will be accepted. The outputs will be switched ON or
OFF according to the information of the data byte and the parallel inputs (Channel 1 to 4 be-
cause of AND operation).
All other control words except the one for 'Diagnosis Only = 00hex' will also be accepted as a
valid control word and the data will be accepted.
Example: HLLHLHLH DDDDDDDD: Outputs will switch according to the data bits.
b) Diagnosis Only
Control byte is set to 00hex: Data byte will be ignored. Diagnostic information can be read out
at any time with no change of the switching conditions. Only 00hex means 'Diagnosis Only'.
Timing Diagrams
CS
SCLK
SI C O N T R O L Byte 7 6 5 4 3 2 1 0
MSB LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO
tlag
tSCKH
tlead 0.7VS
SCLK 0.2VS
tSCKL
tSU
tH
0.7VS
SI
0.2VS
0.7 VS CS
SCLK 0.2 VS
tvalid
tDis
SO 0.7 VS SO
0.2 VS
SO
0.7 VS
0.2 VS
Figure 4:
SO Valid Time Waveforms Enable and Disable Time Waveforms
VIN
tON tOFF
VDS
80%
20%
t
Application Circuits
VBB
VS = 5V C
10k
VS
PRG
OUT1
FAULT OUT2
RESET
IN1
µC IN2
e.g. C167 IN3 TLE
IN4
6230 GP
MTSR SI
MRST SO OUT8
CLK CLK
P xy CS
GND
Drain-Source on-resistance
RDS(ON) = f (Tj) ; Vs = 5V
1,4
1,3
1,2
RDS(ON) [Ohm]
1,1
1
0,9
0,8
0,7
0,6
0,5
0,4
-50 -25 0 25 50 75 100 125 150 175
Tj[°C]
44
VDS(AZ) [V]
43
42
41
-50 -25 0 25 50 75 100 125 150 175
Tj[°C]
250
200
150
100
50
0
0 0,2 0,4 0,6 0,8 1 1,2 1,4
Peak current [A]
Injector 1
Engine Management
P x.1-4
4
4 PW M
Application
Channels Injector 2 TLE 6230 GP in combination
with TLE 6240 GP (16-fold
MTSR SI
TLE
Injector 3 switch) for relays and general
MRST SO
CLK 6220 GP purpose loads and TLE 6220
CLK Injector 4
P x.y CS
CS
Quad GP (quad switch) to drive the
injector valves. This arrange-
4 ment covers the numerous
P x.1-4 4 PW M
Channels loads to be driven in a modern
µC Engine Manage-
SI ment/Powertrain system. From
TLE
SO 28 channels in sum 16 can be
C167 6230 GP
P x.y
CLK
CS Octal controlled direct in parallel for
PWM applications.
8
P x.1-8 8 PW M
Channels
SI
SO TLE
CLK 6240 GP
P x.y CS 16-fold
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