10bit SAR ADC
10bit SAR ADC
10bit SAR ADC
Abstract
This paper presents two low power design techniques used for successive approximation registers (SAR) analog-to-digital
converter (ADC) for transmission of Physiological signal: Dual split switching; set and reset phase. Dual split switching
is used in one sided charge scaling digital-to-analog converter (DAC) to edge of the switching energy by reducing the
leakage in dual transmission gate. The set and reset phase defines the amplification and comparison phase of the com-
parator. The delay time of the comparator is profoundly reduced with folded cascoded pre amplifier and a regenerative
latch. A Serial In Parallel Out (SIPO) N bit register and SAR are designed with negative edge triggered D Flip-Flop (DFF).
For power optimization the supply voltage of SAR ADC is designed with 500 mV. The Variable threshold concept has
been utilized in the entire design to operate the SOC with 500 mV supply voltage. The designed SAR ADC is capable of
supporting the sampling rate of 1 Msps. The circuit is designed using standard UMC 180 nm technology. The simulation
results show that the power consumption of the SAR ADC is 13.99 μW and achieved 68.54 dB SFDR with ENOB value 7.69
bits. The DNL (max) is + 0.9/− 0.82 LSB and INL 1.06/− 1.31 LSB.
Keywords Low power · Dual split switching · Physiological signals · SAR ADC · Variable threshold · Negative edge
triggered DFF
* Kiran Kumar Mandrumaka, kirankumarece@cvsr.ac.in; Fazal Noorbasha, fazalnoorbasha01@gmail.com | 1Department of ECE, Koneru
Lakshmaiah Education Foundation, Vaddeswaram, Guntur, A.P., India.
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i=N-1
2 SAR architecture No
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detailed design process of all the blocks are explained in signal exhibits logic high means level 1 and Vin < Vref the
the next sections. output signal exhibits logic low means level 0.
gm2
Adm = (1)
gds2 + gds6
3 Design details of SAR ADC
The preamplifier is a single stage operational trans con-
3.1 Comparator ductance amplifier (OTA) [32] as shown in Fig. 3. The cur-
rent scaling technique is implemented by the transistors
The low power regenerative comparator circuit is the M5–M6 with higher widths. Transistors Mb1, Mb2, Mb3
essential block in the ADC and many electronic devices. form a current mirror which delivers the differential cur-
The main goal is to design a high speed and low power rents. These differential currents are feed to output stage,
preamplifier regenerative comparator circuit [28, 29]. for voltage to current conversion. Transistors M1 to M6 are
Figure 3 shows the schematic of proposed preamplifier operated in weak inversion region with appropriate W/L
regenerative comparator circuit. The operation of the com- ratio. The drain to source current IDS (2) in weak inversion
parator is divided into pre-amp phase (reset) stage and region depends on reverse saturation current IS, T is the
dynamic comparison phase (set) stage with additional low ambient temperature, n is the inclination of the curve in
on resistance switches S1 and S2 with non-overlapping weak inversion, K is the Boltzmann constant, q the charge
clock signals as shown in Fig. 3. During the reset phase of the electron or hole. The total power consumption of
switch S1 will be open and S2 will be closed then the sin- the comparator is 1.8 μW with 500 mV rail to rail supply
gle stage folded amplifier, amplifies the voltage difference voltage.
between the two input signals with voltage gain 40.4 dB ( )[ ( )]
W
( ) VGS − Vth VDS
(1). During the set phase S1 will close and S2 opens dur- IDS = IS exp q 1 − exp −q (2)
ing the time regenerative comparator circuit compares L nKT KT
between two input signals during the opted sampling Current scaling is achieved by increasing the output
intervals. Because of this set and reset phases the nonlin- impedances and thereby ensuring current scaling. The
ear error and offset error at comparator are reduced during source degenerated current mirrors are formed by transis-
analog to digital conversion. When Vin > Vref the output tors Mc1, M5 and M6, set the currents in the regenerative
Substrate
Bias
Control
Mb3 Mb2 Mb1 Comp+
-
V+ V-
IB M1 M2
S1
S1
M3 M4
Vo - S2 S2
Vo +
M5 M6
CLK_B Mc1
Vi V0
CLK
PMOS NMOS
Fig. 3 Proposed schematic of the preamplifier regenerative comparator circuit with low on-resistance transmission gate based switches
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circuit (the difference between the currents in M3–M4 of the transmission gate is reduced while connecting one
and M5–M6). In order to save the power, the bias circuit low W: L ratio pMOS transistor with high W:L ratio pMOS
is designed in such a way that the currents of transistors transistor and similarly for nMOS transistor.
in the regenerative circuit are only a small portion of the
input pair. The current scaling ratio between Mb1 and Mb2 3.2 Sample and hold
is 7:1(2ID/14). The currents in the regenerative transistors
are ID/7; this is 1/3rd of the differential input pair current. A simple sample and hold circuit is designed with CMOS
Using the bias circuit formed by Mb2 and Mc1, we set the Transmission gate and a sampling capacitor. To avoid
current in the M5 and M6 to be 8ID/7 [31] (Table 1). charge injection error, a dummy switch is arranged as
The Transmission gate based switch is used for switch- shown in the Fig. 4. The dummy switch is driven by an
ing between set and reset operations, but to avoid glitches inverted clock which absorbs the charge injection from
during switching and without voltage drops while passing sampling switch. The unwanted glitches are also elimi-
through the channel, on-resistance should be reduced. The nated by using this dummy switch. The minimization of
parallel combination of one low and high on-resistance of DNL and INL for better ADC design can be possible by
the transistors results low on-resistance. So on-resistance connecting a buffer at the end of the sample and hold
circuit.
Table 1 Design summary of pre-amplifier
3.3 Digital to analog converter (DAC)
Devices W (μm)/L (nm) ID (nA) Operating region
M1:M2 20/180 393 Sub threshold A 10 bit charge scaling capacitive DAC is designed with a
M3:M4 50/180 393 Sub threshold combination of two 5 bit charge scaling sub-DACs with a
M5:M6 10.02/200 505 Sub threshold scaling capacitor Cs as shown in the Fig. 5. The operation of
CLK_B CLK
Vin Vout
CLK CLK_B
(a) (b)
Fig. 4 a Sample and hold circuit with dummy switch. b Simulation result with sampling rate 5 Ksps
VSample
`
CS +
Comparator Vout
-
C C 2C 4C 8C 16C C 2C 4C 8C 16C
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Case: 1000000000 Case: 1100000000 Case: 1110000000 Case: 0111000000 Case: 0011100000
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CLK_B
CLK_B switch between amplifier and comparator. The primary
element used in the dual splitting design is a trans-
D Q
mission gate [34]. In the proposed transmission gate,
CLK another set of NMOS and PMOS transistors are connected
CLK
in parallel, so that the on resistance and sampling distor-
CLK CLK tion are maintained as low as possible. The length and
widths are in 2:1 ratio. As mentioned in previous section
transmission gate is operated with VTCMOS technique
CLK_B CLK_B
refer Fig. 10.
V0
CLK
V2b
R1
R2
Vin Out Vref
V1b
R3
R4
CLK_B
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109
145
181
217
253
289
325
361
397
433
469
505
541
577
613
649
685
721
757
793
829
865
901
937
973
1009
1
37
73
-0.5
-1
-1.5
Fig. 12 Simulated INL 2
INL=1.06/-1.31LSB
1
0 LSB
491
701
106
141
176
211
246
281
316
351
386
421
456
526
561
596
631
666
736
771
806
841
876
911
946
981
1
36
71
1016
-1
-2
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Fig. 16 Simulated FFT for a 100 Hz sine wave with sampling rate 6 Conclusion
1 MS/s
A 10 bit SAR ADC with a 100 mV Vref input range using
Table 2 Key parameters of proposed SAR ADC dual split switching network in DAC is presented. A regen-
erative comparator operating in the sub threshold region
Architecture SAR
with low offset is used, along with low power SAR logic
VDD (V) 0.5 with negative edge triggered flip-flop at a 500 mV supply
Power dissipation (μW) 13.99 μW voltage. The proposed ADC consumes 13.99 μW power.
Technology (nm) 180 The ENOB around 7.69 bits.
Resolution (bits) 10
Fsample Up to 1 Msps Acknowledgements The authors are highly thankful to the Chairman
of ANURAG group of institutions Dr. P. Rajeshwar Reddy M. L. C for
DNL (max) + 0.9/− 0.82 LSB his constant encouragement and also providing all the necessary
INL 1.06/− 1.31 LSB resources to carry out this work. They are also thankful to Dr. K. S. R.
SFDR (dB) 68.54 Krishna Prasad, Professor, NIT, Warangal and Dr. K. S. Rao, Director,
SINDR (dB) 61.96 Anurag Group of Institutions for their valuable suggestions during
this work. The authors deeply express their gratitude Department
ENOB 7.69 of ECE, K L. University.
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