AY2018-19 Course Listing
AY2018-19 Course Listing
Features Applications
Spread spectrum for EMI reduction Surveillance camera
Wide spread % option IP camera
Center spread: from ±0.125% to ±2%, ±0.125% step size Industrial motors
Down spread: -0.25% to -4% with -0.25% step size Flat panels
Spread profile option: Triangular, Hershey-kiss Multi function printers
Programmable rise/fall time for EMI reduction: 8 options, PCI express
0.25 to 40 ns
Any frequency between 1 MHz and 141 MHz accurate to
6 decimal places
100% pin-to-pin drop-in replacement to quartz-based XO’s
Excellent total frequency stability as low as ±20 ppm
Operating temperature from -40°C to 85°C.
Low power consumption of 4.0 mA typical at 1.8V
Pin1 modes: Standby, output enable, or spread disable
Fast startup time of 5 ms
LVCMOS output
Industry-standard packages
QFN: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5 mm2
Contact SiTime for SOT23-5 (2.9 x 2.8 mm2)
RoHS and REACH compliant, Pb-free, Halogen-free
and Antimony-free
Electrical Specifications
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated.
Typical values are at 25°C and 3.3V supply voltage.
Parameters Symbol Min. Typ. Max. Unit Condition
Frequency Range
Output Frequency Range f 1 – 141 MHz
Notes:
1. In both center spread and down spread modes, modulation rate
is employed with a frequency of ~31.25 kHz.
2. Contact SiTime for wider spread options
Notes:
3. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.
4. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Note:
5. Exceeding this temperature for extended period of time may damage the device.
Note:
6. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Timing Diagrams
Vdd Vdd
90% Vdd
50% Vdd
CLK Output
CLK Output HZ
HZ
T_resume: Time to resume from ST
T_start: Time to start from power-off
Vdd Vdd
50% Vdd
OE Voltage
T_oe 50% Vdd
OE Voltage
T_oe
CLK Output CLK Output
HZ HZ
T_oe: Time to re-enable the clock output T_oe: Time to put the output in High Z mode
Figure 4. OE Enable Timing (OE Mode Only) Figure 5. OE Disable Timing (OE Mode Only)
Vdd
50% Vdd Vdd
SD Voltage
50% Vdd
SD Voltage
T_sde
T_sdde
Deviation (%)
Frequency
Deviation (%)
Frequency
Figure 6. SD Enable Timing (SD Mode Only) Figure 7. SD Diable Timing (SD Mode Only)
Note:
7. SiT9005 has “no runt” pulses and “no glitch” output during startup or resume.
Table 10. Vdd = 2.8V Rise/Fall Times Table 11. Vdd = 3.0V Rise/Fall Times
for Specific CLOAD for Specific CLOAD
Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF
L 3.77 7.54 12.28 19.57 25.27 L 3.60 7.21 11.97 18.74 24.30
A 1.94 3.90 7.03 10.24 13.34 A 1.84 3.71 6.72 9.86 12.68
R 1.29 2.57 4.72 7.01 9.06 R 1.22 2.46 4.54 6.76 8.62
B 0.97 2.00 3.54 5.43 6.93 B 0.89 1.92 3.39 5.20 6.64
T 0.55 1.12 2.08 3.22 4.08 T or "‐": default 0.51 1.00 1.97 3.07 3.90
E or "‐": default 0.44 1.00 1.83 2.82 3.67 E 0.38 0.92 1.72 2.71 3.51
U 0.34 0.88 1.64 2.52 3.30 U 0.30 0.83 1.55 2.40 3.13
F 0.29 0.81 1.48 2.29 2.99 F 0.27 0.76 1.39 2.16 2.85
YXXXX
1.5
0.5
#1 #2 #2 #1
1.0
0.75
0.75 ± 0.05
1.1
0.9
1.9
YXXXX
0.7
#1 #2 #2 #1
1.2
0.9
0.75 ± 0.05
1.4
Notes:
8. Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the
device.
9. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Ordering Information
The Part No. Guide is for reference only.
To customize and build an exact part number, use the SiTime Part Number Generator.
Note:
10. Contact SiTime for SOT23 (2.9 x 2.8 mm2) package
SiTime Corporation, 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | Phone: +1-408-328-4400 | Fax: +1-408-328-4439
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