COURSE PLAN

Department: ECE

Staff Name:
COURSE TITLE LOGIC DESIGN LAB
COURSE CODE 10ESL38
NAME OF DEPARTMENT ECE
PROGRAM NAME B.E.
SEMESTER Third
SECTION
LECTURE HOURS 0
TUTORIAL HOURS 0
PRACTICAL HOURS 3x14 ~ 42
CREDITS (L-T-P: Total) 0:0:3
PREREQUISITES Basic Electronics; Logic Design

COURSE DESCRIPTION

The Lab is designed to give students a practical idea of how to use the knowledge acquired
in the theory subject dealing with Boolean algebra and logic design. The students get a
hands on experience how logic gates operate in practice and how the circuits designed
using theoretical techniques of minimization like K-Maps and QMC method etc work
practically.

They design and implement increasing complex circuits in combinational domain starting
with implementation of a simple Boolean function and move on to half adders, full adders,
corresponding subtracters. From this foundation the move on to parallel binary adders with
carry propagation. Then they design encoders, decoders, and design of Boolean functions
using these, and also code converters. They continue the same to multiplexers and
demultiplexers.

The subject moves smoothly from the concept of combinational to sequential logic with a
basic study of memory elements called flip flops. Using various flip flops shift registers are
constructed and operation in various modes is verified practically. Then asynchronous and
synchronous counter circuits are made with flip flops, followed by counter special IC chips.
COURSE OUTCOMES

At the end of this course the students should be able to use discrete components to test and verify
the logic gates.

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1. Simplify and realize Boolean expressions using logic gates/Universal gates.

2. Realize Half/Full adder and Half/Full Subtractors using logic

3. Realize (i) parallel adder/Subtractors using 7483 chip ; (ii) BCD to Excess-3 code conversion and vice
versa.

4. Realize Binary to Gray code conversion and vice versa

5.Be able to use MUX/DEMUX – use of 74153, 74139 for arithmetic circuits and code converter.

6. Realize One/Two bit comparator and study of 7485 magnitude

7. Use a) Decoder chip to drive LED display and b) Priority encoder.

8. Verify the Truth table of Flip-Flops: (i) JK Master slave (ii) T type and

9. Realize 3 bit counters as a sequential circuit and MOD – N counter design (7476, 7490, 74192,
74193).

10. Perform Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95.

11. Wire and test Ring counter/Johnson counter.

12. Wire and test Sequence generator.



COURSE OBJECTIVES

Course objectives from teaching perspective (what do you want to teach to achieve outcomes).
 Explain the working of the logic gate IC chips and their biasing, with pin details and
connections. Verify that the students are able to test the connectivity and continuity; and
make proper connections to get relevant outputs.
 Provide the theoretical design of half and full adders and subtractors with Boolean gates.
Illustrate how the circuit is implemented with the gates handled in the previous experiment.
 Explain the internal working and external pins of 7483 (parallel adder) and demonstrate the
working with 2 or 3 examples of addition and subtraction. Show how this can be used as a +3
or -3 circuit for getting BCD to X3 and vice versa conversion.
 Explain the theory and utility of various codes including binary and gray. Illustrate the
development and implementation of converters from one to another with XOR gates.
 Describe the working of a MUX and its operation. Illustrate its application for arithmetic circuits
 and converter.
 Explain comparator – 1 and 2 bit operation. Stress the importance of comparing MSB first and
LSB later. Illustrate the design and implementation of the comparator.
 Explain how binary value is decoded to run LED display. Use the code conversion concept to
display various digits.
 Explain the working, pinouts and biasing connections of various Flip Flop IC chips and
demonstrate the connection and use of the same.
 Explain counter design and guide through various kind of counter design and implementation
experiments.
 Design Registers using both basic flip flops and also 7495 chip. Guide students to verify
various modes of operation.
 Illustrate the working of ring and johnsons counter with register chip, and guide the students
to verify the circuit designed.
 Explain random sequence generation and make the students design and verify the circuit for a
particular given sequence.

SYLLABUS

UNIT NO. TOPICS/CONTENTS L T P

HOURS HOURS HOURS
1. Simplification, realization of Boolean expressions using logic 0 0 3
gates/Universal gates.
2. Realization of Half/Full adder and Half/Full Subtractors using 0 0 3
logic
3. (i) Realization of parallel adder/Subtractors using 7483 chip 0 0 3
(ii) BCD to Excess-3 code conversion and vice versa.
4. Realization of Binary to Gray code conversion and vice versa 0 0 3
5. MUX/DEMUX – use of 74153, 74139 for arithmetic circuits 0 0 3
and code
6. Realization of One/Two bit comparator and study of 7485 0 0 3
magnitude comparator
7. Use of a) Decoder chip to drive LED display and b) Priority 0 0 3
encoder.
8. Truth table verification of Flip-Flops: (i) JK Master slave (ii) T 0 0 3
type
9. Realization of 3 bit counters as a sequential circuit and MOD 0 0 3
– N counter design (7476, 7490, 74192, 74193).
10. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 0 0 3
74S95.
11. Wiring and testing Ring counter/Johnson counter. 0 0 3
12. Wiring and testing of Sequence generator. 0 0 3

REFERENCES

S.NO PARTICULARS OF BOOKS/ARTICLES

1. Datasheets
2. Lab Manual

UNIT/TOPIC WISE OUTCOMES MAPPING WITH ABET A-K COMPETENCIES

UNIT OUTCOMES TEACHING/LEARNIN ASSESMENT ABET /PEO

NO./TOPIC G STRATEGIES STRATEGY AND MAPPING
TOOLS a b c d e f g h i j k
Realization Implementation Providing the circuit, Circuit execution, Viva, √
of gate and explanation, illustration, observation record
of Boolean minimization of guidance.
expression. function
practice
Half/Full Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
adder and of Adder and guidance.
Subtractor subtractor
using logic
(i) Parallel Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
adder/Subt of parallel adder guidance.
ractors and subtractor
using 7483
(ii) BCD to
Excess-3
code
conversion
and vice
versa.
Binary to Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
Gray code of Code guidance.
conversion converters
and vice
versa
MUX/DEM Designing and Providing the circuit, Circuit execution, Viva, √ √
implementation explanation, illustration, observation record
UX – use of of arithmetic guidance.
74153, circuits and
74139 for code converters
arithmetic with mux and
demux ICs
circuits and
code
Realization Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
of of comparators guidance.
One/Two
bit
comparato
r and study
of 7485
magnitude
comparatr
Use of a) Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
Decoder of LSD display guidance.
chip to using decoder
drive LED IC
display and
b) Priority
encoder.
Truth table Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
verification of Flip Flops guidance.
of Flip- using gates and
Flops: (i) JK flip flop IC
Master chips
slave (ii) T
type
Realization Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
of 3 bit of 3 bit counters guidance.
counters as (synchronous
sequential and
circuit and asynchronous)
MOD – N
counter
design
(7476,
7490,
74192,
74193).
Shift left; Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
Shift right, of registers guidance.
SIPO, SISO,
PISO, PIPO
operations
using
74S95.
Wiring and Designing and Providing the circuit, Circuit execution, Viva, √ √
implementation explanation, illustration, observation record
testing of ring and guidance.
Ring Johnson ring
counter/Jo counters
hnson
counter.
Wiring and Designing and Providing the circuit, Circuit execution, Viva, √
implementation explanation, illustration, observation record
testing of of sequence guidance.
Sequence generators
generator.

LECTURE/TUTORIAL PLAN (BEFORE SEMSETER COMMENCEMENT AS PER TIME TABLE)

S.NO DATE TOPICS TO BE COVERED/TESTS ACTIVITY ASSESMENT Tool

 planned

LECTURE/TUTORIAL PLAN (DURING SEMSETER AS PER LECTURE/TUTORIAL TAKEN )

S.NO DATE TOPICS COVERED/TESTS ACTIVITY done ASSESMENT Tool

ASSIGNMENTS/SEMINARS

S.NO DATE OF DATE OF PARTICULARS OF ASSIGNMENT MARKS/GRADES

ANNOUNCEMENT SUBMISSION (WEIGTHAGE)

MIDTERM / CONTINUOUS ASSESMENT / FINAL TESTS

S.NO DATE OF TYPE OF SYLLABUS MARKS/GRADES EXAM HOURS NUMBER OF

TEST TEST TOPICS/UNITS WEIGTHAGE QUESTIONS

SAMPLE QUESTIONS ON EACH UNIT (COVERING BLOOMS TAXONOMY, ALL 6 LEVELS)

SAMPLE QUESTIONS (ONE QUESTION ON EACH LEVEL OF BLOOMS TAXONOMY

1. Verify the truth table of NAND, AND, NOR, OR, NOT and XOR gates
using IC chips.
2. Minimize the given Canonical SOP expression and implement using (A)
NAND-NAND and (B)AND-OR logic
3. Minimize the given Canonical POS expression and implement using (A)
NOR-NOR and (B)OR-AND logic
4. Write the truth tables of half and full adders and design and implement
circuits using (a) Basic and XOR gates (b) NAND gates (c) NOR Gates
5. Write the truth tables of half and full Substractor and design and
implement circuits using (a) Basic and XOR (b) NAND (c) NOR Gates
6. Verification of De Morgans theorem and implementation of all basic
gates from (a) NAND (b)NOR universal gates.
7. Design and implement Parallel adder and subtractor using 7483 IC.
8. Design and implement BCD to X3 and vice versa using 7483 IC.
9. Design and implement Binary to gray and vice versa using XOR
10. Design and implement Full and half adder/ subtractor using MUX
11. Design and implement Code converter using MUX
12. Design and implement Logic function using Demux
13. Design and implement 1 and 2 bit comparator with gates
14. Implement a 4 bit comparator using 7485 IC
15. Display Decimal digits for binary codes usind LED display.
16. Verify operation of priority encoder
17. Design and implement all flip flops using gates and verify truth tables.
18. Verify Truth tables of flip flops using flip flop ICs.
19. Design a 3 bit synchronous (a)up counter (b) down counter (c)up down
counter using 7476
20. Design a 3 bit Asynchronous (a)up counter (b) down counter (c)up
down counter using 7476
21. Implement Mod-N counters using 7490, 74192, 74193
22. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95.

23. Design, wire and verify (a) Ring counter (b) Johnson counter
24. Design a circuit to generate a given sequence and verify it.