ASIC Technology

A Brief Introduction To The ASIC Technology

And It's Design Flow

Gerhard R. Cadek – TU-Wien, Arbeitsgruppe CAD - 22.02.2002 16:25

ASIC Design

Lecture 3: ASIC Structures & Design Flow

1. IC Manufacturing 9. IC Production Test

2. CMOS Technology 10. HW/SW Design and
3. ASIC – Structures & Design Verification
Flow 11. µP, µC, DSP
4. FPGA – Technology & 12. Comparing ASIC/FPGA vs.
Devices µP/µC
5. HDLs and Synthesis 13. Managing ASIC-Projects
6. Digital Design Methodology 14. IC Packaging and IO
7. Simulation digital 15. Future Trends
8. Simulation analog/mixed

2
Contents

9 We will examine different ASIC structures and classify

them
• ASIC, Gate Array, FPGA, etc

9 We will have a closer look to the custom ICs

9 We will learn about the basic ASIC design flow

9 We will compare digital with analog design flow

3
Classification

9 There are many different possible classification

schemes
9 We will use a scheme based on the programming
technology
9 ASICs may be divided into two major classes:
– Mask Programmable ASICs (MPGAs)
Programmed during manufacturing in the fab
– User Programmable Logic Devices (UPLDs)
Programmed by the user on the desk

4
 Classification

ASIC
Application Specific Integrated Circuits

MPGA UPLD
Mask Programmable User Programmable
Gate Arrays Logic Devices

Gate Array FPGA FPIC CPLD

Field Programmable Field Programmable Complex Programmable
Sea of Gates Gate Arrays Interconnect Circuits Logic Devices
Embedded Arrays
Standard Cell Array of Logic Crossbar Multiple
Core Based Design • LUT AND/OR Matrices
• NAND
• MUX
• Wide Gates

5
Custom ICs

9 Now we will have a more closer look to the MPGAs

9 They are also called:

– Custom ICs
– ASICs

9 This is sometimes quite confusing since the term

"ASIC" is also used as a term denoting all user
specific ICs and thus including user programmable
logic devices.

6
Full Custom ICs

9 Irregular blocks

I/O pads and logic cells

irregular
array of
cells

Examples:
• processors
• memory

7
Concept of the "Gate"

9 Use a pre-defined building block - the "Gate"

9 Compose all logic functions out of this basic element

VDD rail

p-channel MOSFET

n-channel MOSFET

VSS rail

8
A Gate Configured as a NAND

9 The function is defined by two or three masks

• Typically poly silicon, metal1, metal2

VDD rail

p-channel MOSFET

a s=a&b

n-channel MOSFET
b
VSS rail

9
Gate Array

9 Array of gates surrounded by a pad ring

9 Large routing channels
• Simple one-dimensional routing
• Fixed logic/routing ratio

I/O pads

regular array of
gates with
routing channel

routing channel

10
Sea of Gate Arrays

9 Routing is performed across the gates

• Requires more metal layers
• Flexible logic/routing ratio

I/O pads

regular array of
gates without
any routing
channel

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Embedded Arrays

9 They include large compiled regular blocks

• RAM, ROM, multiplier, etc.

embedded sea of gates

optimized
core block

embedded
optimized
pad ring core block

12
Programmable Logic

9 We will have just a brief view to the programmable

logic devices

9 To compare them to custom ICs

9 FPGAs and CPLDs are that important that there is a

separate lecture covering just these devices

13
FPGA

9 FPGAs are similar to gate arrays

9 User programmable logic cells
9 Cells may be simple NANDs, MUX, or LUTs
9 Programmable interconnects
– Different levels of interconnects
• Short, medium, long, clock
– Main drawback compared to gate arrays
• System performance limited by interconnections
• Programmability requires area and introduces additional delay

14
CPLD

9 Multiple blocks of AND/OR blocks

9 PAL-like structure

15
Volumes and Complexity

Technology Volume Gates

Standard Cell > 100k 50k - 10M
Sea of Gates > 100k 30k - 5M
Embedded Array > 50k 50k - 1M
Gate Array 50k - 100k 50k - 300k
FPGA 1 - 10k 1k - 5M
CPLD 1 - 10k 400 - 100k

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Typical Costs

Technology NRE (€) €/pcs.

Standard Cell 100k - 2M smallest
Sea of Gates 30k – 200k small
Embedded Array 30k - 100k small
Gate Array 20k - 50k small
FPGA small 5 - 10k
CPLD small 1 - 100

Notice:
9 Prices are just a figure to compare the technologies.
9 Costs vary with a large number of factors.

17
Device Cost vs. Volume

9 Rule of thumb

$/chip

chips
FPGAs

Full Custom

Gate Arrays

18
Generic ASIC Design Flow

9 Now we will examine the ASIC design flow

• The road from concepts to Silicon

9 There are EDA tools that support each level of design

abstraction

9 We start first with a simple generic design flow

9 We continue discussing some design principles

9 Finally we will have a more closer look to the design

flow and the EDA tools required

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Generic ASIC Design Flow

idea

specification

system level design

system level
simulation

20
Generic ASIC Design Flow

circuit architecture design

architecture
simulation

synthesizeable netlist
register transfer level (RTL)

21
Generic ASIC Design Flow

circuit design

pre-layout
simulation

gate level netlist

pre-layout

22
Generic ASIC Design Flow

physical design

post-layout
simulation

gate level netlist

post-layout

23
Generic ASIC Design Flow

production test generation

production test
simulation

sign-off

24
ASIC Design Flow Requirements

9 There are some basic requirements or principles for

the design flow
• They are valid for every technology like ASIC, FPGA, MCM,
PCB etc.

9 Consistency
• A consistent data base of all design related data from design
entry through verification down to production data
• Controlled access for team members

9 Automation
• Speed up the design flow by automating tasks
• Use scripting capabilities
• Use sophisticated EDA tools
• Perform each design step on highest level possible

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ASIC Design Flow Requirements

9 Flexibility
• Combine tools from different vendors
• Support standardized interfaces
• Enable continuously adaptation of design methodology
• Support distributed design teams

9 Repeatability
• Every design step has to be repeatable and documented
• Basic requirement to maintain quality

9 Design iterations have to converge

• Every loop in the design flow should bring up considerably less
design rule violations
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ASIC Design Flow Requirements

9 Every design step is followed by a verification phase

• Feedback principle
• Required also for purely automated tasks since complex EDA
tools might introduce some errors

9 Embedded verification
• Every design step is accompanied by a verification
• Actually design entry requires just 20-30% of the time budget
• Rest of time is spent for verification

27
ASIC Design Flow Requirements

9 System design & verification

• Model and verify the interaction of the design and its
environment
• Model larger electronic systems including software
• Model also mechanical systems etc.

9 Just think of entering an elevator

• No one likes the idea of a blue screen or crash when pushing
the key for the first floor

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ASIC Design Flow: The Goal

9 Deal with the ever increasing complexity of the

integrated circuits
• Well known as Moore‘s law

9 Formulated by Gordon Moore in the 1960s

• Gordon Moore was a founder of Intel
• The average circuit density doubles every 18 months

9 This is the silicon industry basic economic “law”

• Although somewhat a self fulfilling prophesy
• This is now more or less valid for more than 30 years

29
ASIC Design Flow: The Goal

9 Beside the increasing complexity we have to deal with

other problems too
• Performance increases factor 10 every 8 years

• Power consumption increases factor 10 every 6 years

• Test vectors increases factor 1000 every 6 years

9 Now let’s have a look to the design flow from a more

technical point of view

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Technical Design Flow

SYSTEM DESIGN
tool/library setup system simulation

generated blocks design capture IP blocks

functional simulation
RTL DESIGN

test design synthesis floorplanning

equivalence checking static timing analysis

SYNTHESIS

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Technical Design Flow

SYNTHESIS
test simulation post synthesis simulation

PHYSICAL
placement
DESIGN

detailed routing

global routing

timing extraction

32
Technical Design Flow

PHYSICAL
DRC VERIFICATION

LVS

POST LAYOUT
test simulation post layout simulation VERIFICATION

tester rules validation static timing analysis

equivalence checking

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Design Capture

9 Tools:
– “Simple” text editor (language sensitive)
• XEmacs, WinEdit, or even Notepad or vi
– Simulator
• Modeltech: Modelsim
• Synopsys: VSS, VCS
• Cadence: Leapfrog, Verilog-XL
– Revision control system
• RCS, CVS

34
Design Capture

9 Input:
– HDL design files and testbenches
• Do it yourself
– IP blocks
• From an IP vendor
– Generated blocks, hard macros
• From the ASIC/FPGA vendor
9 Output:
• Information whether your design behaves as specified.
9 Abstraction level:
• Cycle based

35
Synthesis

9 Tools:
– Synthesis
• Synopsys: DesignCompiler
• Cadence: Ambit
– Test Synthesis
• Synopsys: TestCompiler
– Power Synthesis
• Synopsys: PowerCompiler
9 Input:
– HDL design files
– Technology library
• From ASIC vendor

36
Synthesis

– Design constraints
• Time, area, test, clock, power, hierarchical, floorplan
9 Output:
– Design database
• Different levels
– Reports
• Constraints, time, area, power
– Gate level netlist
• any HDL and EDIF
9 Abstraction level:
• Gate level
• Full gate timing, estimated routing timing

37
Test Design

9 Tools:
– Test Synthesis
• Synopsys: TestCompiler, TetraMAX
– Fault Simulation
• Synopsys: TetraMAX
• Cadence: Verifault XL
– ATPG – Automatic Test Pattern Generation
• Synopsys: TetraMAX

38
Test Design

9 Input:
– Gate level netlist
• From synthesis tools
– Technology library
• From ASIC vendor
9 Output:
– Gate level netlist with test structures inserted
• Full/partial scan test
• IDDQ test
– Production test pattern
9 Abstraction level:
• Transistor

39
Physical Design

9 Tools:
– Clock tree synthesis
– Placement
– Detailed/global routing
– Timing extraction

– There are huge design frameworks available

• Cadence
• Synopsys
• Avant!

40
Physical Design

9 Input:
– Gate level netlist from synthesis
– I/O placement (pinout)
– Constraints
• Timing, placement, routing
– Floorplan
– Clock distribution scheme
– Technology library

41
Physical Design

9 Output:
– Layout database
– Extracted timing information
• Usually SDF
– Extracted layout netlist
• Any HDL and EDIF
– Mask data
• Usually GDSII
9 Abstraction level:
• Transistor level
• Full gate and routing timing

42
Physical Verification

9 Tools:
– ERC
– DRC
– LVS

9 Input:
– Gate level netlist from synthesis
– Layout database
– Mask data

43
Physical Verification

9 Output:
– Design electrically ok
– All technology rules are ok
– Mask data is consistent with pre-layout netlist

9 Abstraction level:
• Transistor level and beyond

44
Design Flow Trends

9 Due to second order effects that have to be modeled

for nowadays DSM designs the classical design flow
changes a little bit
• Each design steps requires a lot of interaction
• E.g. synthesis and placement are no longer a separate task
but have to done in “parallel”

9 Interconnection defines the performance

• Both area and delay

45
Analog/Mixed IC Design Flow

9 Up to now we concentrated on digital ICs

• But what about analog and mixed signal ICs?
• Is there a difference in the design flow?

9 Analog design is about controlling some couple of

thousands transistors
• Instead of some 100 millions as for digital design

9 Analog design requires more detailed simulation

• There is no simple state reduction possible as done for digital
simulation
• Analog simulators like SPICE are required

46
Analog/Mixed IC Design Flow

9 Analog simulation thus requires more computing

performance
• That‘s why one is limited in the design’s complexity

9 Due to the complexity of analog design there is only

limited support for design automation
• A lot of hand crafting is still necessary

9 Design principles are still the same

• More on this topic will be discussed in the lecture “Analog and
mixed signal simulation”

47
Analog/Mixed IC Design Flow

Specification

Circuit Development

Floorplanning Cell Design

Placement Simulation

ERC

Routing Cell Layout

DRC

LVS

Test Specification Sign Off

48
Commercial Design Flow

9 Now we will have a look to the ASIC design flow from

the commercial perspective
• More details on this topic will be discussed in the lecture “ASIC
management and design interfaces”

9 Goal is to give a basic understanding of the sequence

of events of an industrial ASIC design

49
Commercial Design Flow

idea

draft spec.

12 weeks ASIC vendor feasibility study IP vendor

final spec.

project kick off

50
Commercial Design Flow

submit order design

10 to 40+
libraries, support simulation
weeks

synthesis synthesis test generation

layout layout

2 to 8 sign off
weeks

prototype contract

51
Commercial Design Flow

prototype production design test PCB

3 to 12 prototype test
weeks

prototype delivery

analyse prototypes

4 weeks
prototype approval

52
Commercial Design Flow

qualification

volume order
8 to 20
weeks
volume production

volume delivery

53
Summary

9 We have learned about

– Different kind of ASIC structures
– Structure of custom ICs
– Basic ASIC design flow and its requirements
– Digital design flow and tools
– Compared the digital design flow with the analog
flow
– Commercial design flow

54