DESIGN AND IMPLEMENTAION OF A
DDR SDRAM CONTROLLER
FOR SYSTEM ON CHIP
Magnus Själander
2002-12-13
Contents
• Double Data Rate Interfaces
• DDR SDRAM Architecture and Functionality
• DDR Memory Controller
• Data Resynchronization
• Floorplan and Place & Route
• Future Work
• Conclusion
2002-12-13 2 MO/EAB/RTN/D Magnus Själander
Double Data Rate Interfaces
New
• Data Transmissions on rising and falling edge
• Data Strobe
SDR
Clk
Advantages
• Time of Flight Data D0 D1 D2 D3 D4 D5 D6 D7
• Clock Skew
DDR
• Pin Count
Clk
• Bandwidth
Disadvantage Data Strobe
• Synchronization Data D0 D1 D2 D3 D4 D5 D6 D7
Don't care
2002-12-13 3 MO/EAB/RTN/D Magnus Själander
•
•
•
•
•
Four Banks
Sense Amplifiers
1T Memory Cells
Global Data Path
SDRAM Architecture
Row and Column Select Lines
2002-12-13
4
VDD
SE*
Row Decoder
Row Decoder
Sense Amplifiers Sense Amplifiers
Column Decoder and Global Data lines Column Decoder and Global Data lines
Sense Amplifiers Sense Amplifiers
Row Decoder
Row Decoder
SE
BL
BL*
Central I/O
Row Decoder
Row Decoder
Sense Amplifiers Sense Amplifiers
Column Decoder and Global Data lines Column Decoder and Global Data lines
Sense Amplifiers Sense Amplifiers
WL
M1
Row Decoder
Row Decoder
Cs
BL
BL*
CBL
MO/EAB/RTN/D Magnus Själander
DDR SDRAM Architecture
Input Buffer WEi
I/O Control
• 2n-prefetch CK, CK Data Input Register
DMi
Bank Select Serial to Parallel
• Delay Lock Loop
64
Bank 1
Refresh Counter
Row Decoder
Output Buffer
Sense AMP
Row Buffer
2n-prefetch
Bank 2 64 32
Bank 3 DQ
CK, CK
Address Register
Bank 4
ADDR
Column Decoder
Column Buffer
Latency and Burst Length
Strobe
Gen.
Programming Register DLL DQS
CK, CK
WEi
DMi
Timing Register
CK, CK
CKE
RAS
CAS
WE
DM
CS
2002-12-13 5 MO/EAB/RTN/D Magnus Själander
DDR SDRAM Improvements
SDR SDRAM
• Long Delay in Column Clk
Decode and Data Lines
Data D0 D1
• Added a Delay Lock Loop to 7 ns 7 ns
Increase Clock Frequency Read Data
started available
Clock period
DDR SDRAM
Clk
De
l ay
Delayed Clk
Data D0 D1
5 ns
7 ns
Clock period
Read Data
started available
2002-12-13 6 MO/EAB/RTN/D Magnus Själander
DDR SDRAM Commands
Same Commands as for Standard SDRAM
• READ
• WRITE
• ACTIVATE
• PRECHARGE
• REFRESH
• MRS (Mode Register Set)
Added
• EMRS (Extended MRS)
2002-12-13 7 MO/EAB/RTN/D Magnus Själander
DDR SDRAM Memory Controller
DDR SDRAM Memory Controller
Command Initialize
Command
Data APB Data
Core Memory Address
Command Command Controller
DQS
Address Address
APB Buss
AHB Buss
Write Data Data Strobe DDR
SDRAM
Data Mask
AHB Write Data DQ
Read Data Read Data
DQeven
Read Data
DQodd
2002-12-13 8 MO/EAB/RTN/D Magnus Själander
Core Memory Controller
Initialize Initialization
Initialize
Command
Activate/Precharge
Address Next Address
Command Command
Address Open Banks
Address
Command Address
Refresh
Open
Timing
Row
Refresh
Enable DQS
Address
Address Current Increment Read/Write
Address Boundary Read Write Command
Command
Address
Command
2002-12-13 9 MO/EAB/RTN/D Magnus Själander
AHB Interface
AHB Interface
Command
Command Address Command
Core
Sample Memory Address
Address Controller
Present DQS
Increment Counter
Data Strobe
AHB Buss
AHB DDR
Write Data Core Data Data Data Mask SDRAM
x2 Write Data DQ
Addr Addr
Data Read Data DQ
Read Data Buffer Even even
Data
Data
Read Data DQ
Odd odd
2002-12-13 10 MO/EAB/RTN/D Magnus Själander
Arbiter
DDR SDRAM Memory Controller
Command
AHB Buss 0
Address
Data
Write Data AHB I Strobe
Data Mask
Write Data
Read Data
Command Command
Command
Address Address
Core Memory
Arbiter Address Controller DQS
Command
Command Address DDR
SDRAM
Data Mask Data Strobe
Address Write Data
AHB Buss 1
Data Write Data DQ
Write Data AHB II Strobe
Read Data
DQeven
Read Data
Read Data
DQodd
2002-12-13 11 MO/EAB/RTN/D Magnus Själander
Capturing the Data
• Phase Shift the Data Strobe
• Resynchronize the Data
Clk
Command NOP READ NOP
Address Col n
Data Strobe
Data
Don't care
2002-12-13 12 MO/EAB/RTN/D Magnus Själander
Phase Shift the Data Strobe
• Delay Lock Loop Phase Detector and Control Logic
• Inverter Delay Data Strobe Digital Delay Line
Data Strobe
Delayed 90o
• PCB Line Delay
• Programmable Delay Line with Temperature Sensing
Programmable Delay Line
Data Strobe
Data Strobe Delayed 90o
Programmable Look Up Table
Temperature Sensor
2002-12-13 13 MO/EAB/RTN/D Magnus Själander
Synchronization of the Data
D Q Data Even
One Flip-Flop for each Flank to
Sample Data D Q Data Odd
Data Strobe
Data Strobe
Data 0 1 2 3 4 5 6 7
Data Even 0 2 4 6
Data Odd 1 3 5 7
Do not care
2002-12-13 14 MO/EAB/RTN/D Magnus Själander
Synchronization of the Data Continued
Reference Clock Low
Rising Edge of Data Strobe
Data Strobe
Reference Clk
Clk x2
Data Even 0
Data Stable
Reference Clock High
Rising Edge of Data Strobe
Data Strobe
Reference Clk
Clk x2
Data Even 0
Data Stable Not stable
2002-12-13 15 MO/EAB/RTN/D Magnus Själander
Synchronization of the Data Continued
High D QI
Clk I
S Q Phase
Simplified Phase Detector &
High D QII R
Clk II
Clk I
Clk II
QI
Q II
Phase
Time
Time
Time Line
Line
Line Undefined
2002-12-13 16 MO/EAB/RTN/D Magnus Själander
Floorplan
50 µm
AHB I Read, Write and Address Buss
Data Buffer (AHB I) 155 µm
AHB I Control
Signals
50 µm
DDR Control
Clock Signals
Signals 185 µm 700 µm
DDR Memory Controller
Address and
APB Signals
Data Buss
50 µm
AHB II Control
Signals
Data Buffer (AHB II) 155 µm
AHB II Read, Write and Address Buss
50 µm
35 µm 630 µm 20 µm
15 µm
700 µm
AHB Interface region
2002-12-13 17 MO/EAB/RTN/D Magnus Själander
Place & Route
Data Buffer I
ABH I
Data
AHB Buffer
II II
AHB Core Refresh RW command
AHB x2 Initialization Command Timing
APB Current Address Open Banks Top
Arbiter Next Address Data Out
2002-12-13 18 MO/EAB/RTN/D Magnus Själander
Future Work
• Improved Refresh Handling
• Attempt to Reduce Initial Latency for Bursts
• Improved Buffer Handling
2002-12-13 19 MO/EAB/RTN/D Magnus Själander
Conclusion
• Working Implementation
• Smaller Changes to Improve Performance
• Highlights Difficulties and Solutions
2002-12-13 20 MO/EAB/RTN/D Magnus Själander
Questions ?
2002-12-13
