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Wired-OR Logic: Noise Margin

The document discusses emitter coupled logic (ECL), which is an unsaturated logic family that is faster than TTL. It summarizes the operation of an ECL OR/NOR gate circuit, which consists of difference amplifiers and emitter followers. The circuit has two outputs, where one corresponds to OR logic and the other corresponds to NOR logic. It also describes how multiple gate outputs can be connected to realize additional "wired-OR" logic functions without extra hardware.

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Dhruv Paul
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101 views2 pages

Wired-OR Logic: Noise Margin

The document discusses emitter coupled logic (ECL), which is an unsaturated logic family that is faster than TTL. It summarizes the operation of an ECL OR/NOR gate circuit, which consists of difference amplifiers and emitter followers. The circuit has two outputs, where one corresponds to OR logic and the other corresponds to NOR logic. It also describes how multiple gate outputs can be connected to realize additional "wired-OR" logic functions without extra hardware.

Uploaded by

Dhruv Paul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Digital Electronics 979

Fan-out = Minimum of flit IoL The emitter followers are used at the output of difference
Inputs Transistors Transistors Output
,
7i
/Thi A 8 T3 7, );
Cut-off Active
e0 Cut off
IL ' 0 Cut-off Act ive < ut o ff oje o tcpac
Fan-out for a standard ITL = Minimum of (10,10) =10 Active
LoOe 0 Logie 1 Cut-off Active Cut-off C ' e t o f f L i n e i 01::, I Ric 0
Logic I L.5tic0 Active Active Cut-off Cutoft Witctive ' ! V e t f t 0
Noise Margin Los ie I
Active Active Cut-off Cut-off 'Active
Logic I 4 v:iv:).
IoakI .
The noise immunity of a digital circuit is its ability amplifier to shift the DC level. Th., circuit has two
tolerate a noise signal. A quantitative measure of noise outputs and Y2 which are complementary. Y 1
immunity is known as theooise margin. corresponds to OR logic and Y2 corresponds to NOR
Logic 1 level noise margin\(41) = Von logic.
Logic 0 level noise margin (A0)=VIL VoL The operation of the
circuit is summarized in Y(OR)
For a standard family,
Vni = 2 V, gm =2.4 V, VIL = 0.8 V, Vas =0.4 V
table (a). ti 9(NOR)
Table (a) Operation of
(A1)=2.4 V-2 V=0.4 V Symbol of OR/NOR gate
ECL circuit
(AO) = 0.8 V 0.4 V = 0.4 V In terms of 0 and 1,
table (a) can be written as in table (b).
Emitter Coupled Logic Table (b) Operation of ECL circuit
Emitter Coupled Logic (ECL) is faster than TM family.
The transistors of an emitter coupled logic are operated in
cut-off or active region, it never goes in saturation
therefore, the storage time is eliminated. Emitter coupled
logic family is an example of unsaturated logic family.
Fig. 18 shows the circuit of an emitter-coupled logic
OR/NOR gate.

Wired-
OR
Ys
Logic
The ECI,
circuit has two outputs Y 1 and Y2. Y1 is the
output of OR logic and a is the output of NOR logic.
(Y1 =A + =17 =A +B). When the outputs, of two Or
more than two gates are connected, then an additional
logic is realized without using any additional hardware.
Vcc=+5V Consider the circuit shown in Fig. 19.
Y2
IRc4

Vec= 5 V
Fig.18 Emitter coupled logic OR/NOR gate
Y1
The circuit consists of difference amplifiers and emitter A
followers. Emitter terminals of the two transistors are
connected together hence, it is called as emitter coupled
logic.
V2
Fig. 19 Wired-OR logic

r4=i7,4-y2=A+h+c+D
Y$ = +Y2 =A+B+C +D
Consider another circuit shown in Fig. 20.
Fig. 20 Wired-OR logic

= f2 = A + B C + D
1'5=1'1 +Y2= A +B +C+D

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