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Fpgastructural Verilog Coding

Structural Verilog coding represents the connectivity between components in a design. It uses 26 primitives for gates and switches. The procedure is: 1. Start with a module declaration and list inputs/outputs. 2. Declare inputs and outputs. 3. Declare internal signals as wires. 4. Instantiate gates and specify their inputs/outputs. Examples show codes for a 2-input OR gate, 2-1 multiplexer, and a combinational circuit. Exercises have students write code for a given circuit and draw the logic diagram from given code.

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86 views8 pages

Fpgastructural Verilog Coding

Structural Verilog coding represents the connectivity between components in a design. It uses 26 primitives for gates and switches. The procedure is: 1. Start with a module declaration and list inputs/outputs. 2. Declare inputs and outputs. 3. Declare internal signals as wires. 4. Instantiate gates and specify their inputs/outputs. Examples show codes for a 2-input OR gate, 2-1 multiplexer, and a combinational circuit. Exercises have students write code for a given circuit and draw the logic diagram from given code.

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Shafayat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Verilog HDL

Structural Verilog Coding

Primitives in Structural Verilog Code


Procedure of writing structural Verilog code
Examples of Structural Verilog Code

Prepared By-
Mohammed Abdul Kader
Lecturer, EEE, IIUC
Structural Verilog Code
Structural verilog HDL code represents the connectivity among different components of a design.

Primitives in Structural Coding

Verilog has a set of 26 primitives representing gates and switches.

2 Lecture Materials on "Structural Verilog Coding", By- Mohammed Abdul Kader, Lecturer, EEE, IIUC
Procedure of writing Structural Verilog Code

1) Start Verilog coding using the keyword module.


2) Give an arbitrary name for the circuit that you want to design.
3) Write all the inputs and outputs within a first bracket. Sequence is not matter.
4) Declare which are inputs (that you have listed in the first bracket). If bit width of input is more
that one bit that it needs to mention.
5) Declare which are outputs including number of bits.
6) Declare the internal signals of the circuit as wire.
7) Instantiate the logic gates that we have used in the design (or, not, and etc)
8) Specify the outputs and inputs of the logic gate within a first bracket (after the instantiation
name). Sequence is name of the output and then input.
Example 1:

3
Lecture Materials on "Structural Verilog Coding", By- Mohammed Abdul Kader, Lecturer, EEE, IIUC
Example 2: Structural Verilog code for 2/1 Mux

4 Lecture Materials on "Structural Verilog Coding", By- Mohammed Abdul Kader, Lecturer, EEE, IIUC
Example 3: Structural Verilog code of a combinational digital circuit

5 Lecture Materials on "Structural Verilog Coding", By- Mohammed Abdul Kader, Lecturer, EEE, IIUC
6 Lecture Materials on "Structural Verilog Coding", By- Mohammed Abdul Kader, Lecturer, EEE, IIUC
Exercise 1: Write structural Verilog code for following circuit

7 Lecture Materials on "Structural Verilog Coding", By- Mohammed Abdul Kader, Lecturer, EEE, IIUC
Exercise 2: Draw the logic diagram from the Verilog code as shown below.

8 Lecture Materials on "Structural Verilog Coding", By- Mohammed Abdul Kader, Lecturer, EEE, IIUC

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