Design Challenges For Distributed Power

Systems
Fred C. Lee, Ming Xu, Shuo Wang and Bing Lu
Center for Power Electronics Systems
The Bradley Department of Electrical and Computer Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061 USA
Email: fclee@vt.edu
Abstract: Remarkable progresses have been made over the
past decade in power conversion technologies, including
advanced power semiconductor devices, power management
ICs, innovative circuit topologies, and packaging and
integrated system solutions. These technological advancements
have been manifested in a wide range of products and
applications with ever increasing performances, efficiency, and
power density. This paper highlights some of the challenges
and opportunities of power conversion technologies in the
Distributed Power System
(DPS) for computer,
telecommunication and network products. Topics discussed in
this paper include improved EMI filter design techniques to
mitigate the detrimental effects of filter/converter parasitics;
impacts of the operating frequency of PFC to the size and
weight of EMI filter; power conversion architecture and
potential simplification; high-frequency high-density AC/DC
and DC/DC topologies and designs; bus converters; as well as
non-isolated point- of -load converters

configured to be scalable and adaptable to ever changing

power requirements of computers and telecommunication
equipment and systems. The frond-end AC/DC converter is
a standardized module with the paralleling capability to
convert the AC voltage source into the 48V DC voltage bus.
This DC bus voltage is often distributed via a back-plane
into various circuit boards in a form of plug-in modules, or
"circuit packs" in the telephone jargon, with additional
point-of-load DC/DC modules locally supplying the need
power levels at the appropriate voltages to the end users.
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Keywords-DPS, Power Architecture, EMIfilter, ACIDC, DCIDC

I. INTRODUCTION

Widespread use of the internet and telecommunication

requires infrastructure support using a more sophisticated,
high-quality and reliable "power network" that naturally
takes the form of distributed power generation, distribution
and regulation. Such a system is expected to achieve fully
controllable, fully reconfigurable, autonomous platforms
and customized for ever changing applications. It is
envisioned that these advanced systems will be required to
provide on-demand power from a required source, and
required load at any rate and in any desired form. A typical
distributed power system (DPS) as shown in Fig. 1, is

Fig. 1. Distributed power system

1-4244-0449-5/06/$20.00 C2006 IEEE

(a)

(b)
Fig. 2. Power density roadmap
(a) AC/DC converters, (b) DC/DC converters

With ever increasing in functionality and shrinking in size

and weight of all forms of computer and telecommunication
equipment, it is essential to pack the advanced power
hungry processors onto each circuit boards together with the
high quality customized and miniaturized power. The
aggressive power density targets for AC/DC converters and
DC/DC modules, as shown in Fig. 2 [1], respectively were
met in the past decade and perhaps in the foreseeable future.
The typical real estate utilization of the state-of-the-art 3kW
1U telecom AC/DC with 25W/inch3 is shown in Fig.3.
From this picture, it can be easily seen that EMI filter, PFC
inductor and bulk capacitors and magnetics in the DC/DC
converter represent the major portion of the system.
With rapidly growing computer, telecommunication, and
internet technologies and applications, power supplies,
other than demanding for higher power density, must
achieve higher power conversion efficiency, especially at
lighter load, in order to meet the stringent regulation for
energy saving.
IPEMC 2006

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In the following sections, design challenges and

opportunities for EMI filter, front-end AC/DC, board
mounted DC/DC will be presented. More distributed power
architecture with potential cost saving and performance
improvements is proposed. At the meantime, system
packaging and integration technologies leading to further
improvement of power density and performances are
discussed.

Fig. 3. State-of-the-art front-end converter layout

IIEMI FILTER DESIGN CONSIDERATIONS AND CHALLENGES

In power electronics applications, electromagnetic (EMI)
filter is a necessary interface between the power line and
power conversion equipment, such as AC/DC and DC/DC
converters operating in high frequency switching mode.
They generate conducted switching noise with a spectrum
that ranges from the designed switching frequency up to
30MHz. EMI standards, such as EN55022 class A, specify
the frequency range (l5OkHz-30MHz) and noise limits
which all power supplies must meet. In order to satisfy
these EMI standards, one or two stages of EMI filters are
usually employed. A typical one-stage EMI filter used in
power supplies is shown in Fig. 4.

Powa C

L-

L,m

Lm

inductors degrades significantly the filter high frequency

performances. Investigation [2, 3] shows the mutual
coupling (mutual inductance) between inductor and trace
loops, between inductor and capacitor, between two
capacitors significantly affect differential mode (DM) EMI
filter's high frequency performances. Equivalent series
inductance (ESL) of capacitors also plays the role on the
filter performances. The equivalent parallel capacitance
(EPC), i.e. winding capacitance, of the inductor is a key
factor detrimental to CM filter's high frequency
performances [8]. These parasitics must be minimized to
improve EMI filter's ability to attenuate high frequency
noises.
The mutual inductance between inductor and trace loops
can be easily reduced by reducing the loop areas. One
simple method to minimize the coupling between the
inductor and capacitors is to rotate the inductor winding by
90 as shown in Fig. 6 [3]. In so doing, the mutual
inductance can be reduced by as high as 92% (89.3nH vs.
7.5nH). To reduce the mutual inductance between two
capacitors, one simple method is simply to arrange
physically the two capacitors to be perpendicular [4]. In
this manner, the coupling between the two capacitors can be
reduced by 66% as shown in the measurement result. An
even better method is to place a 3/4 turn in parallel with one
of the capacitor as shown in Fig. 7 [7].
20

-40
-60
-80
100
-120

-140
-160
-1801. OOE+04

N
piStis

1. OOE+05

1. OOE+06
Frequency (Hz)

1. OOE+07

1. OOE+08

(a)
OOE+00

PO||a

OO(E'(01
OOE+0t 1

Circuit

Prototype

Fig. 4. One-stage EMI filter under investigation

Due to the self- and mutual parasitics, the EMI filters do

not work as well as expected at high frequencies (HF). Fig.
5(a) compares three DM insertion voltage gain curves, the
curve that represents filter with ideal components, the curve
that includes components together with their associated self
parasitics, and the curve including self parasitics and
parasitics due to the coupling of electric field or electromagnetic field referred to as mutual parasitics. It is shown
that the self parasitics make DM filter's HF performance
much worse than that of an ideal filter; however, the mutual
parasitics finally determines filter's HF performance. For
CM filter performance shown in Fig. 5 (b), the self
parasitics, especially the winding capacitance (EPC) of

Frequency(Hz)

(b)

Fig. 5. Comparison of insertion voltage gains: (a) Differential Mode (DM)

and (b) Common Mode (CM)
M5'M2\

M2

A~~~~~~

p2

Windings are rotated by 900

Fig. 6. Reducing the mutual inductance between the inductor and

capacitor

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In Fig. 7, the magnetic flux linking C2 also links

cancellation turn, so the mutual inductance between two
capacitors is cancelled. A 92.3% reduction (439pH vs.
19pH) is achieved in the measurement. The suggested
methods illustrated in Fig. 6 and Fig. 7 can be employed at
the same time to achieve even better results. Fig. 9 shows
the measured insertion voltage gains with these proposed
methods and compared them with the original EMI filter
without incorporating any suggested methods for
improvement.
Fig. 8 shows that the combination of methods suggested
in Fig. 6 and Fig. 7 gives best result. A 40dB improvement
achieved at 30MHz. It is well known that capacitor behaves
like an inductor at high frequencies after the series resonant
frequency between the capacitance and the ESL. For a
0.47[tF/400V film capacitor, the measured series resonant
frequency is around 2MHz, which means this capacitor
behaves like an inductor beyond 2MHz. For an electrolytic
capacitor (220tF/250V), the measured series resonant
frequency is even below 100 kHz. If this electrolytic
capacitor is used as a bulk capacitor for a converter with
switching frequency above 100 kHz, the capacitor actually
works like an inductor even for the fundamental component
of the switching waveform.
t-

Wang and Lee [9] further proposed a method to cancel the

ESL of capacitors so as to significantly improve capacitor's
filtering performance at high frequencies. The idea is shown
in Fig. 9.
Fig. 9 shows that the two networks on the top are
equivalent. If two capacitors are diagonally connected and
the inductor L is chosen with a value equal to the ESL of
the two capacitors, then the resultant network is a T filter
with the capacitor free from ESL as shown in the bottom
diagram. In the proposed concept, the L can be
implemented with the PCB trace inductance. Fig. 10 shows
the measured insertion voltage gains with and without ESL
cancellation. It is shown that after ESL is canceled, the film
capacitor's performance is improved significantly above
3MHz and a 27dB improvement is achieved at 30MHz
when compared with two paralleled capacitors. For
electrolytic capacitors, a 27dB improvement at 30MHz also
demonstrated and performance improvement above 150
kHz is also noted. The performance improvement for both
film and electrolytic capacitors is further verified in [9] by
measuring the EMI noise of a converter using a noise
separator [6] and a spectrum analyzer.
-30

-Twc pa allel c

itors

Cl

-Y'

-40

13, 'I"

EL

1}11011

n
-80 j
1. OOE+05

1 .OOE+07

1 .OOE +06

1 .OOE +08

Frq.u.ny(Hz)

Fig. 7. Integrating cancellation turn with capacitor to cancel mutual

inductance between two capacitors

(a)

-11

-10

f77T7~

NIN %

--r~a~uwr-u--

ff
'a

gs

-30

- 40

.e

L.r,

cular

-20

Twc

"I

it

ion turn +

Id windings

zi

zi

-60
1.001)E+05

1. OOE+06

Zi
ESL

1.00E+07

1. OOE+08

2C

EPC

IDM

L8

EPRII

ICM

1 EPC
L

TCN

IDM
o$t~~~2
t

EPRII

EPC
L

ESL

ESR/2
ESt2C

EPR

IDM

L=ES L

(b)
Fig. 10. Comparison of capacitor performance: (a) film (0.47tF/400V) and
(b) electrolytic (220tF/250V)

Zl 2l

Zl

ESR

an, .ellatl

Frequency(Hz)

Fig. 8. Comparison of filter performance

I,

"e,

,M"

Frequeny (Hz)

Z3

-11,

-50

li
zi

parallel

apaclu
17

EPC

(a)

IDM

L/8

L8

ICM

EPC
EPR

(b)

EPC

(c)

Fig. 11. Inductor model: (a) separate DM inductor model (b) model for two
DM inductors in one core and (c) CM inductor model.
(a)

(b)

Fig. 9. Illustrating the idea of ESL cancellation: (a) network with

cancellation inductor and (b) the equivalent network without ESL

The method for cancellation of winding capacitance EPC

of an inductor was proposed recently [10, 11]. Fig. 11

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shows models for DM inductors and CM inductors taking

into consideration of EPR and EPC. Fig. 12 shows the
ideas of winding capacitance cancellation.
If the two DM inductors are separated, i.e. not on one
core, the parasitic model can be shown in Fig. 11(a). If two
DM inductors are on one core then there is equivalent
parasitic capacitance CN between two inductors as shown in
Fig. 11(b), since the permittivity of the core would be
relatively high and the distance between two inductor
windings are relatively close. For CM inductor the model is
shown in Fig. 11 (c).
In order to cancel the winding capacitance of DM
inductors, two extra small capacitors are needed. For
separate DM inductors, two small capacitors with values
equal to EPC are diagonally connected to two inductors as
shown in Fig. 12(a). The cancellation mechanism can be
explained by network equivalence as well as mutual
capacitance theory developed in [10]. For combined DM
inductors, since two windings are on the same core, the
effect of CN can be equivalent to a negative capacitor with
value of CN/2 in parallel with each inductor [10, 11]. If the
equivalent negative capacitance is smaller than original
EPC, then the total winding capacitance is still positive.
Two small capacitors with values of EPC-CN/2 can be
diagonally connected to two inductors to cancel it. This is
shown in Fig. 12 (b). However, if the total winding
capacitance is negative, then two small capacitors with
values of CN/2-EPC should be parallel with two DM
inductors. Ironically, in order to cancel the winding
capacitance, external capacitors are needed in parallel with
windings. This is shown in Fig. 12 (c).
--E:::~

N2

A-I

EPCI
L/4

XI

EPCI

EPR2

L/4

--

C01=4EP
L/4

I
-

(a)

(b)

Fig. 13. The cancellation of winding capacitance for CM inductor:

(a) Cancellation idea and (b) proposed bifilar winding structure

two winding halves and the cancellation capacitor can cause

high frequency noises.
A bifilar winding structure, which is not used in
conventional CM inductors due to large EPC, is proposed
for high coupling coefficient. Because two winding halves
are almost in the same position, the coupling coefficient is
very high. The measured value is 0.99995. Although EPC is
enlarged, the EPC cancellation techniques can be employed
and the performance improved.
10

-20-

-30

1. OE+05

1. OE+06

1. OE+07

1. OE+08

1. OE+07

1. OE+08

Frequency (Hz)

EPC
L/8

L/8

(a)

-C

'N

10

L8

L/8

_a

EPC

-15

20
3025

EPR

(a)

cI

EPC
EPR

E2 2

L2

to

b L/4

-a C1=4EFCC

EPR

EPRI
EPCI

Li
N1

EPR

(b)

(c)

Fig. 12. Winding capacitance cancellation for DM inductors: (a) separate

DM inductor, (b) two DM inductors on one core when equivalent winding
capacitance is positive and (c) two DM inductors on one core when
equivalent winding capacitance is negative

For CM inductors, the method proposed for DM inductors

can also be applied if a winding is allowed in ground path.
If the winding is not desirable on ground path, the method
proposed in [4] can be considered. For the method in [4],
the coupling coefficient between two half windings of one
side must be as high as 0.9999, which is possible to be
realized in an integrated inductor structure. However, for a
conventional discrete CM inductor winding structure, the
coupling coefficient is around 0.99. Therefore, the idea can
not be applied, since a resonance between the leakage of

10

30

1. OE+05

1. OE+06

Frequency (Hz)

(b)
Fig. 14. Improvement on inductor impedance: (a) DM inductor and (b) CM
inductor

Fig. 14 (a) and (b) show the measured impedance of the

filter inductor. Impedance at high frequencies is
significantly reduced for both DM and CM inductors due to
winding capacitance cancellation. Both DM and CM
inductor filtering performance is improved by more than
20dB. More elaborated EMI noise measurements on the
proposed EPC cancellation techniques when applied to a
power converter were reported in [10, 11] with significant
improvements shown.

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1 .106

In this section, various techniques for cancellation of both

mutual parasitics and self-parasitics are introduced. A much
better understanding of the basic nature of EMI noises had
led to development of in the practice. Continuous research
in this area will eventually lead to an understanding and
development of this subject matter as a branch of science in
stead of art or "magic" as it is often referred to.

20% ripple

I .104

III. HIGH FREQUENCY HIGH DENSITY FRONT-END AC/DC

For the front-end AC/DC converters, normally they are

implemented by two-stage approach. The first stage is the
power factor correction (PFC) stage, which is able to
provide power factor correction function and a constant
voltage for the DC/DC stage input. The second stage is the
DC/DC stage, which gives a regulated output voltage for
the load. For the PFC stage, the single switch continuous
current mode (CCM) PFC is the most widely used topology
because of its simplicity and smaller EMI filter. For the
whole front-end converter, the EMI noise major comes from
the PFC stage. The differential mode and common mode
EMI noise models for the single switch CCM PFC circuit
have been derived and verified by CPES. Based on the
derived the EMI noise model, the switching frequency
impact on the EMI filter design of the PFC circuit is
analyzed. The switching frequency selection guideline is
given based on the analysis.
III-. Benefitsfrom High Frequency PFC:

Based on the filter attenuation requirement, we are able to

develop the relationship between the corner-frequency of
the filter and the switching frequencies of the converter, as
shown in Fig. 15(a) [13 15]. In these curves, the zigzag
nature of the curve is caused by the EMI standard which
specifies the regulation requirement beginning at 150 kHz.
Those vertical jumps at frequencies representing the various
sub-harmonics of 150kHz, such as 50kHz, 75kHz, etc.
When the switching frequency is slightly lower than those
frequencies, the corner frequency of the DM filter is much
higher. Beyond 150 kHz, the filter corner frequency will
continue to increase as the switching frequency increases.
From the curves, it can be seen that when the switching
frequency is roughly higher than 400-500 kHz, the corner
frequency of the DM filter will be higher than all the
previous peaks. As it is know, higher the corner frequency
means smaller the EMI filter size. Therefore, one can
observe that the size reduction of the DM filter is achieved
only if the switching frequency is higher than 400-500 kHz,
in comparison with that at 150 kHz.
Similar observation can be made for the CM filter. From
Fig 15(b), it can be seen that irrespective to what K value is
( where K is related to the circuit parasitic, the switching
speed of the MOSFET and the output voltage of the PFC
circuit.), when the switching frequency is higher than
400kHz, the size of CM filter will be smaller than that
previously achieved at 150kHz. Further increasing of the
switching frequency will continue to reduce filter size.

30% ripple

1 .104

.105

fs

.106

I *10'

Switching frequency (Hz)

iio-6

(a)

I-lo'

GL)

GL)0-

0-

K=10
K=5 1.105

K=1

-10

.104

.104

10'

I .106

Switching frequency (Hz)

(b)
Fig. 15. Filter corner frequency vs. switching frequency:
(a) Differential Mode (b) Common Mode

From the previous analysis, we can conclude that the

switching frequency has great impacts on the EMI filter
design. Since the EMI spec begins at 150 kHz, certain
frequency range should be avoided. Clearly, there is no
filter size reduction achieved when the switching frequency
is chosen between 150-400 kHz. Since the new generation
of power devices, such as CoolMOS and SiC, enable the
PFC circuit to operate at a much higher switching
801i

801i

70

I;

40
0

..e I

iD rDiiDlgiSllW
8 1jlWlxJ,hDv

Illl Il'I'

40
stadar

1,

10
0

100000

1000000

f(Hz) 10000000

10000(

100000

1000000

f(Hz)

10000000

100000000

(b) 400kHz PFC EMI noise

(d) 400kHz PFC EMI filter

(e) lOOkHz Boost inductor

(f) 400kHz Boost inductor
Fig. 16. EMI noise after filtering and EMI filter size comparison

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frequency. It is possible to contemplating a siwitching

frequency higher than 400 kHz. To illustrate this p(Dint, two
CCM PFC circuits were built, one operated at 100 IkHz and
the other at 400 kHz. Two EMI filters were dlesigned,
respectively to meet the EMI standard EN55022 Class B.
As shown in Fig. 16, both of the converters can fmeet the
standard at the low frequency range. For the two different
EMI filter and boost inductor, we can see that 3500 and 55O
volume reduction is achieved respectively by pus]hing the
switching frequency from 100kHz to 400kHIz. The
excessive noises at high frequencies are due to paraisitics of
the EMI filter as discussed in the previous sectiion. The
problem can be solved by using the suggested tec,hniques,
grounding and shielding technologies.
In Fig. 17(a), the impedances of the boost inductc rs when
designed for 100 kHz PFC, there is a resonant vallD ey at the
frequency about 17MHz. At this frequency, the imipedance
of the boost inductor is small. Therefore, the EMI noise at
corresponding frequency is high, which can be seein in Fig.
17(b) [15, 16]. But for the 400 kHz boost indu(ctor, the
resonant valley is pushed beyond 30MHz, as disc ussed in
the previous section; the filter's ability to attenu,ate high
frequency noises is compromised with the pres,ence of
parasitics. Therefore, it is important to eliminate Ithe high
frequency noise peaks. From the experimental res,ults, we
can clear see that the benefit brought by pusthing the
switching frequency higher.
To get high switching frequency for PFC, CTPES has
evaluated different device combinations. As showrn in Fig.
18, the revolutionary devices, CoolMOSTm and SiiC diode
enable much higher efficiency and higher frequency [17]. A
10K

1 00
n

1 0
10

0.1

0.01~00
1 Ok
1 OOk
1k

1M

F re q uency(H z)

0IV1 3 0 M

(a)

160j
140

100

m
60-

400 k:Hz Noise

40
20
0

1.00E+04

1.00E+05

1.00E+06

1.00E+07

1.00 E+

Frequency (Hz)

(b)
Fig. 17. Comparison between two boost inductors for dif-ferent
switching frequencies: (a) Impedance, (b) EMI noise

1kW CCM PFC using CoolMOS TM and SiC diode

running at 400 KHz is demonstrated. It shows that by using
the CoolMOSTm and SiC diode, the 400 KHz CCM PFC
can achieve the similar efficiency by using conventional
devices at 100 KHz switching frequency, as shown in Fig.
18.
0 .99

916

O..-95

Id

CI

0 .92

I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

0 91

099114

90

10

240

Fig. 18. Efficiency comparison between different PFC designs

Normal: IRFP460 + RHRP860, New: CoolMOS + SiC diode

III-2. High frequency DC/Converter:

To achieve high power density for the front-end AC/DC

converters, increased switching frequency is desired.
However, its effectiveness is limited by the large holdup
capacitors. For the telecom and computer applications,
system is required to maintain a regulated output voltage

with full power for 20ms after AC input is lost. Therefore,

bulky capacitors are employed to provide the needed energy
during holdup time. The size of the selected bulk capacitors
will directly impact the input voltage range of the down
stream DC/DC converter, thus its conversion efficiency and
power rating. To reduce the holdup time capacitors and
improve converter power density, it is essential to select an
appropriate converter topology that can achieve high
efficiency with wide input voltage range, especially high
efficiency at 400V input [18 20].
For conventional PWM DC/DC converters, a maximum
duty cycle is designed for the minimum input (say, 300V)
which occurs when the AC input power is lost.
Consequently,

the

given

circuit will operate at

smaller

duty cycle when the input voltage is at around 400V. Thus,

to realize a wide input range, it is inevitable that the
converter efficiency is suffered at the nominal input of
400V. Fig. 19 demonstrates the efficiency of an
asymmetrical half-bridge (AHB) optimally designed for a
fixed input voltage at 400V. The circuit can achieve 94.50
efficiency. When the same circuit is designed to operate at
300V to 400V input range, the converter efficiency can only
achieve 92% at 400V [20].
Instead of using PWM converters, certain class of
resonant converters such as the LLC resonant converter as
shown

in

Fig. 20(a)

is

able

to

operate

with

wide

input

without compromising circuit efficiency at the desired

operating voltage, i.e. at 400V. Because the magnetizing

range

inductor participates in

characteristic is change,

resonant, converter

as

voltage gain

shown in Fig. 20(b).

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96

3OOV

LLC for
to 400V input

96

_ ~~~~~~~~AHBSfor 400V i
9 4-

200kHz--

,?

~!95-

400kHz

UD 94-

94inputonly

LU 93

\ 1 MHz

92

LU

92

/AH

for

300V

to

300

320

340

360

400

600

800

Output power (Vl!)

1000

1200

Fig. 21. Efficiencies for LLC converter with different switching frequency

90AC4V input

90

200

400

380

Vin (V)

Fig. 19. Efficiency of AHB and LLC converters

ZVS Region
Q1

n:l:l

Vin

Lm .

Dl

-4

Vo

1-1T

D2

ZCS Region
RL

Normalized ftequency

(a)
(b)
Fig 20. LLC resonant converter (a) Circuit topology (b) Voltage gain

The LLC converter can achieve a voltage conversion ratio

either higher or lower than unity. Moreover, the zero
voltage switching (ZVS) can be achieved with switching
frequency both lower and higher than the series resonant
frequency determined by Lr and Cr. By choosing a suitable
transformer turns-ratio, the converter can be targeted to
operate right on top of the resonant frequency with optimal
efficiency at normal operation condition, i.e.400V input.
During holdup time, input voltage drops, and LLC resonant
converter reduces its switching frequency and increase
voltage gain to maintain regulated output voltage. Although
LLC converter operates far away from the resonant point
during the holdup time which means the circuit is less
efficient, it only lasts for 20mS and will not cause extra
thermal problem. Because LLC converter can operate at
resonant frequency during normal operation condition, the
circuit is operated at the most efficient point and its
efficiency could be much higher in comparison with AHB
or other PWM topologies. As shown in Fig. 19, with 200
kHz switching, LLC could achieve 2 to 300 efficiency
improvement over that of AHB. Moreover, LLC resonant is
operated with ZVS turn-on and relatively small turn-off
current. These properties make switching losses at the
primary side switches very small. Besides, the secondary
side diodes are also operated with ZCS thus reduces the
diode reverse recovery loss. The much reduced switching
losses enable LLC resonant converter to operate at much
higher switching frequencies while maintaining high
efficiency. A proto-type 1MHz LLC was developed with
94.5O efficiency at 1kW output. The efficiency of LLC
resonant converter for different switching frequency is
shown in Fig. 21. As shown in Fig. 22(b), 1MHz LLC
achieves 76W/in3 power density [20, 22].

(a)
(b)
Fig. 22. Comparison among different DC/DC converter designs:
(a) 200 kHz AHB, 12W/in3, (b) IMHz LLC, 76W/in3

III-3. High density front-endACIDC via IPEMs

Although higher density is achieved at higher frequency,

some fundamental limitations prevent further improvement
in power density. For example, the parasitic inductance in
the switch commutation loop hampers the switching speed
and causes more switching losses. Large voltage stresses
appear on switching devices due to large parasitic
inductance, which compromises reliability. The parasitic
junction capacitances between high voltage transition points
to the earth ground increases the common mode noise.
Moreover, the parasitic components brought by the
interconnection of the electrical layout played a negative
role in the system electromagnetic interference noise (EMI)
if it is not treated carefully.
The front-end ac/dc converters are essentially customdesigned and manufactured using discrete parts, which high
labor content and high cost. To address the aforementioned
performance issues and cost, the integrated power
electronics module (IPEM) concept was proposed by Center
of Power Electronics Systems (CPES). The IPEM concept
is to explore the integration of discrete power devices to the
extend that it is technologically practical and economically
feasible. To this end, the active power semiconductor
devices, with its associated drivers, protection circuits,
sensors and controller are integrated together in the form of
modular building block here referred to as active IPEM.
Similarly, the passive power components such as inductors,
capacitors and power transformers are integrated together
into a Passive IPEM. One apparent benefit of integration is
the size reduction. The integration of the switching devices
together with their associated gate driver circuit, invariably
will reduce parasitics associated with interconnects, thus
resulting in smaller switching losses and voltage stresses.
By integrating inductors, capacitors, together with power
transformer, passive component size can be greatly reduced.
Moreover, due to the integration, circuit component number
can be greatly reduced. The assembly of such modules
could be automated thus reduce labor content. Furthermore,

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by perfecting the process of integration, IPEMs can become

standard building blocks to facilitate system integration.
Therefore, the reliability, product cycle time and cost can be
significantly reduced [23, 24].
To demonstrate the benefits of the IPEM concept under
the system level, two 1kW front-end AC/DC converters
were built using exactly the same topologies, one using
discrete devices and the other one using IPEMs. As shown
in Fig. 1 and 23, the system is constructed by the two
stages: PFC stage and DC/DC stage. For the PFC stage, a
400 kHz single switch PFC using CoolMOS and SiC diode
were chosen to reduce the boost inductor and EMI filter.
The Asymmetrical Half Bridge operating at 200 kHz was
used for the DC/DC stage. The converters are designed for
the universal input line 90V-264V, and the power rating is
de-rated to 600W when operated below 150V input. Two
converters are show in Fig. 23. The discrete components
have been replaced by the Active and Passive IPEMs.
Through integration, density and form factor of the active
and passive devices are much improved. Therefore, the
power density at the system level is improved significantly.
As for the discrete approach, the power density is 7.5 W/In3,
and for the IPEM-based converter, the power density is 11.4
W/In3 and still has the room for improvement.

IV. HIGH FREQUENCY HIGH CURRENT DENSITY BOARDMOUNTED ISOLATED DC/DC CONVERTERS

With rapidly growing computer and telecommunication

applications, the point-of-load (POL) DC/DC module is
becoming smaller and smaller, from non-isolated POL to
isolated 1/4 brick to 1/8 brick and even to 116 brick, and in
the mean time, with continuous increasing in current
demand and decreasing in output voltage. High power
density and high efficiency are demanded by the customers
Design engineers ,now a day are facing challenges in all
fronts, including higher operating frequencies with reduced
switching losses, conduction losses, body diode losses and
even the gate driver losses; innovative packaging and
thermal management; EMI and EMC containment and
reduction.
This section will introduce two examples of circuit means
of achieving higher operating frequencies and in the same
time, higher efficiencies. These goals are realized by
simultaneously reducing the primary side switching losses
and conduction losses as well as the secondary side
synchronous rectifier body diode conduction losses, reverse
recovery losses, drive losses, and conduction losses.
IV-J. Single Stage isolated DC/DC:
A. State-of-the-art:

Fig. 24(a) shows a typical PWM hard-switching 48V

input DC/DC topology. To get faster dynamic performance
and higher power density, higher switching frequency is
desired. However, as shown in Fig. 24(c), efficiency will
suffer a lot at higher switching frequency mainly due to the
switching loss, driving loss and SR body diode conduction
loss. By far, the soft switching technique is a well-known
approach to reduce the switching loss effectively.

Fig. 23. Comparison between the discrete and integrated DPS System:
(a) Discrete devices DPS, (b) IPEM-based DPS

By replacing the discrete active and passive devices into

the IPEMs, the number of components of the systems can
be reduced from several hundreds part to about 20-30 parts.
Not only the system power density has been improved, the
system electrical performance has been improved as well.
The system efficiency increases more than 2% at the high
line voltage range, and more than 300 at 90V. Since the
conduction losses are roughly the same for the same
operation condition, the major improvement lies on the
switching loss reduction by minimizing the circuit
parasitics.
At the same time, due to the smaller parasitic inductance
on critical path of the converter, less voltage stress is
achieved. For the discrete PFC switch, when switch turn off
occurs at 7Amp, the device voltage overshoot is 123V. But
when the discrete components are replaced with an active
IPEM, the voltage over-shoot is reduced to 72V even at
1 OAmp.

(b)

(a)

1OOkHz
500kHz

8 00

00kHz

7.00
6 00

-:

5.00

(I)

4.00

0)

o 300

-J

2 00

1.00
0.00

C,

(c)

Fig. 24. State-of-the-art power pod in server

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Therefore, Fig. 24(b) shows the state-of-the-art 48V DC/DC

for server processor (power pod), running at 300KHz by
employing phase-shift full-bridge ZVS topology. Its
efficiency can be seen in Figure 30(b).
In the conventional synchronous rectifier, the dead time
is necessary, accompanying with the body diode conduction
loss and reverse recovery loss due to the current through the
body diode during the dead time. There are some precise
timing-control driving ICs to reduce the body diode
conduction loss. However, they cannot effectively solve the
body diode reverse recovery problem. And also, they are
expensive and noise sensitive.
A. Self-Driven ZVS Full-Bridge DCIDC and Magnetic
Integration:

The self-driven technique has been widely used in the

industry practice due to their simplicity and low cost.
However, for bridge-type symmetrical converters,
implementation of self-driven capability is difficult because
of the inherent dead time period. One possible solution is
the level-shifted self-driven concept [25]. However, the
proposed approach has several drawbacks: (a) Ringing
occurs at the gate signal because the signal is coming from
the main power transformer and severe ringing is coupled
from the power stage, (b) there is extra body diode
conduction loss, and (c) there is large amount of conduction
loss due to the low driving voltage during dead time. These
issues prevent the level-shifted self-driven concept from
being used in high-frequency applications.
In order to overcome these issues, a self-driven ZVS fullbridge (FB) was proposed [26, 27]. The power stage is
shown in Fig. 25. By simply rearranging the control
strategy, it becomes very suitable for self-driven capability
as well as achieving ZVS. It was further demonstrated that
the self-driven scheme can save driving loss and body diode
conduction loss and is very suitable for high-frequency
applications where high power density is required.
A 1MHz prototype picture shown in Fig. 26(a) was built
to verify this self-driven concept. Fig. 26(b) shows the
efficiency comparison. Including the driver loss, the
proposed self-driven ZVS full-bridge can achieve 81.7%
efficiency. There is an efficiency improvement of 4.70 as
compared with the conventional phase-shifted full-bridge
with an external driver.
5 Qa Q424 .CI 1 S1~~S
in

..............I
-sl

.Q2
......

Q
..

Ia

..................

H....

....

.....

........................... .................
'-----

..

..

Fig.25. Conceptual diagram of the proposed self-driven ZVS full-bridge

DC/DC converter

However, this topology requires a total of 3 discrete

transformers, one main power transformer and two
synchronous rectifier gate drive transformers, thus
increasing the number of passive components. Further work

(a)
(b)
Fig. 26. (a) Hardware of the proposed DC/DC, (b) efficiency comparison

has been done to integrate all of the three magnetic

components and two output inductors into a single core as
shown in Fig. 27 [28]. This fully integrated magnetic has
been adopted in a 1.2V/70A 1/8 brick prototype with 87%
overall efficiency at 600 KHz switching frequency.
Comparing to the state-of-the-art 1/8 brick product, it can
deliver 4000 more output current while having 2% higher
efficiency.

Fig. 27. 600 KHz 1.2V/70A1/8 brick hardware and measured efficiency

Generally, the gate driving loss can be reduced by the

combination of the ZVS technique and Self-driven
technique. As an example, the proposed self-driven ZVS
full-bridge has the following advantages: (a) soft switching
for primary switches; (b) clean gate signal and no levelshifting during dead time; (c) reduced gate driving loss; and
(d) reduced body diode conduction loss. The experimental
results verify that this topology is very promising in highfrequency applications. Furthermore, the proposed selfdriven method can be applied to any bridge and non-bridge
topologies employing complementary control.
B. Current Tripler Concept and Magnetic Integration:

For low-voltage and high-current applications, the

secondary-side device switching and conduction losses have
a major impact on system efficiency. To reduce the
conduction loss in the secondary side, one solution is to
reduce the on-resistances of the synchronous rectifiers and
the transformer winding resistance. This can be realized by
paralleling more synchronous rectifier switches (SRs) and
enlarging the window area of the transformer. The
drawbacks of this solution are the higher cost, larger gate
driver loss and larger footprint.
Other than reducing the Rds (on) of the synchronous
rectifier, proper secondary-side topologies should be
selected to reduce the RMS current through the SRs. There
are three major secondary-side topologies: forward rectifier,
center-tapped rectifier and current-doubler rectifier. Among
these three topologies, the current-doubler rectifier is the
most suitable for high-current, low-voltage applications.

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Because of its simpler transformer structure and halved

inductor currents and transformer secondary currents, the
current-doubler topology offers lower conduction losses
than the conventional center-tapped topology [29].
The reason for the lower RMS current of the currentdoubler rectifier is that during the freewheeling period
(when there is no input-output energy transfer), both SR
switches can conduct simultaneously to share the load
current. As a result, the total rectifier conduction loss during
the freewheeling period is reduced. To further reducing the
conduction losses for higher current applications, often
times, current-doubler with more semiconductor devices in
parallel and distributed magnetics are used to reduce the
transformer winding losses. However, those solutions have
their limitations:
a) Increased cost,
b) Larger footprint and lower power density, and
c) More devices mean greater driver loss.
Recently, a novel current-Tripler topology was proposed,
as shown in Fig. 28. The proposed topology can easily
achieve ZVS for all MOSFETs, therefore switching loss is
significantly reduced [30]. Through magnetic integration
shown in Fig. 29, a three phase high frequency transformer
can be used to greatly simplify the circuit.
Compared with the conventional current doubler, the
proposed current Tripler can reduce the SR conduction loss
and transformer winding loss by 20% and 12.5%
respectively.
A 300 kHz prototype was developed to demonstrate the
concept. Comparing to the typical industry design with the
same spec and switching frequency, proposed current-

Fig. 28. Proposed Zero-Voltage-Switch current-Tripler DC/DC converter

~~~~--b
3a-

BtW1

aL-

(a)

X , _umm

Bl

(b)

(c)

Fig. 29. Implementation by three discrete cores

tripler DC/DC converter can achieve 4500 footprint

reduction and 400 higher efficiency, as shown in Fig. 30.
IV-2. Two-Stage isolated DC/DC:

The 48V input DC/DC for high-end server and telecom

applications requires higher voltage devices on the primary
side and a transformer for isolation. To get fast dynamic
response and regulation performance, the PWM type power
conversion is preferred, whereas the efficiency and
switching frequency is limited by the presence of the
leakage inductances of the transformer. In order to achieve
acceptable efficiency, lower switching frequencies, around
200 300 KHz, are normally adopted. Thus the size of the
transformer and its passive components are bulky and the
transient responses are slow. Excessive output capacitors
are necessary to satisfy the dynamic transient requirement.
In general, the isolated 48V DC/DC is normally customized
design with higher cost, while its footprint and power
density are significantly lower than that of the non-isolated
POL converters.
First stage

Second stage

Fig. 31. Proposed two-stage solution

To leverage the 48V isolated DC/DC with standard high

frequency non-isolated POL converter techniques, a
superior two-stage approach was proposed [31], as shown in
Fig. 31. The first stage utilizes a simple inductorless
"DC/DC transformer operating at 1MHz switching
frequency by adopting the resonant switching to minimize
switching losses. The second stage employs the multi-phase
buck capable of operating at multi-Mega Hertz, taking
advantage of the already established infrastructure for lowvoltage POL converters. Fig. 32 shows the two-stage
prototype for the 48V power pod used in the server. Due to
the MHz switching frequency in the second stage, the
passive components can be greatly reduced. Table I lists the
comparison between the CPES two-stage prototype and the
industry single stage practice in Fig. 24(b), Based on the
reduction of passive components, the power density of the
power pod can be increased to around 150%. It is also
apparent that since the output capacitors are significantly

Efficiency Compariso
90

mt~ip

X1 _ I I =E=.
l
l
=_

=~ ~ ~ ~:7 88

~~~~86r

Cureh80ou -1

,urrent-Tripler~~
~~~~~8

-ustomnized C,
Transforme

(a)

10

20

30

40

50

60

Load [A]

70

80

90 100 110 120

(b)

Fig. 30. (a) 300 KHz hardware of the proposed ZVS current tripler,
(b) efficiency comparison with state-of-the-art

Fig. 32. 130W two-stage power pod prototype for server

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TABLE I

ThE COMPARISON 3ETWEEN SIN=-STAGE AND T 0-STACE

Sw itching

frequency
Indusrr
Practice

300kHz

CPES

1
-stage:
3OOkHz,
2 d stage-

Prototype

1M1Hz

one

Ti ansfoirmei
Philips EI32

Capacito-

PhilipUS
X
El2r

5nL
l F
Tantalum

.t

V1isv
THLP-

4270uF
ESRE

Philips E 52?505D
1 XH

54%

R,edtion

Inductor

(a)

75%

90%

reduced, the two-stage approach is less costly than the

single-stage approach. This architecture has been quickly
adopted by the industry and used in the current products.
IV-3. Intermediate Bus Architecture (IBA) and Bus Converter:

With the proliferation of low-voltage, high-current

microprocessors/DSPs and high-voltage analog devices on a
single circuit board, the number of different voltages
encountered has mushroomed. All these voltages share a
common ground so that it is unnecessary to use an isolated
transformer for each of these loads, respectively. Therefore,
the two-stage concept aforementioned was extended to the
sub-system level, as shown in Fig. 33, in which an isolated
bus converter steps down the 48V to an intermediate bus
voltage to feed all the non-isolated point-of-load converters
(POL) in the same board. This concept has been adopted by
industry and is becoming a mainstream for high-end server
and telecommunication applications, because it is more
cost-effective, more flexible in terms of system structure.

(c)

Fig. 34. Proposed inductor-less resonant FB DC/DC transformer

shown in Fig. 35, for the INTEL Pentium processor. This

was quickly adopted by the industry. The VR is
designed to operate at around 300 KHz and the control
bandwidth is around 50 KHz. It is well known that the
switching frequency can be increased to reduce the output
capacitance. However, the efficiency of today's single stage
suffers at higher switching frequencies. As shown in Fig. 36,
the major loss factors are the switching losses and the body
diode losses.
concept

18V

(70demm I

FPGAI

AV-1 2V

ASC

,=
uP

Fig. 33, Two-stage architecture

5V

viAv

Fig. 35, State-of-the-art VR solution: Multi-phase Buck

IBA

To minimize the size and cost of these bus converters,

CPES proposed inductor-less bus converter family with
ZVZCS switching behavior through the resonant between
the transformer leakage inductor and output capacitor [32].
These proposed topologies can double the power capability
compared with state-of-the-art products. As an example,
Fig. 34(a) shows the full-bridge version of the proposed
inductor-less bus converter family. Fig. 34(b) and (c) shows
the 800 kHz 500W bus converter prototype with 96%
efficiency at full load.
V. HIGH FREQUENCY HIGH CURRENT DENSITY NONISOLATED POINT-OF-LOAD (POL) CONVERTERS VRs
--

In 1997, CPES proposed a multi-phase buck converter,

as

as

OD0

-----

ILO

.-0-

--g-

|------------------

S ------------ 3--------------

------------| l------g----1MHz

Output Current

(a)

(b)

Fig. 36. Issues of single stage 12V VR at higher switching

frequency, (a) efficiencies, (b) Loss breakdown comparison

V-i. 1MHz ZVS Self-Driven Single-stage VRs:

From the loss breakdown in Fig. 36, the major factors

affecting circuit efficiency at 1MHz are switching loss, body
diode losses and gate driving loss.

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BIEL k 2 nd Sae
MulthAs

Voltage step-down converter

Ql1

imxi

4C
300-500KHz

Fig. 37. Proposed ZVS self-driven full bridge Buck

To minimize the aforementioned high frequency losses, a

novel self-driven dc/dc converter for non-isolated 12-V VR
was proposed, as shown in Fig. 37 [33]. ZVS was realized
all the MOSFETs. By adding a transformer, the
for
proposed topology extends its duty cycle so that both the
switching loss and body diode reverse recovery loss are
further reduced. This innovative self-driven concept
eliminates the need for synchronous rectifier drivers which
saves cost and driver loss. In addition, self-driven scheme
reduces the body diode conduction losses. Furthermore, the
magnetic integration has been realized to merge the output
inductor into the transformer to further reduced the size. All
of these benefits have been demonstrated in a 1MHz 100A
1U 12V VRM prototype shown in Fig. 38(a). Compared to
the conventional Buck design, the proposed topology can
elevate the efficiency by 6% at 1MHz switching frequency
with the same active component setup, as shown in
Fig.38(b).

90

90v
--4 pliase buck

82

rf E _

(a)

8~~~~0lo

8~~~~~~82
i i ii ! i
30

50

70

90o

.10

30

lo(A)

(b)

Fig. 39. The structure of the two-stage approach in [34]

(a)

(b)

Fig. 40. Demonstration of the two-stage 12V VR

(a) Hardware, (b) efficiency comparison

stage counterpart.
The conventional Buck converter was employed for the
first stage initially, as shown in Fig. 39. It was designed to
run at low switching frequency, e.g. 200-300 KHz, to attain
high efficiency. However, this low switching frequency
makes the first stage relatively large in size. Subsequently, a
magnetic-less DC/DC converter was developed by adopting
the switching capacitor technology [36]. Because no
magnetic component is required, it can substantially boost

Fig. 38. Demonstration of the proposed DC/DC in 1U IOOA 12V VRM

(a) Hardware, (b) efficiency comparison

Thought the proposed self-driven topology is compelling,

the duty cycle loss induced by the transformer leakage
inductor is one inherent limitation for higher than 1 MHz
operation. Theoretical analysis reveals that the gain of this
topology is diminishing with switching frequency increasing
beyond 1MHz.
Thereby, a two-stage approach shown in Fig. 39 is
proposed in [34]. The first stage can be designed at relatively
low switching frequency to step down the input voltage from
12V to around 5V. With the lower input voltage, the
switching losses and reverse recovery losses of the second
stage, which are proportional to the input voltage, are
dramatically reduced. Therefore, it was demonstrated that
the second stage switching frequency can be pushed to
2MHz to achieve 350 kHz bandwidth at 83% efficiency [34,
35]. The prototype in Fig. 40 clearly shows that the twostage approach can eliminate the output electrolytic
capacitor entirely together with a 2% efficiency
improvement over the single stage solution. This is achieved
with a switching frequency is 4 times higher than the single

/YK2cm

5.2cm

cm

4cm

Fig. 41. Size comparison between voltage divider and Buck

the power density of the first stage up to 1KW/inch3. The

proposed first stage with fixed 2:1 conversion ratio is
essentially serves as a voltage divider. It can achieve 98%
efficiency with 12V or even higher input voltage. Fig. 41
shows the comparison between the buck and voltage divider
designs for the first stage.
Other than high power density, the proposed voltage
divider can achieve ultra-high efficiency in the whole load
range with capability to handle over load conditions. By
adapting the switching frequency to the load, 98-99%

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efficiency in whole load range has been demonstrated in a

70W prototype design as shown in Fig. 42. Even with
100% overload, the circuit can maintain 95.50 efficiency.
1 00%

98%
96%Xi -iXX XX 111
94%
lv 90%

6'o

8 8 O/

86%
84 g1

1.

1.0

Io (A)

DCM, Vo=0.9V

1 0
> a

100. 0
>

aCM, Vo=1.2v.

Fig. 45. Efficiency improvement from two-stage on CPU VR

lili
E

M 1222X
M T T g M - _199l__
-1--l- WWW LI
E E El E B R .Xm TT
lM
--l 2

l/

84% l
82%
80%=
0. 1
|E

-----------1--1----------------1--

-'

82

I I

I
variable frequency
l|
I
2
92% I-W2*fixed frequency
A - Over power
m m X X X m m 'm -IIm
-111
i= i= i
X XX WmS

ll

*1-

.1I

90% _
88%
86% =

VI. CONCLUSION
This paper provides an overview of some of the important
design challenges and opportunities for power supplies,

___________

80

120

100

......

20

40

60
Po

(W)

Fig. 42. Experimental efficiencies of 70W prototype

V-3. Non-isolated System Two-stage Archiitecture:

By extending this two-stage approaich into system level,

the non-isolated IBA structure is prop()sed, as shown in Fig.
43, in which the voltage divider is useed as the non-isolated
bus converter. This architecture has been investigated for
the laptop with the configuration show,n in Fig. 44 [37].

Qi:sw to
i PL<4

-1k33VeD
ASIC

fNon

00

//~~~~
Un-regulated -6V

11

up

.-ii

Fig. 43. Proposed non-isolated system two-stage architecture

54W

LYaj7LD0

16W

18W

Fig. 44. Proposed system two-stage powe ,rarchitectureforlaptop

Detailed analysis and experim[ental results have

demonstrated that this architecture cz achieve 4500O total
inductor size reduction, 3500 total calpacitor size reduction
and 700 total cost reduction for major IVRs inside the laptop
Furthermore, the proposed two-sta ge architecture can
improve the light load efficiency for zall down-stream VRs,
which is critical to the battery life of the laptop. As an
example, Fig. 45 shows 1-2% efficie ncy gain on the CPU
VR at half load power and below.

pn

specifically using the example of a generic distributed

power system for computer server, telecom and network
applications.
First, the effects of mutual and self-paraitics of the filter
capacitors and inductors on the performance of EMI filter
are presented. Techniques for cancellation of both mutual
parasitics and self-parasitics are introduced. Specifically,
mutual coupling between inductors and capacitors as well
as coupling between two capacitors can be minimized.
Among the self-parasitics, the ESL of capacitors and the
winding capacitance of the filter inductors are identified
most detrimental to both DM and CM noises. The
unwanted effects of self-parasitic can be neutralized by
circuit means. The proposed technologies are proven by
theory and verified by experiments. It is demonstrated that,
EMI filter's HF performance can be greatly improved by
applying proposed methods in practice.
To achieve higher power density of front-end converter, it
1is essential to using high switching frequency techniques to
reduce passive component size. In the PFC stage, it is found
that the impact of switching frequency to EMI filter size
reduction is realized when the switching frequency is
pushed beyond 400 kHz. The switching frequency between
150kHz to 400kHz should be avoid since the EMI filter
size could be even larger than that at 70KHz due to the
EMI regulation that specifies noise level from 150 KHz to
30MHz.
Besides the reduction on EMI filter and PFC inductor, it is
essential to reduce the size of bulk capacitor for hold up
time requirement. It is found that the LLC resonant
converter offer special advantage for this application. It can
work with wide input range without sacrificing the
conversion efficiency at the normal operation condition.
Furthermore, smaller switching loss allows LLC converter
to operate at considerably higher switching frequency while
maintaining high efficiency. A prototype LLC converter
operated at 1 MHz was demonstrated with 76W/in3 power
density.
System power density was further improved by means of
integration using IPEM concept. Modular and integrated
approach makes the system layout easy and manufacturing
process more automated. Furthermore, it was shown that
circuit interconnect parasitics were significantly reduced,

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thus further improving converter efficiency and reducing

components stresses.
Products in the area of isolated and non-isolated point-ofload converters are fiercely competitive. The major driving
forces are cost, efficiency and power density. Design
challenges for high-frequency, high-density POLs involve
innovative circuit means of reducing the primary side
switching losses and conduction losses as well as the
secondary side synchronous rectifier body diode conduction
losses, reverse recovery losses, drive losses, and conduction
losses. Packaging and thermal management are equally
important. Some of the important recent developments are
presented. A novel zero-voltage-switching (ZVS) currentTripler converter was presented which offers great
advantages compared with the popular current double
configuration especially for low voltage and high current
applications. A novel self-driven ZVS full bridge topology
was introduced with significant saving of driver losses,
switching losses, and body diode losses for isolated and
non-isolated DC/DC converters. One of the potential
applications is for powering the next generation of
microprocessors. Prototype hardware is demonstrated
operating at 1MHz 12V with an efficiency 6% above the
comparable multi-phase Buck topology used in today's
VRM design. Other than the topological innovations, CPES
also proposed two-stage power architectures to further
improve the system performance for isolated and nonisolated applications. Prototypes were developed to
demonstrate significant improvements in efficiency, power
density as well as potential cost saving compared to the
state-of-the-art.
REFERENCE
[1] Milan.M Jovanovic "Technology Drivers and Trends for Power
Supplies in Computer/Telecom Applications", IEEE APEC'2006,
Plenary Session (presentation)
[2] Shuo Wang, Fred C. Lee, D. Y. Chen and W. G. Odendaal, "Effects
of Parasitic Parameters on EMI Filter Performance," Power
Electronics, IEEE Transactions, Volume 19, Issue 3, May 2004, pp.
869- 877.
[3] Shuo Wang, Fred C. Lee and W. G. Odendaal, "Characterization and
Parasitic Extraction of EMI Filters Using Scattering Parameters,"
Power Electronics, IEEE Transactions, Volume 20, Issue 2, March
2005, pp. 502 - 510.
[4] Rengang Chen, J. D. van Wyk, Shuo Wang and W. G. Odendaal,
"Improving the Characteristics of Integrated EMI Filters by
Embedded Conductive Layers," Power Electronics, IEEE
Transactions, Volume 20, Issue 3, May 2005, pp. 611 - 619.
[5] J. D. van Wyk, Fred C. Lee, Zhenxian Liang, Rengang Chen, Shuo
Wang and Bing Lu, "Development of Some Technologies for
Integration in Power Electronics Systems," Power Electronics, IEEE
Transactions, Volume 20, Issue 3, May 2005, pp. 523 - 536.
[6] Shuo Wang, Fred C. Lee and W. G. Odendaal, "Characterization,
Evaluation and Design of Noise Separator for Conducted EMI Noise
Diagnosis," Power Electronics, IEEE Transactions, Volume 20,
Issue 4, Jul. 2005, pp. 974-982.
[7] Shuo Wang, Fred C. Lee and W. G. Odendaal and J. D. van Wyk,
"Improvement of EMI Filter Performance with Parasitic Parameter

Cancellation," Power Electronics, IEEE Transactions, Volume 20,

Issue 5, Sept. 2005, pp. 1221-1228.
[8] Shuo Wang, Rengang Chen, J. D. van Wyk, Fred C. Lee and W. G.
Odendaal, "Developing Parasitic Cancellation Technologies to
Improve EMI Filter Performance for Switching Mode Power
Supplies," Electromagnetic Compatibility, IEEE Transactions,
Volume 47, Issue 4, Nov. 2005, pp. 921- 929.
[9] Shuo Wang, Fred C. Lee and W. G. Odendaal, "Cancellation of
Capacitor Parasitic Parameters for Noise Reduction Application,"
Power Electronics, IEEE Transactions, accepted to appear in 2006.
[10] Shuo Wang, Fred C. Lee and J.D. van Wyk, "Inductor Winding

[11]
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Capacitance Cancellation Using Mutual Capacitance Concept for

Noise Reduction Application," Electromagnetic Compatibility, IEEE
Transactions, accepted to appear in 2006.
Shuo Wang, Fred C. Lee and J.D. van Wyk, "Design of Inductor
Winding Capacitance Cancellation for EMI Suppress," Power
Electronics, IEEE Transactions, under review.
Rengang Chen, J.D. van Wyk, Shuo Wang and W.G. Odendaal,
"Planar Electromagnetic Integration Technologies for Integrated EMI
Filters," in Proc. IEEE Industry Applications Conference, 12-16, Oct.
2003, Volume 3, pp. 1582 -1588.
Fu-Yuan Shih; Chen, D.Y.; Yan-Pei Wu; Yie-Tone Chen, "A
procedure for designing EMI filters for AC line applications,"
Power Electronics, IEEE Transactions on, Volume: 11 Issue: 1, Jan.
1996 Page(s): 170 -181
Ting Guo; Chen, D.Y.; Lee, F.C., "Separation of the common-modeand differential-mode-conducted EMI noise" Power Electronics,
IEEE Transactions on, Volume: 11 Issue: 3, May 1996 Page(s): 480 488
Lu, B.; Dong, W.; Wang, S.; Lee, F.C.; "High frequency
investigation of single-switch CCM power factor correction
converter", in Proc. IEEE APEC 2004, pp. 1481 - 1487
Shuo Wang; Lee, F.C.; Odendaal, W.G.; "Single layer iron powder
core inductor model and its effect on boost PFC EMI noise", in
Proc. IEEE PESC 2003, Page(s):847 - 852
Bing Lu, Wei Dong, Qun Zhao, F.C. Lee, "Performance Evaluation
of CoolMOSTm and SiC Diode for Single-phase Power Factor
Correction Applications," in Proc. IEEE-APEC 2003', pp.651-657
Y. Jang; M.M. Jovanovic, D.L. Dillman, "Hold-up time extension
circuit with integrated magnetics,", in Proc. IEEE APEC 2005. pp.
219 - 225
Y. Xing; L. Huang; X. Cai; S. Sun; "A combined front end DC/DC
converter,", in Proc. IEEE APEC 2003 , pp. 1095 - 1099
B. Yang, F.C. Lee, A.J. Zhang, G. Huang, "LLC resonant converter
for front end DC/DC conversion," in IEEE-APEC 2002, pp. 11081112
G. Ivensky, S. Bronstein, S. Ben-Yaakov, "Approximate analysis of
the resonant LCL DC-DC converter," in IEEE Electrical and
Electronics Engineers in Israel, 2004. Proceedings, pp. 44-47
B. Lu, W. Liu, Y. Liang, F. C. Lee, J.D. van Wyk, "optimal design
methodology for LLC resonant converter", in Proc. IEEE-APEC
2006, pp.533-538
J.D. van Wyk, F.C. Lee, D. Boroyevich, Z. Liang; K. Yao, "A future
approach to integration in power electronics systems," in Proc. IEEEIECON '03. Volume: 1, pp. 1008-1019
F.C. Lee, J.D. van Wyk, D.Boroyevich, G. Lu; Z. Liang; P.Barbosa,
"Technology trends toward a system-in-a-module in power
electronics," Circuits and Systems Magazine, IEEE , Volume: 2
Issue: 4 , 2002, Page(s): 4 -22
Pedro Alou, Jose A. Cobos, et al., "A New Driving Scheme for
Synchronous Rectifiers: Single Winding Self-Driven Synchronous
Rectification," in IEEE Transaction on Power Electronics, Vol. 16,
No. 6, Nov. 2001, pp. 803-811.
Y. Ren, M. Xu, D. Sterk and F.C. Lee, "1MHz Self-Driven ZVS
Full-Bridge Converter for 48V Power Pods," in Proc. IEEE- PESC
2003, Page(s): 1801- 1806.

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[27] Ming Xu, Yuancheng Ren, Jinghai Zhou, Lee, F.C.; "1MHz SelfDriven ZVS Full-Bridge Converter for 48V Power Pod and DC/DC
Brick" IEEE Transaction on Power Electronics Volume: 20, Issue: 5
, September 2005, Pages:997 - 1006
[28] D. Sterk, M. Xu, Y. Ren and F.C. Lee, "Novel Integrated
Transformer Winding Scheme for Self-driven ZVS Interleaved
Asymmetrical Half-Bridge for Telecommunications Quarter Brick"
in Proc. IEEE APEC 2004, pp.912-918
[29] Y. Panov and M. Jovanovic, "Design and Performance Evaluation of
Low-Voltage/High-Current DC/DC On-Board Modules," IEEE
Transactions on Power Electronics, Volume: 16 Issue: 1,Jan.2001, pp.
26 -33.
[30] Ming Xu, Jinghai Zhou, Lee, F.C.; "A current-tripler dc/dc
converter" IEEE Transaction on Power Electronics Volume: 19
, Issue: 3, May 2004, Pages:693 - 700
[31] Y C.Ren, Ming Xu, Gary Yao, F C.Lee "Two-stage 48V power pod
exploration for 64-bit microprocessor" in Proc. IEEE APEC'2003,
Pages: 426 - 431
[32] Yuancheng Ren, Ming Xu, Lee, F.C.; "A Family of High Power
Density Un-regulated Bus Converters", IEEE Transaction on Power
Electronics , Volume: 20 , Issue: 5 , September 2005, Pages: 1045 1054
[33] Jinghai Zhou, Ming Xu, Julu Sun, Lee, F.C.; "A Self-driven Softswitching Voltage Regulator for Future Microprocessor", IEEE
Transaction on Power Electronics Volume: 20, Issue: 4, July 2004,
Pages:928 - 936
[34] Yuancheng Ren, Ming Xu, Kaiwei Yao,Yu Meng, Lee, F.C.; "Twostage Approach for 12V VR", IEEE Transaction on Power
Electronics,, Volume: 19, Issue: 6, Nov. 2004, Pages: 1498 - 1506
[35] Yuancheng Ren, Ming Xu, Kaiwei Yao, Lee, F.C.; "Analysis of the
Power Delivery Path from 12V VR to Microprocessors", IEEE
Transaction on Power Electronics, Volume: 19, Issue: 6, Nov. 2004,
Pages:1507- 1514
[36] Ming X.;Julu Sun, and Lee, F.C.; "Voltage Divider and its
Application in Two-stage Architecturess", in Proc. IEEE
APEC'2006, Pages: 499 - 505
[37] Julu Sun, Ming Xu, and Lee, F.C.; "High Power Density, High
Efficiency System Two-stage Power Architecture for Laptop
Computers", in Proc. IEEE PESC'2006

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