EEDG/CE 6301: Advanced Digital Logic

Mehrdad Nourani
Dept. of EE
Univ. of Texas at Dallas

Session 03
Overview of HDL-for-Synthesis

Parametric Coding in VHDL

Parametric Coding in VHDL

The concept of generics is often used to
parameterize components.
Example 5.1: 32-bit 2-input MUX:
--Example 5.1: 32-bit input MUX
library IEEE;
use IEEE.std_logic_1164.all;
entity mux32 is
generic(n : natural := 31);
port(
x : in std_logic_vector (n downto 0);
y : in std_logic_vector (n downto 0);
s : in std_logic;
f : out std_logic_vector (n downto 0));
end entity mux32;
architecture behavior of mux32 is
begin -- behavior -- no process needed with concurrent statements
f <= y when s='1' or s='H' else x;
end architecture behavior; -- of mux32
4

Example 5.1 (contd)

Schematics after

synthesis and design

optimization:

The generic statement

allows parametric
settings so that the
design could be compiled
for desired values.

Parametric Loop in VHDL

Generic statement required in entity.
Loop is declared using for-loop statement
Example 5.2: VHDL code for a 32-bit adder:
-- Example 5.2: 32-bit input adder
library IEEE;
use IEEE.std_logic_1164.all;
entity add32 is
generic(n : natural := 31);
port (a
: in std_logic_vector (n downto 0);
b
: in std_logic_vector (n downto 0);
cin : in std_logic;
sum : out std_logic_vector (n downto 0);
cout : out std_logic);
end entity add32;
architecture behavior of add32 is
begin -- behavior
adder: process
variable carry : std_logic; -- internal
variable isum : std_logic_vector(n downto 0); -- internal
begin
carry := cin;
for i in 0 to n loop
isum(i) := a(i) xor b(i) xor carry;
carry := (a(i) and b(i)) or (a(i) and carry) or (b(i) and carry);
end loop;
sum <= isum;
cout <= carry;
end process adder;
end architecture behavior; -- of add32

Example 5.2 (contd)

Schematic after synthesis and design optimization:

Parametric Coding in VHDL (contd)

Iterative commands declared using for-generate
statements
Makes copies of concurrent statements

Example 5.3: 32-bit 2-input MUX with forgenerate:

--Example 5.3: 32-bit input MUX with for-generate statements
library IEEE;
use IEEE.std_logic_1164.all;
entity mux32_it is
generic(n : natural := 31);
port(
x : in std_logic_vector (n downto 0);
y : in std_logic_vector (n downto 0);
s : in std_logic;
f : out std_logic_vector (n downto 0));
end entity mux32_it;
architecture mux32_it_arch of mux32_it is
begin
gen1: for i in 0 to n generate
f(i) <= (x(i) and not s) or (s and y(i));
end generate gen1;
end architecture mux32_it_arch;

Example 5.3 (contd)

The generate statement
combines concurrent
statements with a looping
capability

Schematics after synthesis

and design optimization ->
The same gate level
structure achieved as in
Example 5.1
9

Hierarchical Design in VHDL

10

Hierarchical Design in VHDL

VHDL supports design by creating modules of circuit
components that can be used in another design
Components and port mapping used in top level design

a3 b3

a2 b2

a1 b1

a0 b0

module

module

module

module

module

&

11

Example 6: A hierarchical Design

--Example 6: A hierarchical design
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_components.all;
entity module is
port ( A, B : in std_logic;
Z : out std_logic);
end module;
architecture module_arch of module is
begin
Z <= (A and not B) or (not A and B);
end module_arch;
----------------------------------------------------------------------------TOP LEVEL MODULE
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_components.all;
ENTITY hier IS
PORT ( a0, b0, a1, b1, a2, b2, a3, b3: IN
o : OUT
std_logic ) ;
END hier;
ARCHITECTURE hier_arch OF hier IS
component module
port ( A, B : in std_logic;
Z : out std_logic);
end component;
SIGNAL p, q, r, s: std_logic;
BEGIN
M_1 : module port map( A => a0, B => b0, Z
M_2 : module port map( A => a1, B => b1, Z
M_3 : module port map( A => a2, B => b2, Z
M_4 : module port map( A => a3, B => b3, Z
o <= p and q and r and s;
END;

module

r
a3 b3

a2 b2

a1 b1

a0 b0

module

module

module

module

std_logic;

&
=>
=>
=>
=>

p);
q);
r);
s);

o
12

Example 6: Synthesis
Schematics design after
Synopsys synthesis,
design optimization and
compilation:
The module in this
design is an XOR gate
Each module would be
optimized alone
Does not necessarily
optimize the whole
design altogether
13

Sequential Modeling

14

Modeling Flip-Flops
D-flip-flop behavior
-Example 7.1: D-flip-flop with reset
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dff is
port( d:in std_logic;
clk,rst:in std_logic;
q:out std_logic);
end dff;
architecture dff_arch of dff is
begin
process(rst, clk)
begin
if rst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d; --rising edge triggered
end if;
end process;
end dff_arch;

15

Negative Edge Triggered D-Flip-flop

VHDL Code:
-- Example 7.2 Negative Edged Triggered DFF
library ieee;
use ieee.std_logic_1164.all;
entity dflipn is port (
d,clk: in std_logic;
q: out std_logic );
end dflipn;
architecture dflipn_arch of dflipn is
begin
process(clk)
begin
if (clk'event and clk = '0') then
q <= d; -- set the changes to the negative edge of clock
end if;
end process;
end dflipn_arch;
16

Importance of Sensitivity List

17

Process and Sensitivity List

A process is a wrapper for sequential statements.
Sequential statements model combinational or synchronous logic (or
both).
Statements within a process are executed sequentially.
Beware! Signal assignments are BOTH concurrent and sequential.

A process is concurrent with other concurrent statements in an

architecture.
An architecture can have multiple processes.
Signal changes in the sensitivity list cause the process to "run" or
be evaluated.
All sequential statements in the process are "executed".
Variables are updated as statements are sequentially "executed".
Signal updates are scheduled as statements are sequentially
"executed".
Signal updates occur when the process is suspended (finished).

A common error is to think that signal updates take place when a

sequential statement is executed.
18

Importance of Sensitivity List

The signal sensitivity list is used to specify
which signals should cause the process to be reevaluated.
Whenever any event occurs on one of the
signals in the sensitivity list, the process is reevaluated.
A process is evaluated by performing each
statement that it contains. These statements
(the body of the process) appear between the
begin and end keywords.
Synthesis programs do not care about
sensitivity list but gives you a warning if they
are not complete.
19

Example 8: Importance of Sensitivity List

If d input is added to the sensitivity list of D-Flip-Flop
(Example 7.1), there would just be an overhead for
simulation, but no false behavior for simulation or
synthesis would be observed if it is not on the list.

This behavior is because of the rising-edge detection of D-FlipFlop.

Transparent latch should have the d input added to

the sensitivity list, as change in input should be
reflected at output when en is high.
VHDL Code for Latch with input d on sensitivity list:
--Example 8.1: Transparent Latch
library ieee;
use ieee.std_logic_1164.all;
entity mylatch is
port( d:in std_logic;
en:in std_logic;
o:out std_logic);
end mylatch;

architecture mylatch_arch of mylatch is

begin
Latch_Data:process(en,d)
--sensitivity list
begin
if (en = '1') then
o <= d;
-- If en = 0, then o keeps its old value.
end if;
end process Latch_Data;
end mylatch_arch;

20

Example 8 (contd)
For combinational logic or latches you have to
take more care with the sensitivity list.
If d input is not on sensitivity list of the latch,
-> wrong functionality in simulation.
VHDL code of a latch with incorrect behavior:
--Example 8.2: Latch with incorrect behavior
library ieee;
use ieee.std_logic_1164.all;
entity mylatch is
port( d:in std_logic;
en:in std_logic;
o:out std_logic);
end mylatch;

architecture mylatch_arch of mylatch is

begin
Latch_Data: process(en)
--sensitivity list
begin
if (en ='1') then
o <= d;
-- If en = 0, then o keeps its old value.
end if;
end process Latch_Data;
end mylatch_arch;

21

Example 8: Synthesis & Test bench

Synthesis of both example 8.1 and 8.2 codes
look alike!

VHDL Code for Test bench:

--Test bench for Example 8: Latch
library IEEE;
USE IEEE.std_logic_1164.all;
entity tbmylatch is
end tbmylatch;
architecture tbmylatch_arch of tbmylatch is
component mylatch
port( d:in std_logic;
en:in std_logic;
o:out std_logic);
end component;

signal in_d, in_en, out_o: std_logic := '0';

begin
imylatch:mylatch port map(d=>in_d, en=>in_en, o=>out_o);
in_en<= not in_en after 10 ns;
in_d<='0','1' after 25 ns, '0' after 35 ns;
end tbmylatch_arch;
configuration cf_mylatch of tbmylatch is
for tbmylatch_arch
for imylatch:mylatch
use entity WORK.mylatch (mylatch_arch);
end for;
end for;
end cf_mylatch;

22

Example 8: Simulation
Simulation results of Example 8.1:

Correct

Simulation results of Example 8.2:

Incorrect functionality
23

Modeling Sequential FSM

24

Sequential Logic Using VHDL

Finite State Machine (FSM)
A circuit that has defined states and can switch
between them if certain conditions exist

Moore Machine
A Moore machine has output(s) that depend on
state only
The FSM has the output(s) written in the state itself

Mealy Machine
A Mealy machine has output(s) that depend on both
the state and input(s)
The FSM has the output written on edges
25

Moore Machine
State Diagram:
Transition Table:

0
S0/0
0

Present
State

Next State

Output
(Z)

x=0 x=1
1

S1/1

S2/1

1
S3/0

S0

S0

S2

S1

S0

S2

S2

S2

S3

S3

S3

S1

26

Example 9: Moore Machine

VHDL Code:
--Example 9: Moore machine
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity moore is
port( x, clk:in bit;
Z:out bit);
end moore;
architecture moore_arch of moore is
type state_type is (S0, S1, S2, S3);
signal current_state, next_state: state_type;
begin
--process to hold synchronous elements (flip-flops)
SYNCH:process
begin
wait until clk'event and clk='1';
current_state <= next_state;
end process;

--process to hold combinational logic

COMBIN:process (current_state, x)
begin
case current_state is
when S0 =>
Z <= '0';
Output is defined
if x='0' then
outside if-then-else
next_state <= S0;
statement
else
next_state <= S2;
end if;
when S1 =>
Z <= '1';
if x='0' then
next_state <= S0;
else
next_state <= S2;
end if;
when S2 =>
Z <= '1';
if x='0' then
next_state <= S2;
else
next_state <= S3;
end if;
when S3 =>
Z <= '0';
if x='0' then
next_state <= S3;
else
next_state <= S1;
end if;
end case;
end process;
end moore_arch;

27

Example 9: Moore Machine (contd)

Schematics of Synthesized logic:

28

Mealy Machine
State Diagram:
Transition table:

0/0
S0
0/0

Present
State

1/1

Next State
x=1

S1

S2

1/1

1/0
S3

0/1

Output
(Z)

x=0 x=1 x=0

S0

S0

S2

S1

S0

S2

S2

S2

S3

S3

S3

S1

0/0

29

Example 10: Mealy Machine

VHDL Code:
--Example 10: Mealy machine
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mealy is
port( x, clk:in bit;
Z:out bit);
end mealy;
architecture mealy_arch of mealy is
type state_type is (S0, S1, S2, S3);
signal current_state, next_state: state_type;
begin
--process to hold synchronous elements (flip-flops)
SYNCH:process
begin
wait until clk'event and clk='1';
current_state <= next_state;
end process;

--process to hold combinational logic

COMBIN:process (current_state, x)
begin
case current_state is
when S0 =>
if x='0' then
Z <= '0';
Output is defined
next_state <= S0;
inside if-then-else
else
statement
Z <= '1';
next_state <= S2;
end if;
when S1 =>
if x='0' then
Z <= '0';
next_state <= S0;
else
Z <= '0';
next_state <= S2;
end if;
when S2 =>
if x='0' then
Z <= '1';
next_state <= S2;
else
Z <= '0';
next_state <= S3;
end if;
when S3 =>
if x='0' then
Z <= '0';
next_state <= S3;
else
Z <= '1';
next_state <= S1;
end if;
end case;
end process;
end mealy_arch;

30

Example 10: Mealy Machine (contd)

Schematics of Synthesized logic:

31

Asynchronous Modeling

32

Asynchronous Design
An asynchronous circuit is one in which
synchronization is performed without a global
clock

Advantages:
Elimination of clock skew problems.
Average-case performance.
Adaptivity to processing and environmental
variations.
Component modularity and reuse.
Lower system power requirements.
Reduced noise.

33

Example 11: Asynchronous Design

Example 11: Design an asynchronous sequential circuit
with two inputs P (pulse) and R (reset), and a single
output Z that is normally 0. The output should be set to
1 whenever a 0 1, or 1 0 transition occurs on P,
and should be reset to 0 whenever R is 1
Flow Table (non-optimized)

34

Example 11: VHDL Code

--Example 11: Asynchronous modeling in VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity asyn is
port (
p,r: in std_logic;
z: out std_logic);
end asyn;
architecture asyn_arch of asyn is
type states is (s0, s1, s2, s3, s4, s5);
signal currentstate : states:= s0;
begin
state_trans: process(p,r)
begin
case currentstate is
when s0=>
if (p='0') and (r='0') then
currentstate<=s0;
z<='0';
elsif (p='0') and (r='1') then
currentstate<=s3;
z<='0';
elsif (p='1') and (r='1') then
currentstate<=s4;
z<='0';
else
currentstate<=s1;
z<='1';
end if;
when s1=>
if (p='0') and (r='0') then
currentstate<=s2;
z<='1';
elsif (p='0') and (r='1') then
currentstate<=s3;
z<='0';
elsif (p='1') and (r='1') then
currentstate<=s4;
z<='0';
else
currentstate<=s1;
z<='1';
end if;

when s2=>
if (p='0') and (r='0') then
currentstate<=s2;
z<='1';
elsif (p='0') and (r='1') then
currentstate<=s3;
z<='0';
elsif (p='1') and (r='1') then
currentstate<=s4;
z<='0';
else
currentstate<=s1;
z<='1';
end if;
when s3=>
if (p='0') and (r='0') then
currentstate<=s0;
z<='0';
elsif (p='0') and (r='1') then
currentstate<=s3;
z<='0';
elsif (p='1') and (r='1') then
currentstate<=s4;
z<='0';
else
currentstate<=s1;
z<='1';
end if;
when s4=>
if (p='0') and (r='0') then
currentstate<=s2;
z<='1';
elsif (p='0') and (r='1') then
currentstate<=s3;
z<='0';
elsif (p='1') and (r='1') then
currentstate<=s4;
z<='0';
else
currentstate<=s5;
z<='0';
end if;

when s5=>
if (p='0') and (r='0') then
currentstate<=s2;
z<='1';
elsif (p='0') and (r='1') then
currentstate<=s3;
z<='0';
elsif (p='1') and (r='1') then
currentstate<=s4;
z<='0';
else
currentstate<=s5;
z<='0';
end if;
end case;
end process state_trans;
end asyn_arch;

35

Example 11: Synthesis

Schematics of logic synthesis:

MUX not FF!

36

Parallelism and
Interaction Among Units

37

Parallelism and Interaction Among Units

VHDL concurrent statements allows parallelism
among units.
x y
--Example 12: Parallelism & Interaction
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_components.all;
-------------------------------------entity myand is
port ( A, B : in std_logic;
Z : out std_logic);
end myand;
architecture myand_arch of myand is
begin
Z <= A and B after 10 ns;
end myand_arch;
-------------------------------------LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_components.all;
entity myxor is
port ( A, B : in std_logic;
Z : out std_logic);
end myxor;
architecture myxor_arch of myxor is
begin
Z <= A xor B after 20 ns;
end myxor_arch;

--TOP LEVEL MODULE

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_components.all;
ENTITY mydesign IS
PORT ( x, y : IN std_logic ;
f, g : OUT
std_logic ) ;
END mydesign;
ARCHITECTURE mydesign_arch OF mydesign IS
component myand
port ( A, B : in std_logic;
Z : out std_logic);
end component;
component myxor
port ( A, B : in std_logic;
Z : out std_logic);
end component;
BEGIN
U_1 : myand port map( A => x, B => y, Z => f);
U_2 : myxor port map( A => x, B => y, Z => g);
END;

myand

Z
f

myxor

Z
g

38

Example 12: Synthesis

Schematic of Synthesis:

39

Example 12: Test Bench

Test bench:
--Test bench for Example 12
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_components.all;
entity tbmydesign is
end tbmydesign;
architecture tbmydesign_arch of tbmydesign is
component myand
port ( A, B : in std_logic;
Z : out std_logic);
end component;
component myxor
port ( A, B : in std_logic;
Z : out std_logic);
end component;
component mydesign
PORT ( x, y :in std_logic;
f, g :out std_logic);
end component;
signal in_x, in_y, out_f, out_g: std_logic;
begin
imydesign:mydesign port map(x=>in_x, y=>in_y, f=>out_f, g=>out_g);
in_x<='0';
in_y<='1';
end tbmydesign_arch;
configuration cf_mydesign of tbmydesign is
for tbmydesign_arch
for imydesign:mydesign
use entity WORK.mydesign(mydesign_arch);
end for;
end for;
end cf_mydesign;

40

Example 12: Simulation

Wave graph Simulation:
AND result available at 10 ns

XOR result available at 20 ns

Outputs observed at respective times

41

Implementing Memory in VHDL

42

Example 13: Memory Module in VHDL

--Example 12: A 4*4 RAM module
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SRAM is
generic(
width:
integer:=4;
depth:
integer:=4;
addr:
integer:=2);
port( Clock:
in std_logic;
Enable:
in std_logic;
Read:
in std_logic;
Write:
in std_logic;
Read_Addr:
in std_logic_vector(addr-1 downto 0);
Write_Addr:
in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out:
out std_logic_vector(width-1 downto 0)
);
end SRAM;
architecture behav of SRAM is

-- Write Functional Section

process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;

Write

Use of arrays

type ram_type is array (0 to depth-1) of

std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
-- Read Functional Section
process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- builtin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;

Read
43

Example 13: Synthesis

Schematics of logic synthesis:

44