FPGA Vision Using The NI LabVIEW
FPGA Vision Using The NI LabVIEW
Overview
With FPGA technology and the NI LabVIEW FPGA Module, you can perform high-speed field-programmable gate
array (FPGA) processing on images acquired from Camera Link cameras. FPGA processing is particularly useful in
applications that require low latency between acquisition and the processed image. This document provides an
overview of image processing on an FPGA, including typical use cases.
Table of Contents
1.
2.
Related Links
Preprocessing
Image transforms
Feature Extraction
Edges, lines, and corners
Image operators
Binary objects
Shading correction
Color
Bayer decoding
Measurements
Centroid
Filtering (smooth/sharpen)
Binary morphology
Area measurements
In addition to the LabVIEW graphical design environment, LabVIEW FPGA supports a feature for HDL IP integration
called Component-Level IP (CLIP). With CLIP, you can insert HDL IP into an FPGA target so VHDL code can
communicate directly with an FPGA VI. CLIP also facilitates communication between the FPGA and external circuitry
using existing HDL IP.
processing, which results in minimum system latency. You can send image information to the CPU for data storage or
image display after processing is complete.
Figure 1. All processing is performed in hardware on the FPGA. The CPU is free to perform other tasks, and system
latency is minimized to the transit time of the data through the FPGA.
Examples of this use case include high-speed sorting, eye-tracking and laser alignment.
Figure 2. Image acquisition and preprocessing are performed on the FPGA and image data is then passed to the
CPU. The CPU performs more complicated image analysis such as pattern matching and classification.
FPGA image processing is particularly useful in applications that require high-speed bit-level processing. The FPGA
receives image data and processes individual bits using a high-speed onboard clock (up to 100 MHz clock rate). You
perform data transfer and processing in hardware on a single clock cycle. You can break many vision algorithms into
multiple iterative tasks and then break those tasks into parallel operations on the FPGA.
Examples where this type of architecture can be applied include surface and web inspection applications, and optical
coherence tomography (OCT) applications.