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Technical Note: LPSDRAM Unterminated Point-to-Point System Design: Layout and Routing Tips
Technical Note: LPSDRAM Unterminated Point-to-Point System Design: Layout and Routing Tips
Introduction
Technical Note
LPSDRAM Unterminated Point-to-Point System Design:
Layout and Routing Tips
Introduction
Low-power (LP) SDRAM, including both low-power double data rate (LPDDR) and lowpower single data rate (LPSDR), devices require a well-designed environment, package,
and PCB, to maximize their performance for todays high-speed/low-power applications.
Designers can benefit from a set of proven layout and routing techniques for Mobile
designs using unterminated point-to-point interfaces. Derived from electronics theory
and Micron design experience, the guidelines in this technical note can enhance signal
integrity (SI) optimization in unterminated point-to-point systems.
This technical note provides guidance for the development of multilayer board designs.
It contains established system design recommendations to improve SI and reduce noise
for LPDDR and LPSDR devices in unterminated point-to-point and point-to-multipoint
systems.
The guidelines and examples in this technical note represent one of several acceptable
methods and may not be applicable for all unterminated point-to-point designs.
Background
Previous Micron technical notes have focused on design, layout, and simulation techniques focused on standard SDRAM designs. Refer to TN-46-11, Hardware Tips for
Point-to-Point System Design: Termination, Layout, and Routing and TN-46-14, DDR
SDRAM Point-to-Point Simulation Process.
The need for low power in LPSDRAM designs has influenced the adoption of programmable output drive strength and LVCMOS outputs. Though essential for LP designs,
providing a programmable drive to replace external termination presents some unique
design challenges. LVCMOS outputs eliminate the need for a Vref supply but require
near full-rail output transitions that can induce noise onto the DQ lines. The LPSDRAM
interface is either x16 or x32, effectively doubling the number of DQ that transition
during each cycle. The design of the memory signal environment can compensate for
these differences to produce a more robust design.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Microns production data sheet specifications. All
information discussed herein is provided on an as is basis, without warranties of any kind.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Data Point-to-Point
Controller
(custom)
Memory
(tristate)
TL Microstrip
507
0.48ns
Figure 2:
Memory
Apt ACDC = 3.474ns
Jitter = 39ps
2.16
1.66
1.15
0.65
0.14
-0.36
0.00
1.50
3.01
4.51
6.02
7.52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Controller
Apt ACDC = 3.631ns
Jitter = 31ps
3.00
2.16
1.32
0.48
0.36
1.20
0.00
Figure 4:
1.50
3.01
4.51
6.02
7.52
Controller
Apt ACDC = 3.547ns
Jitter = 35ps
2.02
1.57
1.12
0.68
0.23
0.22
0.00
1.50
3.01
4.51
6.02
7.52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Power Delivery
The LPSDRAM interface typically consists of either a x16 or a x32 data bus. Traditional
SDRAM devices are usually x4 or x8.
LPSDRAM devices use LVCMOS output signals that switch to near full-rail levels for each
transition. Traditional SDRAM uses SSTL-2 drivers with a reduced output-switching
voltage range.
Doubling the number of I/Os and increasing the output-switching voltage range for
LPSDRAM both contribute to SSO noise, particularly when full drive strength is selected
for the interface. Increased switching noise can also require additional decoupling to
filter the noise from the system.
The following examples illustrate how optimized power delivery can minimize SSO
noise.
The waveforms in figures 5 and 6 are the result of a simulation done for a x32 LPDDR
device on an unterminated mobile system.
The DQ bus is a 2-inch transmission line (Z0 = 50) with a 5pF load.
31 DQ act as aggressors, all running the same PRBS pattern.
The victim DQ runs a different PRB pattern.
The four DQS pads are sent a recurring 0101... pattern.
The data rate is 333 Mb/s (166 MHz).
The driver is set to full drive strength.
The impact of poor power delivery (running at 333 MHz) on the DQ eye diagrams is
shown in Figures 5.
Causes of poor power delivery include:
Long, narrow metal traces for supply voltages
Insufficient trace-routing spacing induces crosstalk
Poorly placed or insufficient decoupling capacitors
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Victim
2.70
2.70
1.98
1.98
1.26
1.26
0.54
0.54
0.18
0.18
0.90
0.90
0.00
1.20
2.40
3.60
4.80
0.00
6.00
1.20
2.40
3.60
4.80
6.00
The impact of good power delivery on the DQ eye when running at 333 MHz is
demonstrated in Figure 6.
Techniques for good power delivery include:
Achieving the best signal integrity in a system requires good designs for both trace
routing and power delivery. A well-designed interconnect can be marginalized by a
poorly designed power delivery mechanism. Maintaining low impedance for the power
delivery provides the best signal integrity.
Figure 6:
Victim
2.70
2.70
1.98
1.98
1.26
1.26
0.54
0.54
0.18
0.18
0.90
0.90
0.00
1.20
2.40
3.60
4.80
6.00
0.00
1.20
2.40
3.60
4.80
6.00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Decoupling
Adequate power decoupling on the PCB is necessary to prevent excessive Vdd noise and
the resulting memory errors in applications where power-supply draw can change by
magnitudes in a single clock cycle.
Optimal capacitor placement and values can be defined through simulation or creation
of a prototype. From this data, designers can determine the correct number of decoupling capacitors to use and their most advantageous placement. These factorsthe
number and location of capacitorsare of greater importance than the exact value of
each capacitor.
As a general guideline, select the lowest equivalent series inductance (ESL) capacitor
package suitable for your application. Use the highest capacitance available in that
package and place as many capacitors as possible in the design.
Place capacitors as close as possible to each corner of each LPDDR or LPSDR device.
Adjacent devices can share capacitors at the corners that fall between them. Backside
components must have their own capacitors. This distributed decoupling approach
minimizes capacitor ESL effects and localizes transient currents and returns.
See Micron technical notes TN-46-02, Decoupling Capacitor Calculation for a DDR
Memory Channel and TN-00-06, Bypass Capacitor Selection for High Speed Designs
for detailed decoupling discussions. Both are available on Microns Web site:
www.micron.com.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Signal 1
L1
0.7 mil
4.5 mil
L2Vss
1oz
6.5 mil
L3Vdd
1oz
30 mil
Signal 2
L4
5.0 mil
L5Vss
1oz
4.5 mil
0.7 mil
Notes:
Figure 8:
Signal 3
L6
1.
2.
3.
4.
5.
0.7 mil
L1
Signal 1
L2Vss
Vss
L3
Signal 2
L4
Signal 3
L5Vdd
Vdd
L6
Signal 4
4.5 mil
1oz
6.5 mil
1oz
30 mil
5.0 mil
1oz
4.5 mil
0.7 mil
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
S2
S3
S1
Notes:
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Signal Set
Signals
Data/Data strobe
DQ to DQ
DQ to DQS
DQS in a byte lane
to DQS in a different byte lane
DQ and DM
Adjacent address lines
Address lines
CAS#, RAS#, WE#, CS#, CKE
CK#-to-CK
CK# (or CK in group of two) to DQS line
Differential pair (CK, CK#) to any other signal
Address
Command/Control
Clock
Notes:
Spacing
Type
Min
Nom
Max
Unit
Notes
S1
S2
S1
8
8
12
12
mil
mil
mil
S2
S1
S2
S1
S1
S2
S2
8
6
6
6
12
12
12
15
12
mil
mil
mil
mil
mil
mil
mil
2
3
1. DQS signals are generally routed in the midst of related nibbles or bytes, so DQS-to-DQS
spacing is not relevant.
2. All CK and CK# signals lines should have differential characteristic impedance (Zdiff) of
100120.
3. Generally not an issue as the CK# and DQS lines are not adjacent.
Expandability
Refer to Micron component data sheets for NC, DNU, or RFU pins in lower-density
components that are used as upper-address pins in higher-density components. For
example, ball H3 is NC in the 128Mb (8 Meg x 16) LPSDRAM component; it is A12 in the
256Mb (16 Meg x 16) LPSDRAM component. Designers can increase design expandability by placing a 0 series resistor between the pin and the controller such that it can
be depopulated when switching to the lower-density component (shown in Figure 10 on
page 11). This approach makes it possible to reuse the PCB without significant redesign.
Figure 10:
Addr12
(most significant address)
07
10K7
Pin 36:
NC for 128Mb
A12 for 256Mb
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Routing
Though there are many signals on LPDDR or LPSDR components, most of them have
similar functionality and work together. Groups of I/O signals have one of four purposes:
to carry a binary address, to transmit or receive data, to relay a command to the device,
or to latch in address/data or a command.
The address group consists of row/column address and bank address pins. The
command group includes the row address strobe (RAS#), the column address strobe
(CAS#), and write enable (WE#). The control group includes chip select (CS#) and clock
enable (CKE). Each data group/lane contains 10 signals: the eight DQ (DQ[7:0]), the
strobe (DQS), and the data mask (DM). Devices with x8 bus widths have only one data
group, while x16 and x32 bus-width devices have two and four lanes, respectively.
To facilitate data lane routing, Micron recommends placing alternate, adjacent 10-line
data lanes on different critical PCB stackup layers. To decrease crosstalk, when data and
address/control tracks coexist on the same layer, they must be isolated from each other
by at least 20 mil. If possible, place data tracks on different layers from address and
control lanes.
Related functionality makes minimizing skew critical. This requires the signals of each
group to be routed to similar electrical lengths. Routing address lines together on the
same layer and isolating data lanes from the address, command, and control groups will
also help minimize skew.
Match trace lengths for the data group within 50 mil of each other to diminish skew;
serpentine traces (back and forth traces in an S pattern to increase trace length) can be
used to match lengths. In addition, some controllers require byte lanes to have matched
trace lengths. If the controller does not specify this, route byte lanes so that 500 mil is
the largest trace-length difference relative to the clock group trace length.
Serpentine trace patterns contribute the desired delay, but be aware that there is some
self coupling; that can change the propagation delay for a signal. Use simulations to validate timing.
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Point-to-Multipoint Systems
Clock Routing in Multiple LPDDR Devices
For LPDDR systems, match CK trace length to CK# trace length 20 mil and CK/CK#
trace lengths to DQS trace length 500 mil. If multiple clock pairs are transmitted from
the controller to components, all clock-pair traces should be equivalent within 20 mil.
Recommended LPDDR routing topology for clock pairs is shown in Figures 11 and 12.
If the trace lengths from split point to LPDDR components are less than 1in (2.5cm),
use a single 100120 resistor (Rt) at the split point (see Figure 11).
If the lengths from the split point to the DRAM devices are greater than 1in (2.5cm),
use two resistors located near the respective LPDDR components (see Figure 12).
These resistors are in parallel, so each Rt should be 200240 to keep the effective
resistance at 100120.
Figure 11:
DDR#2
DDR#1
CK
CK
CK#
Split point
CK#
RT
Length from
the split point
to DRAM device
is <1in (2.5cm)
Memory Controller/ASIC
13
Length from
the split point
to DRAM device
is <1in (2.5cm)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
DDR#2
DDR#1
CK
CK
CK#
RT
CK#
RT
Split point
Length from
the split point
to DRAM device
is >1in (2.5cm)
Notes:
2
Memory Controller/ASIC
Length from
the split point
to DRAM device
is >1in (2.5cm)
1. All CK and CK# signal lines have characteristic impedance (Z0) of 100120.
Match clock-pair traces to each signal trace in the address and command groups to
within 400 mil. If clock traces cannot be matched to the trace lengths of these groups
within 400 mil, then all clock trace lengths must be increased as a group. The longest-toshortest trace length difference must be 800 mil, so both longest and shortest traces
determine how much length must be added to all clock lines.
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
DDR
SDRAM
DDR
SDRAM
RS
DDR
SDRAM
Memory Controller/ASIC
Simulation
During the layout phase for a new or revised design, Micron strongly recommends simulating I/O performance at regular intervals. Optimizing an interface through simulation
can help decrease noise and increase timing margins before building prototypes. Issues
are often resolved more easily when found in simulation, as opposed to those found
later that require expensive and time-consuming board redesigns or factory recalls.
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Summary
Signal integrity, power delivery, and decoupling are all major concerns when designing
LPSDRAM applications.
Mobile LPSDRAM designs (LPDDR and LPSDR) provide an attractive alternative to traditional DRAM designs when used for mobile applications. The option to control the drive
strength to match the impedance of the memory bus enables removal of the termination
voltage (Vterm) and series termination resistors. Mobile LPSDRAM designs can be used
to reduce memory cost and power consumption in mobile applications.
Mobile applications, when properly designed and validated through simulations, can
realize superior functionality and stability.
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.
Revision History
Rev A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/08
Initial release.
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2008 Micron Technology, Inc. All rights reserved.