1 MHz to 8 GHz, 70 dB

Logarithmic Detector/Controller
AD8318
FEATURES

FUNCTIONAL BLOCK DIAGRAM

VPSI

ENBL

TEMP
SENSOR

TEMP

DET

DET

TADJ

GAIN
BIAS

DET

VPSO

SLOPE

VSET

VOUT

DET
CLPF

INHI
INLO

CMIP

04853-001

Wide bandwidth: 1 MHz to 8 GHz

High accuracy: 1.0 dB over 55 dB range (f < 5.8 GHz)
Stability over temperature: 0.5 dB
Low noise measurement/controller output (VOUT)
Pulse response time: 10 ns/12 ns (fall/rise)
Integrated temperature sensor
Small footprint LFCSP
Power-down feature: <1.5 mW at 5 V
Single-supply operation: 5 V @ 68 mA
Fabricated using high speed SiGe process

CMOP

GENERAL DESCRIPTION
The AD8318 is a demodulating logarithmic amplifier, capable
of accurately converting an RF input signal to a corresponding
decibel-scaled output voltage. It employs the progressive
compression technique over a cascaded amplifier chain, each
stage of which is equipped with a detector cell. The device is
used in measurement or controller mode. The AD8318
maintains accurate log conformance for signals of 1 MHz to
6 GHz and provides useful operation to 8 GHz. The input range
is typically 60 dB (re: 50 ) with error less than 1 dB. The
AD8318 has a 10 ns response time that enables RF burst
detection to beyond 45 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature
conditions. A 2 mV/C slope temperature sensor output is also
provided for additional system monitoring. A single supply of
5 V is required. Current consumption is typically 68 mA. Power
consumption decreases to <1.5 mW when the device is disabled.
The AD8318 can be configured to provide a control voltage
to a VGA, such as a power amplifier or a measurement output,
from Pin VOUT. Because the output can be used for controller
applications, wideband noise is minimal.

VOUT (V)

RF transmitter PA setpoint control and level monitoring

RSSI measurement in base stations, WLAN, WiMAX, and
radars

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0
65 60 55 50 45 40 35 30 25 20 15 10 5
PIN (dBm)

6
10

04853-052

APPLICATIONS

ERROR (dB)

Figure 1.

Figure 2. Typical Logarithmic Response and Error vs. Input Amplitude at 5.8 GHz

In this mode, the setpoint control voltage is applied to VSET.

The feedback loop through an RF amplifier is closed via VOUT,
the output of which regulates the amplifier output to a magnitude
corresponding to VSET. The AD8318 provides 0 V to 4.9 V
output capability at the VOUT pin, suitable for controller
applications. As a measurement device, Pin VOUT is externally
connected to VSET to produce an output voltage, VOUT, which
is a decreasing linear-in-dB function of the RF input signal
amplitude.
The logarithmic slope is nominally 25 mV/dB but can be
adjusted by scaling the feedback voltage from VOUT to the
VSET interface. The intercept is 20 dBm (re: 50 , CW input)
using the INHI input. These parameters are very stable against
supply and temperature variations.
The AD8318 is fabricated on a SiGe bipolar IC process and is
available in a 4 mm 4 mm, 16-lead LFCSP for the operating
temperature range of 40oC to +85oC.

Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 2004-2007 Analog Devices, Inc. All rights reserved.

AD8318
TABLE OF CONTENTS
Features .............................................................................................. 1

Temperature Compensation of Output Voltage..................... 13

Applications....................................................................................... 1

Temperature Sensor ................................................................... 14

General Description ......................................................................... 1

Measurement Mode ................................................................... 14

Functional Block Diagram .............................................................. 1

Device Calibration and Error Calculation.............................. 15

Revision History ............................................................................... 2

Selecting Calibration Points to Improve Accuracy over a

Reduced Range ........................................................................... 16

Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Using the AD8318 .......................................................................... 12
Basic Connections ...................................................................... 12
Enable Interface .......................................................................... 12
Input Signal Coupling................................................................ 12
Output Interface ......................................................................... 13

Variation in Temperature Drift from Device to Device........ 17

Temperature Drift at Different Temperatures ........................ 17
Setting the Output Slope in Measurement Mode .................. 17
Response Time Capability......................................................... 18
Output Filtering.......................................................................... 18
Controller Mode......................................................................... 19
Characterization Setup and Methods ...................................... 21
Evaluation Board ............................................................................ 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24

Setpoint Interface ....................................................................... 13

REVISION HISTORY
4/07Rev. A to Rev. B
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Table 1............................................................................ 3
Changes to Figure 23...................................................................... 12
Changes to Characterization Setup and Methods Section........ 21
Changes to Figure 48...................................................................... 23
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
1/06Rev. 0 to Rev. A
Changed TADJ Resistor to RTADJ Resistor....................Universal
Changes to Applications .................................................................. 1
Changes to Table 1............................................................................ 3
Changes to Figure 5, Figure 6, and Figure 7 Captions................. 8
Changes to Figure 12 Caption......................................................... 9
Changes to Figure 15 Caption......................................................... 9

Changed General Description Heading to

Theory of Operation ...................................................................... 11
Changes to Enable Interface Section ........................................... 12
Inserted Figure 24........................................................................... 12
Changes to Input Signal Coupling Section ................................. 12
Changes to Measurement Mode Section..................................... 14
Changes to Figure 36...................................................................... 17
Added Output Filtering Section ................................................... 19
Changes to Controller Mode Section .......................................... 19
Changes to Response Time Capability Section .......................... 18
Changes to Table 6.......................................................................... 22
Changes to Figure 47, Figure 48, and Figure 49 ......................... 23
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
7/04Rev. 0: Initial Version

Rev. B | Page 2 of 24

AD8318
SPECIFICATIONS
VPOS = 5 V, CLPF = 220 pF, TA = 25C, 52.3 termination resistor at INHI, unless otherwise noted.
Table 1.
Parameter
SIGNAL INPUT INTERFACE
Specified Frequency Range
DC Common-Mode Voltage
MEASUREMENT MODE
f = 900 MHz
Input Impedance
3 dB Dynamic Range
1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope
Intercept
Output VoltageHigh Power In
Output VoltageLow Power In
Temperature Sensitivity

f = 1.9 GHz
Input Impedance
3 dB Dynamic Range
1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope
Intercept
Output VoltageHigh Power In
Output VoltageLow Power In
Temperature Sensitivity

f = 2.2 GHz
Input Impedance
3 dB Dynamic Range
1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope
Intercept
Output VoltageHigh Power In
Output VoltageLow Power In
Temperature Sensitivity

Conditions
INHI (Pin 14) and INLO (Pin 15)

Min

Typ

Max

Unit

8
VPOS 1.8

GHz
V

957||0.71
65
57
48
1
58
24.5
22
0.78
1.52

||pF
dB
dB
dB
dBm
dBm
mV/dB
dBm
V
V

0.001
VOUT (Pin 6) shorted to VSET (Pin 7), sinusoidal
input signal
RTADJ = 500
TA = 25C
TA = 25C
40C < TA < +85C
1 dB error
1 dB error

PIN = 10 dBm
PIN = 40 dBm
PIN = 10 dBm
25C TA 85C
40C TA +25C
RTADJ = 500

26
19.5
0.7
1.42

TA = 25C
TA = 25C
40C < TA < +85C
1 dB error
1 dB error

PIN = 10 dBm
PIN = 35 dBm
PIN = 10 dBm
25C TA 85C
40C TA +5C
RTADJ = 500

27
17
0.63
1.2

TA = 25C
TA = 25C
40C < TA < +85C
1 dB error
1 dB error

PIN = 10 dBm
PIN = 35 dBm
PIN = 10 dBm
25C TA 85C
40C TA +25C

Rev. B | Page 3 of 24

28
15
0.63
1.2

23
24
0.86
1.62

0.0011
0.003

dB/C
dB/C

523||0.68
65
57
50
2
59
24.4
20.4
0.73
1.35

||pF
dB
dB
dB
dBm
dBm
mV/dB
dBm
V
V

22
24
0.83
1.5

0.0011
0.0072

dB/C
dB/C

391||0.66
65
58
50
2
60
24.4
19.6
0.73
1.34

||pF
dB
dB
dB
dBm
dBm
mV/dB
dBm
V
V

0.0005
0.0062

21.5
25
0.84
1.5

dB/C
dB/C

AD8318
Parameter
f = 3.6 GHz
Input Impedance
3 dB Dynamic Range
1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope
Intercept
Output VoltageHigh Power In
Output VoltageLow Power In
Temperature Sensitivity

f = 5.8 GHz
Input Impedance
3 dB Dynamic Range
1 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope
Intercept
Output VoltageHigh Power In
Output VoltageLow Power In
Temperature Sensitivity

f = 8.0 GHz
3 dB Dynamic Range
Maximum Input Level
Minimum Input Level
Slope
Intercept
Output VoltageHigh Power In
Output VoltageLow Power In
Temperature Sensitivity

OUTPUT INTERFACE
Voltage Swing
Output Current Drive
Small Signal Bandwidth
Video Bandwidth (or Envelope Bandwidth)
Output Noise
Fall Time
Rise Time

Conditions
RTADJ = 51

Min

TA = 25C
TA = 25C
40C < TA < +85C
1 dB error
1 dB error

PIN = 10 dBm
PIN = 40 dBm
PIN = 10 dBm
25C TA 85C
40C TA +25C
RTADJ = 1000
TA = 25C
TA = 25C
40C < TA < +85C
1 dB error
1 dB error

PIN = 10 dBm
PIN = 40 dBm
PIN = 10 dBm
25C TA 85C
40C TA +25C
RTADJ = 500
TA = 25C
40C < TA < +85C
3 dB error
3 dB error

PIN = 10 dBm
PIN = 40 dBm
PIN = 10 dBm
25C TA 85C
40C TA +25C
VOUT (Pin 6)
VSET = 0 V; PIN = 10 dBm, no load 1
VSET = 2.1 V; PIN = 10 dBm, no load1
VSET = 1.5 V; PIN = 50 dBm
PIN = 10 dBm; from CLPF to VOUT
PIN = 2.2 GHz; 10 dBm, fNOISE = 100 kHz, CLPF = 220 pF
PIN = Off to 10 dBm, 90% to 10%
PIN = 10 dBm to off, 10% to 90%

Rev. B | Page 4 of 24

Typ

Max

Unit

119||0.7
70
58
42
2
60
24.3
19.8
0.717
1.46

||pF
dB
dB
dB
dBm
dBm
mV/dB
dBm
V
V

0.0022
0.004

dB/C
dB/C

33||0.59
70
57
48
1
58
24.3
25
0.86
1.59

||pF
dB
dB
dB
dBm
dBm
mV/dB
dBm
V
V

0.0033
0.0069

dB/C
dB/C

60
58
3
55
23
37
1.06
1.78

dB
dB
dBm
dBm
mV/dB
dBm
V
V

0.028
0.0085

dB/C
dB/C

4.9
25
60
60
45
90
10
12

V
mV
mA
MHz
MHz
nV/Hz
ns
ns

AD8318
Parameter
VSET INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Bias Current Source
TEMPERATURE REFERENCE
Output Voltage
Temperature Slope
Current Source/Sink
POWER-DOWN INTERFACE
Logic Level to Enable Device
ENBL Current When Enabled
ENBL Current When Disabled
POWER INTERFACE
Supply Voltage
Quiescent Current
vs. Temperature
Supply Current when Disabled
vs. Temperature
1
2

Conditions
VSET (Pin 7)
PIN = 0 dBm; measurement mode 2
PIN = 65 dBm; measurement mode2
PIN = 10 dBm; VSET = 2.1 V
TEMP (Pin 13)
TA = 25C, RLOAD = 10 k
40C TA +85C, RLOAD = 10 k
TA = 25C
ENBL (Pin 16)

Min

Controller mode.
Gain = 1. For other gains, see the Measurement Mode section.

Rev. B | Page 5 of 24

Max

0.5
2.1
0.04
2.5
0.57

0.6
2
10/0.1

4.5
50

5
68
150
260
350

Unit

V
dB/mV
A
0.63

1.7
<1
15

ENBL = 5 V
ENBL = 0 V; sourcing
VPSI (Pin 3 and Pin 4), VPSO (Pin 9)
ENBL = 5 V
40C TA +85C
ENBL = 0 V, total currents for VPSI and VPSO
40C TA +85C

Typ

V
mV/C
mA
V
A
A

5.5
82

V
mA
A/C
A
A

AD8318
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage: Pin VPSO, Pin VPSI
ENBL, VSET Voltage
Input Power (Single-Ended, re: 50 )
Internal Power Dissipation
JA 1
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature
1

Rating
5.7 V
0 to VPOS
12 dBm
0.73 W
55C/W
125C
40C to +85C
65C to +150C
260C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

With package die paddle soldered to thermal pads with vias connecting
to inner and bottom layers.

Rev. B | Page 6 of 24

AD8318
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12

11

10

CMIP CMIP TADJ VPSO

13 TEMP

15 INLO

CMOP 8

AD8318

16 ENBL

VOUT 6
CLPF 5

CMIP CMIP
1

VSET 7

VPSI

VPSI

04853-002

14 INHI

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.
1, 2, 11, 12
3, 4
5
6
7
8
9
10
13
14
15
16

Mnemonic
CMIP
VPSI
CLPF
VOUT
VSET
CMOP
VPSO
TADJ
TEMP
INHI
INLO
ENBL
Paddle

Description
Device Common (Input System Ground).
Positive Supply Voltage (Input System): 4.5 V to 5.5 V. Voltage on Pin 3, Pin 4, and Pin 9 should be equal.
Loop Filter Capacitor.
Measurement and Controller Output.
Setpoint Input for Controller Mode or Feedback Input for Measurement Mode.
Device Common (Output System Ground).
Positive Supply Voltage (Output System): 4.5 V to 5.5 V. Voltage on Pin 3, Pin 4, and Pin 9 should be equal.
Temperature Compensation Adjustment.
Temperature Sensor Output.
RF Input. Nominal input range: 60 dBm to 0 dBm (re: 50 ), ac-coupled.
RF Common for INHI. AC-coupled RF common.
Device Enable. Connect to VPSI for normal operation. Connect pin to ground for disable mode.
Internally Connected to CMIP (Solder to Ground).

Rev. B | Page 7 of 24

AD8318
TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.6

2.0

1.6

1.8

1.2

1.8

1.2

1.6

0.8

1.6

0.8

1.4

0.4

1.4

0.4

1.2

1.2

1.0

0.4

1.0

0.4

0.8

0.8

0.8

0.8

0.6

1.2

0.6

1.2

0.4

1.6

0.4

1.6

0.2
65

55

45

35

25

15

2.0
15

0.2
65

55

45

35

25

15

ERROR (dB)

2.0

04853-006

2.2

VOUT (V)

2.0

ERROR (dB)

2.2

04853-003

VOUT (V)

VPOS = 5 V; TA = +25C, 40C, +85C; CLPF = 220 pF; RTADJ = 500 ; unless otherwise noted. Colors: +25C  Black; 40C  Blue;
+85C  Red.

2.0
15

Figure 4. VOUT and Log Conformance vs. Input Amplitude at 900 MHz,
Typical Device

Figure 7. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz,
Typical Device, RTADJ = 51
2.0

2.0

1.6

2.0

1.6

1.8

1.2

1.8

1.2

1.6

0.8

1.6

0.8

1.4

0.4

1.4

0.4

1.2

1.2

1.0

0.4

1.0

0.4

0.8

0.8

0.8

0.8

0.6

1.2

0.6

1.2

0.4

1.6

0.4

1.6

55

45

35

25

15

04853-004

0.2
65

2.0
15

0.2
65

55

45

35

25

15

2.0
15

04853-007

2.2

VOUT (V)

2.0

ERROR (dB)

2.2

ERROR (dB)

PIN (dBm)

VOUT (V)

PIN (dBm)

4.5

2.0

1.6

2.0

3.6

1.8

1.2

1.8

2.7

1.6

0.8

1.6

1.8

1.4

0.4

1.4

0.9

1.2

1.2

1.0

0.4

1.0

0.9

0.8

0.8

0.8

1.8

0.6

1.2

0.6

2.7

0.4

1.6

0.4

3.6

55

45

35

25

15

2.0
15

04853-005

0.2
65

0.2
65

55

45

35

25

15

4.5

PIN (dBm)

PIN (dBm)

Figure 6. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz,
Typical Device

Figure 9. VOUT and Log Conformance vs. Input Amplitude at 8 GHz,

Typical Device

Rev. B | Page 8 of 24

04853-008

2.2

VOUT (V)

2.0

ERROR (dB)

2.2

ERROR (dB)

PIN (dBm)

Figure 8. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz,
Typical Device, RTADJ = 1000

VOUT (V)

PIN (dBm)

Figure 5. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz,
Typical Device

2.0

1.6

1.6

1.2

1.2

0.8

0.8

0.4

0.4

0
0.4

0
0.4

0.8

0.8

1.2

1.2

1.6
2.0
65

55

45

35

25

15

04853-012

ERROR (dB)

2.0

04853-009

ERROR (dB)

AD8318

1.6
2.0
65

15

55

45

35

PIN (dBm)

2.0

1.6

1.6

1.2

1.2

0.8

0.8

0.4

0.4

0
0.4

1.2

1.2

1.6
25

15

1.6
2.0
65

15

55

45

4.5

1.6

3.6

1.2

2.7

0.8

1.9

0.4

0.9

0
0.4

15

0.9
1.8

1.2

2.7

1.6
25

0.8

35

15

15

04853-014

ERROR (dB)

2.0

45

25

Figure 14. Distribution of Error at Temperature After Ambient

Normalization vs. Input Amplitude at 5.8 GHz for at Least 70 Devices,
RTADJ = 1000

04853-011

ERROR (dB)

Figure 11. Distribution of Error at Temperature After Ambient

Normalization vs. Input Amplitude at 1900 MHz for at Least 70 Devices

55

35

PIN (dBm)

PIN (dBm)

2.0
65

15

0.4
0.8

35

0.8

45

04853-013

ERROR (dB)

2.0

55

15

Figure 13. Distribution of Error at Temperature After Ambient

Normalization vs. Input Amplitude at 3.6 GHz for at Least 70 Devices,
RTADJ = 51

04853-010

ERROR (dB)

Figure 10. Distribution of Error over Temperature After Ambient

Normalization vs. Input Amplitude at 900 MHz for at Least 70 Devices

2.0
65

25
PIN (dBm)

3.6
4.5
65

15

PIN (dBm)

55

45

35

25

15

PIN (dBm)

Figure 12. Distribution of Error at Temperature After Ambient

Normalization vs. Input Amplitude at 2.2 GHz for at Least 70 Devices

Figure 15. Distribution of Error at Temperature After Ambient

Normalization vs. Input Amplitude at 8 GHz for at Least 70 Devices

Rev. B | Page 9 of 24

AD8318
j1
j2

j0.5

10k
RF OFF

0.2

0.5

0.1GHz

8GHz
5.8GHz

0.9GHz

j0.2

1.9GHz
3.6GHz

2.2GHz

j0.5

1k
40dBm
20dBm

100
10dBm
0dBm

j2

10

04853-015

START FREQUENCY = 0.1GHz

STOP FREQUENCY = 8GHz

j1

10

30

100

300

1k

3k

10k

Figure 19. Noise Spectral Density of Output; CLPF = Open

1k

0.07

0.05

INCREASING VENBL

0.03
0.02

04853-016

0
1.4

1.5

1.6

1.7

10

1.8

10

Figure 17. Supply Current vs. Enable Voltage

100

300

1k

3k

10k

Figure 20. Noise Spectral Density of Output Buffer (from CLPF to VOUT);
CLPF = 0.1 F

VOUT

VOUT (V)

200mV/VERTICAL
DIVISION

PULSED RF INPUT 0.1GHz,

10dBm

2.2

2.0

2.0

1.6

1.8

1.2

1.6

0.8

1.4

0.4

1.2

1.0

0.4

0.8

0.8

0.6

1.2

0.4

1.6

0.2
65

04853-017

GND

30

FREQUENCY (kHz)

VENBL (V)

55

45

35

25

15

2.0
15

PIN (dBm)

20ns PER HORIZONTAL DIVISION

Figure 18. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, 10 dBm;
CLPF = Open

Rev. B | Page 10 of 24

Figure 21. Output Voltage Stability vs. Supply Voltage at 1.9 GHz
When VP Varies by 10%, Multiple Devices

ERROR (dB)

0.01

100

04853-020

DECREASING V ENBL

04853-019

NOISE SPECTRAL DENSITY (nV/ Hz)

0.06

SUPPLY CURRENT (A)

FREQUENCY (kHz)

Figure 16. Input Impedance vs. Frequency; No Termination Resistor on

INHI, ZO = 50

0.04

60dBm

04853-018

NOISE SPECTRAL DENSITY (nV/ Hz)

j0.2

AD8318
THEORY OF OPERATION
The AD8318 is a 9-stage demodulating logarithmic amplifier
that provides RF measurement and power amplifier control
functions. The design of the AD8318 is similar to the AD8313
logarithmic detector/controller. However, the AD8318 input
frequency range extends to 8 GHz with a 60 dB dynamic range.
Other improvements include: reduced intercept variability vs.
temperature, increased dynamic range at higher frequencies,
low noise measurement and controller output (VOUT),
adjustable low-pass corner frequency (CLPF), temperature
sensor output (TEMP), negative transfer function slope for
higher accuracy, and 10 ns response time for RF burst detection
capability. A block diagram is shown in Figure 22.
VPSI

ENBL

TEMP
SENSOR

TEMP

DET

TADJ

GAIN
BIAS

DET

DET

SLOPE

VPSO

VSET

VOUT

DET
CLPF

INHI

CMIP

CMOP

04853-021

INLO

CMIP, the input system common pin, provides a quality low

impedance connection to the printed circuit board (PCB)
ground via four package pins. Ground the package paddle,
which is internally connected to the CMIP pin, to the PCB to
reduce thermal impedance from the die to the PCB.
The logarithmic function is approximated in a piecewise
fashion by nine cascaded gain stages. For a more complete
explanation of the logarithm approximation, refer to the
AD8307 data sheet. The cells have a nominal voltage gain of
8.7 dB each and a 3 dB bandwidth of 10.5 GHz.
Using precision biasing, the gain is stabilized over temperature
and supply variations. Because the cascaded gain stages are
dc-coupled, the overall dc gain is high. An offset compensation
loop is included to correct for offsets within the cascaded cells.
At the output of each of the gain stages, a square-law detector
cell rectifies the signal. The RF signal voltages are converted to a
fluctuating differential current with an average value that
increases with signal level. Along with the nine gain stages and
detector cells, an additional detector is included at the input of
the AD8318, altogether providing a 60 dB dynamic range. After
the detector currents are summed and filtered, the function
ID log10(VIN/VINTERCEPT)

Figure 22. Block Diagram

A fully differential design, using a proprietary high speed SiGe

process, extends high frequency performance. Input INHI
receives the signal with a low frequency impedance of nominally
1200 in parallel with 0.7 pF. The maximum input with 1 dB
log conformance error is typically 0 dBm (re: 50 ). The noise
spectral density referred to the input is 1.15 nV/Hz, which is
equivalent to a voltage of 118 V rms in a 10.5 GHz bandwidth,
or a noise power of 66 dBm (re: 50 ). This noise spectral
density sets the lower limit of the dynamic range. However, the
low end accuracy of the AD8318 is enhanced by specially
shaping the demodulating transfer characteristic to partially
compensate for errors due to internal noise.

(1)

is formed at the summing node,

where:
ID is the internally set detector current.
VIN is the input signal voltage.
VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,
the output voltage would be 0 V if capable of going to 0 V).

Rev. B | Page 11 of 24

AD8318
USING THE AD8318
The AD8318 is specified for operation up to 8 GHz. As a result,
low impedance supply pins with adequate isolation between
functions are essential. In the AD8318, VPSI and VPSO, the two
positive supply pins, must be connected to the same positive
potential. The VPSI pin biases the input circuitry, while the
VPSO pin biases the low noise output driver for VOUT.
Separate commons are also included in the device. CMOP is
used as the common for the output drivers. Pin CMIP and
Pin CMOP should be connected to a low impedance ground plane.

enable interface. The response time of the AD8318 ENBL

interface is shown in Figure 25.
VPSI
40k
DISCHARGE
ENBL
2 VBE

200

40k

2 VBE

ENABLE

CMIP

04853-023

BASIC CONNECTIONS

Figure 24. ENBL Interface

: 2.07V
@: 2.07V

A power supply voltage of between 4.5 V and 5.5 V should be

applied to VPSO and VPSI. In addition, 100 pF and 0.1 F
power supply decoupling capacitors connect close to each
power supply pin. The two adjacent VPSI pins can share a pair
of decoupling capacitors due to their proximity.
VS
499
NOTE 1

12

11

C5
0.1F

10

C6
100pF

RF
INPUT

13 TEMP

R1
52.3

C1
1nF 14 INHI
C2
1nF 15 INLO

CMOP 8

AD8318

16 ENBL

CMIP CMIP
VS

04853-051

CMIP CMIP TADJ VPSO

TEMP

CH1 500mV

VSET 7
VOUT 6

VOUT

CLPF 5

NOTE 2

VPSI

VPSI

920mV

Figure 25. ENBL Response Time; VPOS = 5.0 V;

Input AC-Coupling Caps = 18 pF; CLPF = Open

INPUT SIGNAL COUPLING

C7
100pF
C8
0.1F
04853-022

VS
1SEE TEMPERATURE COMPENSATION SECTION.
2SEE RESPONSE TIME SECTION.

M400ns
A CH1
T
425.200ns

Figure 23. Basic Connections

The paddle of the AD8318 LFCSP is internally connected to

CMIP. For optimum thermal and electrical performance, solder
the paddle to a low impedance ground plane.

ENABLE INTERFACE
To enable the AD8318, the ENBL pin must be pulled high.
Taking ENBL low puts the AD8318 in sleep mode, reducing
current consumption to 260 A at ambient. The voltage on
ENBL must be greater than 2 VBE (~1.7 V) to enable the device.
When enabled, the ENBL pin draws less than 1 A. When
ENBL is pulled low, the pin sources 15 A.

The RF input to the AD8318 (INHI) is single ended and must

be ac-coupled. INLO (input common) should be ac-coupled to
ground (see Figure 23). Suggested coupling capacitors are 1 nF
ceramic, 0402-style capacitors for input frequencies of 1 MHz to
8 GHz. The coupling capacitors should be mounted close to the
INHI pin and the INLO pin. These capacitor values can be
increased to lower the input stage high-pass cutoff frequency.
The high-pass corner is set by the input coupling capacitors and
the internal 10 pF capacitor. The dc voltage on INHI and INLO
is approximately one diode voltage drop below the voltage
applied to the VPSI pin.
The Smith Chart in Figure 16 shows the AD8318 input
impedance vs. frequency. Table 4 lists the reflection coefficient
and impedance at select frequencies. For Figure 16 and Table 4,
the 52.3 input termination resistor is removed. At dc, the
resistance is typically 2 k. At frequencies up to 1 GHz, the
impedance is approximated as 1000 ||0.7 pF. The RF input
pins are coupled to a network as shown in the simplified
schematic in Figure 26.

The enable interface has high input impedance. An internal

200 resistor is placed in series with the ENBL input for added
protection. Figure 24 depicts a simplified schematic of the
Rev. B | Page 12 of 24

AD8318
VPSO

CURRENT

10pF

CLPF

10pF

20k

10
+
0.2V

FIRST
GAIN
STAGE

20k

150

INHI
2k

200

A = 8.6dB

CMOP

INLO

SETPOINT INTERFACE

Figure 26. Input Interface

While the input can be reactively matched, this is typically not

necessary. An external 52.3 shunt resistor (connected on the
signal side of the input coupling capacitors, see Figure 23)
combines with the relatively high input impedance to provide
an adequate broadband 50 match.

S11
Imaginary
0.041
0.183
0.350
0.595
0.616
0.601
0.305
0.286
0.062

ID log10(VIN/VINTERCEPT) = ISET

(2)

If VSET = VOUT/X, ISET = VOUT/(X 3.13 k). The result is

VOUT = (ID 3.13 k X) log10(VIN/VINTERCEPT).

Table 4. Input Impedance for Select Frequency

Real
+0.918
+0.905
+0.834
+0.605
+0.524
+0.070
0.369
0.326
0.390

The setpoint interface is shown in Figure 28. The VSET input

drives the high impedance (250 k) input of an internal
operational amplifier. The VSET voltage appears across the
internal 3.13 k resistor to generate ISET. When a portion
of VOUT is applied to VSET, the feedback loop forces

Impedance
(Series)
927-j491
173-j430
61-j233
28-j117
28-j102
26-j49
20-j16
22-j16
22-j3

ISET
VSET

3.13k
CMOP

04853-026

OFFSET
COMP

04853-024

Figure 27. Output Interface

gm
STAGE

Frequency
(MHz)
100
450
900
1900
2200
3600
5300
5800
8000

VOUT

04853-025

VPSI

Figure 28. VSET Interface

The coupling time constant, 50 CC/2, forms a high-pass

corner with a 3 dB attenuation at fHP = 1/(2 50 CC ), where
C1 = C2 = CC. Using the typical value of 1 nF, this high-pass
corner is ~3.2 MHz. In high frequency applications, fHP should
be as large as possible to minimize the coupling of unwanted
low frequency signals. Likewise, in low frequency applications,
a simple RC network forming a low-pass filter should be added,
generally placed at the generator side of the coupling capacitors,
thereby lowering the required capacitance value for a given
high-pass corner frequency.

The slope is given by ID X 3.13 k = 500 mV X. For

example, if a resistor divider to ground is used to generate a
VSET voltage of VOUT/2, X = 2. The slope is set to 1 V/decade or
50 mV/dB.

TEMPERATURE COMPENSATION OF OUTPUT

VOLTAGE
The AD8318 functionality includes the capability to externally
trim the temperature drift. Attaching a ground-referenced
resistor to the TADJ pin alters an internal current, minimizing
intercept drift vs. temperature. As a result, the RTADJ can be
optimized for operation at different frequencies.
ICOMP

OUTPUT INTERFACE

2V
VINTERNAL
~0.4V
2k
TADJ

04853-027

The logarithmic output interface is shown in Figure 27. The

VOUT pin is driven by a PNP output stage. An internal 10
resistor is placed in series with the emitter follower output and
the VOUT pin. The rise time of the output is limited mainly by
the slew on CLPF. The fall time is an RC limited slew provided
by the load capacitance and the pull-down resistance at VOUT.
There is an internal pull-down resistor of 350 . Any resistive
load at VOUT is placed in parallel with the internal pull-down
resistor and provides additional discharge current.

Figure 29. TADJ Interface

RTADJ, nominally 499 for optimal temperature compensation

at 2.2 GHz input frequency, is connected between the TADJ pin
and ground (see Figure 23). The value of this resistor partially
determines the magnitude of an analog correction coefficient
that is employed to reduce intercept drift.

Rev. B | Page 13 of 24

AD8318
When the VOUT voltage, or a portion of the VOUT voltage, is
fed back to VSET, the device operates in measurement mode.
As shown in Figure 31, the AD8318 has an offset voltage, a
negative slope, and a VOUT measurement intercept greater
than its input signal range.
2.4
2.1

Table 5. Recommended RTADJ Resistors

Recommended RTADJ
500
500
500
51
1 k
500

VOUT (V)

Frequency
900 MHz
1.9 MHz
2.2 GHz
3.6 GHz
5.8 GHz
8 GHz

1.8

1.0

1.5

0.5

1.2

0.6
0.3

The AD8318 internally generates a voltage that is proportional

to absolute-temperature (VPTAT). The VPTAT voltage is multiplied
by a factor of 5, resulting in a 2 mV/C output at the TEMP pin.
The output voltage at 27C is typically 600 mV. An emitter
follower drives the TEMP pin, as shown in Figure 30.
VPSI

0.5
RANGE OF
CALCULATION
OF SLOPE AND
INTERCEPT

0
65 60 55 50 45 40 35 30 25 20 15 10 5
PIN (dBm)

1.0
1.5

10 15
INTERCEPT

Figure 31. Typical Output Voltage vs. Input Signal

The output voltage vs. input signal voltage of the AD8318 is

linear-in-dB over a multidecade range. The equation for this
function is

INTERNAL

VOUT = X VSLOPE/DEC log10(VIN/VINTERCEPT)

= X VSLOPE/dB 20 log10(VIN/VINTERCEPT)

TEMP

04853-028

4k

CMIP

1.5

0.9

TEMPERATURE SENSOR

1k

2.0

VOUT 25C
ERROR 25C

ERROR (dB)

The relationship between output temperature drift and frequency

is nonlinear and is not easily modeled. Experimentation is
required to choose the correct RTADJ resistor at frequencies
not listed in Table 5.

MEASUREMENT MODE

Figure 30. Temp Sensor Interface

The internal pull-down resistance is 5 k. The temperature

sensor has a slope of 2 mV/C.
The temperature sensor output varies with output current due
to increased die temperature. Output loads less than 1 k draw
enough current from the output stage causing this increase to
occur. An output current of 10 mA results in the voltage on the
temperature sensor to increase by 1.5C, or ~3 mV.
Best precision from the temperature sensor is obtained when
the supply current to AD8318 remains fairly constant, that is,
no heavy load drive.

04853-029

Table 5 lists recommended resistors for various frequencies.

These resistors provide the best overall temperature drift based
on measurements of a diverse population of devices.

(3)
(4)

where:
X is the feedback factor in VSET = VOUT/X.
VINTERCEPT is expressed in Vrms.
VSLOPE/DEC is nominally 500 mV/decade and VSLOPE/dB is
nominally 25 mV/dB.
VINTERCEPT, expressed in dBV, is the x-axis intercept of the linearin-dB transfer function shown in Figure 31.
VINTERCEPT is 7 dBV (20 dBm, re: 50 or 2.239 Vrms) for a
sinusoidal input signal.
The slope of the transfer function can be increased to
accommodate various converter mV per dB (LSB per dB)
requirements. However, increasing the slope can reduce the
dynamic range. This is due to the limitation of the minimum
and maximum output voltages, determined by the chosen
scaling factor X.
The minimum value for VOUT is X VOFFSET. The offset voltage,
VOFFSET, is equal to 0.5 V and is internally added to the detector
output signal.
VOUT(MIN) = (X VOFFSET)

Rev. B | Page 14 of 24

(5)

AD8318
The maximum output voltage is 2.1 V X, and cannot exceed
400 mV below the positive supply.

For further information on the intercept variation dependence

upon waveform, refer to the AD8313 and AD8307 data sheets.

VOUT(MAX) = (2.1 V X) when X < (VPOS 400 mV)/(2.1 V)

DEVICE CALIBRATION AND ERROR CALCULATION

When X = 1, the typical output voltage swing is 0.5 V to 2.1 V.

The output voltage swing is modeled using Equation 5 to
Equation 7 and restricted by Equation 8:
VOUT(MIN) < VOUT < VOUT(MAX)

(8)

The measured transfer function of the AD8318 at 2.2 GHz is

shown in Figure 32. The figure shows plots of both output
voltage vs. input power and calculated log conformance error
vs. input power.
As the input power varies from 65 dBm to 0 dBm, the output
voltage varies from 2 V to about 0.5 V.

When X = 4 and VPOS = 5 V,

(X VOFFSET) < VOUT < (VPOS 400 mV)

VOUTIDEAL = SLOPE (PIN INTERCEPT)

SLOPE = (VOUT1 VOUT2)/(PIN1 PIN2)
INTERCEPT = PIN1 (VOUT1/SLOPE)
ERROR (dB) = (VOUT VOUTIDEAL )/SLOPE

VOUT +25C
VOUT 40C
VOUT +85C
ERROR +25C
ERROR 40C
ERROR +85C

(4 0.5 V) < VOUT < (2.1 V 4)

2.2

2 V < VOUT < 4.6 V

2.0

2.0

1.8

1.5

1.6

1.0

1.4

0.5

1.2

1.0

0.5

0.8

1.0

0.6

1.5

0.4

2.0

The slope is very stable vs. process and temperature variation.

When base-10 logarithms are used, VSLOPE/DECADE represents the
output voltage per decade of input power. One decade is equal
to 20 dB; VSLOPE/DEC/20 = VSLOPE/dB represents the output voltage
slope in V/dB.
As noted in Equation 3, the VOUT voltage has a negative slope.
This is the correct slope polarity to control the gain of many
power amplifiers and other VGAs in a negative feedback
configuration. Because both the slope and intercept vary
slightly with frequency, refer to Table 1 for application-specific
values for the slope and intercept.
Although demodulating log amps respond to input signal
voltage, not input signal power, it is customary to discuss the
amplitude of high frequency signals in terms of power. In this
case, the characteristic impedance of the system, Z0, must be
known to convert voltages to corresponding power levels.
Beginning with the definitions of dBm and dBV,
P (dBm) = 10 log10(Vrms2/(Z0 1 mW))
V (dBV) = 20 log10(Vrms/1 Vrms)

(9)
(10)

When Equation 9 is expanded

P (dBm) = 20 log10(Vrms) 10 log10(Z0 1 mW)

(11)

VOUT2

VOUT (V)

For X = 4, slope = 100 mV/dB; VOUT can swing 2.6 V, and the
usable dynamic range is reduced to 26 dB from 0 dBm to 26 dBm.

VOUT1

0.2
65 60 55
45 40 35 30 25 20 15
PIN1
PIN2
PIN (dBm)

5
INTERCEPT

Because the slope and intercept vary from device to device,

board-level calibration is performed to achieve high accuracy.
The equation can be rewritten for output voltage, from the
Measurement Mode section, using an intercept expressed
in dBm.
VOUT = Slope (PIN Intercept)

(14)

In general, the calibration is performed by applying two known

signal levels to the AD8318 input and measuring the corresponding output voltages. The calibration points are generally
chosen to be within the linear-in-dB operating range of the
device (see Figure 32). Calculation of the slope and intercept is
done by:
Slope = (VOUT1 VOUT2)/(PIN1 PIN2)

(15)

Intercept = PIN1 VOUT1/Slope

(16)

(12)

For example, PINTERCEPT for a sinusoidal input signal, expressed

in terms of dBm (decibels referred to 1 mW), in a 50 system is

Once the slope and intercept are calculated, an equation can be

written to allow calculation of an (unknown) input power based
on the output voltage of the detector.

PINTERCEPT (dBm) = VINTERCEPT (dBV)

10 log10(Z0 1 mW) =

Figure 32. Transfer Function at 2.2 GHz

and given Equation 10, Equation 11 can be rewritten as

P (dBm) = V (dBV) 10 log10(Z0 1 mW)

2.5

ERROR (dB)

VOUT(MAX) = (VPOS 400 mV) when X (VPOS 400 mV)/ (2.1 V)

(7)

04853-030

(6)

PIN(unknown) = VOUT (measured)/Slope + Intercept

(13)

7 dBV 10 log10(50 10 ) = 20 dBm

Rev. B | Page 15 of 24

(17)

AD8318

(18)

Figure 32 includes a plot of the error at 25C, the temperature at

which the log amp is calibrated. Note that the error is not zero.
This is because the log amp does not perfectly follow the ideal
VOUT vs. PIN equation, even within its operating region. The
error at the calibration points (12 dBm and 52 dBm, in this
case) is, however, equal to 0 by definition.

Once again, at 25C, an error of 0 dB is seen at the calibration

points. Note also that the range over which the AD8318
maintains an error of < 1 dB is extended to 60 dB at 25C and
58 dB over temperature. The disadvantage of this approach is
that linearity suffers, especially at the top end of the input range.
2.2

Figure 32 includes error plots for the output voltage at 40C

and +85C. These error plots are calculated using the slope
and intercept at 25C. This method is consistent with a massproduction environment where calibration at temperature is
not practical.

2.0

VOUT (V)

1.8

SELECTING CALIBRATION POINTS TO IMPROVE

ACCURACY OVER A REDUCED RANGE
In some applications, very high accuracy is required at just one
power level or over a reduced input range. For example, in a
wireless transmitter, the accuracy of the high power amplifier
(HPA) is most critical at, or close to, full power.

1.8

1.5

1.6

1.0

1.4

0.5

1.2

1.0

0.5

0.6

1.5

0.4

2.0

0.2
65 60 55 50 45 40 35 30
PIN (dBm)
PIN2

20

10 5

2.5

1.4

0.5

1.2

1.0

0.5

0.8

1.0
1.5
2.0
0

2.5

PIN (dBm)

Figure 34. Dynamic Range Extension by Choosing Calibration Points

Close to the End of the Linear Range

Another way of presenting the error function of a log amp

detector is shown in Figure 35. In this case, the dB error at hot
and cold temperatures is calculated with respect to the output
voltage at ambient. This is a key difference in comparison to the
plots in Figure 33 and Figure 34. Previously, all errors were
calculated with respect to the ideal transfer function at ambient.

1.0

VOUT1

1.0

0.2
65 60 55 50 45 40 35 30 25 20 15 10 5

ERROR (dB)

2.0

1.5

1.6

0.4

2.5

2.0

2.0

58dB DYNAMIC RANGE (1dB ERROR)

04853-031

VOUT2

VOUT (V)

2.2

ERROR +25C
ERROR 40C
ERROR +85C

2.5
ERROR +25C
ERROR 40C
ERROR +85C

0.6

Figure 33 shows the same measured data as Figure 32. Note

that accuracy is very high from 10 dBm to 30 dBm. Below
30 dBm, the error increases to about 1 dB. This is because
the calibration points have changed to 14 dBm and 26 dBm.
VOUT +25C
VOUT 40C
VOUT +85C

VOUT +25C
VOUT 40C
VOUT +85C

ERROR (dB)

Error (dB) = (VOUT(MEASURED) VOUT(IDEAL))/Slope

Figure 34 shows how calibration points can be adjusted to

increase dynamic range but at the expense of linearity. In this
case, the calibration points for slope and intercept are set at
4 dBm and 60 dBm. These points are at the end of the linear
range of the device.

04853-038

Using the equation for the ideal output voltage (see Equation 13) as
a reference, the log conformance error of the measured data can
be calculated as

PIN1

Figure 33. Output Voltage and Error vs. PIN with 2-Point Calibration at
10 dBm and 30 dBm

When this alternative technique is used, the error at ambient

becomes, by definition, equal to 0 (see Figure 35). This is valid
if the device transfer function perfectly follows the ideal
VOUT = Slope (PIN Intercept) equation. However, because a
log amp in practice never perfectly follows this equation
(especially outside of its linear operating range), this plot tends
to artificially improve linearity and extend the dynamic range.
This plot is a useful tool for estimating temperature drift at a
particular power level with respect to the (nonideal) output
voltage at ambient. However, to achieve this level of accuracy in
an end application requires calibration at multiple points in the
operating range of the device.

Calibration points are chosen to suit the application at hand. In

general, the calibration points are never chosen in the nonlinear
portion of the transfer function of the log amp (above 5 dBm
or below 60 dBm, in this case).

Rev. B | Page 16 of 24

AD8318
2.5

TEMPERATURE DRIFT AT DIFFERENT

TEMPERATURES

1.5

1.6

1.0

1.4

0.5

1.2

1.0

0.5

0.8

1.0

0.6

1.5

0.4

2.0

0.2
65 60 55 50 45 40 35 30 25 20 15 10 5

2.5

Figure 37 shows the log slope and error over temperature for
a 5.8 GHz input signal. Error due to drift over temperature
consistently remains within 0.5 dB, and only begins to exceed
this limit when the ambient temperature drops below 20C.
When using a reduced temperature range, higher measurement
accuracy is achievable for all frequencies.
VOUT +25C
VOUT 0C
ERROR 10C
ERROR +70C

VOUT 40C
VOUT +70C
ERROR 20C
VOUT 10C
ERROR 40C

2.2

VOUT +85C
ERROR +25C
ERROR 0C
VOUT 20C
ERROR +85C

2.5

2.0

2.0

Figure 35. Error vs. Temperature with Respect to Output Voltage at 25C
(Does Not Take Transfer Function Nonlinearities at 25C into Account)

1.8

1.5

1.6

1.0

1.4

0.5

1.2

1.0

0.5

0.8

1.0

0.6

1.5

0.4

2.0

VARIATION IN TEMPERATURE DRIFT FROM

DEVICE TO DEVICE

2.0

1.6

1.8

1.2

1.6

0.8

1.4

0.4

1.2

1.0

0.4

0.8

0.8

0.6

1.2

0.4

1.6

0.2
65

55

45

35

25

15

2.0
15

2.5

PIN (dBm)

SETTING THE OUTPUT SLOPE IN MEASUREMENT

MODE

PIN (dBm)

Figure 36. Output Voltage and Error vs. Temperature (+25C, 40C, and
+85C) of a Population of Devices Measured at 5.8 GHz

To operate in measurement mode, VOUT is connected to VSET.

This yields the typical logarithmic slope of 25 mV/dB. The
output swing corresponding to the specified input range is then
approximately 0.5 V to 2.1 V. The slope and output swing can be
increased by placing a resistor divider between VOUT and
VSET (that is, one resistor from VOUT to VSET and one
resistor from VSET to common).
As an example, if two equal resistors, such as 10 k/10 k, are
used, the slope doubles to approximately 50 mV/dB. The input
impedance of VSET is approximately 500 k. Slope setting
resistors should be kept below ~50 k to prevent this input
impedance from affecting the resulting slope. When increasing
the slope, the new output voltage range cannot exceed the
output voltage swing capability of the output stage. Refer to the
Measurement Mode section for further details.
AD8318
VOUT

50mV/dB
10k

VSET
10k

Figure 38. Increasing the Slope

Rev. B | Page 17 of 24

04853-033

2.0

ERROR (dB)

2.2

0.2
65 60 55 50 45 40 35 30 25 20 15 10 5

Figure 37. Typical Drift at 5.8 GHz for Various Temperatures

04853-050

VOUT (V)

Figure 36 shows a plot of output voltage and error for multiple

AD8318 devices measured at 5.8 GHz. The concentration of
black error plots represents the performance of the population
at 25C (slope and intercept are calculated for each device).
The red and blue curves indicate the measured behavior of a
population of devices over temperature. This suggests a range
on the drift (from device to device) of 1.2 dB.

VOUT (V)

PIN (dBm)

ERROR (dB)

2.0

ERROR (dB)

VOUT (V)

1.8

ERROR +25C wrt VOUT

ERROR 40C wrt VOUT
ERROR +85C wrt VOUT

04853-032

VOUT +25C
VOUT 40C
VOUT +85C

2.0

04853-039

2.2

AD8318
AD8318
OUTPUT

+5V
1nF

VPOS
INHI
VOUT

40

50

AD8318

52.3

INLO
1nF

+5V

ADCMP563

VSET

50

GND
50

100

50

VREF = 1.8V1.2V

100
COMPARATOR
OUTPUT

5.2V
5.2V

04853-040

PULSED RF
INPUT

Figure 39. AD8318 Operating with the High Speed ADCMP563 Comparator

The AD8318 has a 10 ns rise/fall time capability (10% to 90%)

for input power switching between the noise floor and 0 dBm.
This capability enables RF burst measurements at repetition
rates beyond 45 MHz. In most measurement applications, the
AD8318 has an external capacitor connected to CLPF to
provide additional filtering for VOUT. However, using the
CLPF capacitor slows the response time as does stray capacitance
on VOUT. For an application requiring maximum RF burst
detection capability, the CLPF pin is left unconnected. In this
case, the integration function is provided by the 1.5 pF on-chip
capacitor.
There is a 10 internal resistor in series with the output driver.
Because of this resistor, it is necessary to add an external 40
back-terminating resistor in series with the output when driving
a 50 load. Place the back-terminating resistor close to the
VOUT pin. The AD8318 has the drive capability to drive a 50
load at the end of a coaxial cable or transmission line when back
terminated (see Figure 39).

Figure 40 shows the response of the AD8318 and the comparator

for a 500 MHz pulsed sine wave of varying amplitudes. The
output level of the AD8318 is the signal strength of the input
signal. For applications where these RF bursts are very small,
the output level does not change by a large amount. Using a
comparator is beneficial in this case because it turns the output
of the log amp into a limiter-like signal. While this configuration
does result in the loss of received signal power level, it does
allow for presence-only detection of low power RF bursts.

OUTPUT FILTERING
For applications in which maximum video bandwidth and,
consequently, fast rise time are desired, it is essential that the
CLPF pin be left unconnected and free of any stray capacitance.
To reduce the nominal output video bandwidth of 45 MHz,
connect a ground-referenced capacitor (CFLT) to the CLPF pin,
as shown in Figure 41. Generally, this is done to reduce output
ripple (at twice the input frequency for a symmetric input
waveform, such as sinusoidal signals).
AD8318

The circuit diagram in Figure 39 shows the AD8318 used with a

high speed comparator circuit. The 40 series resistor at the
output of the AD8318 combines with an internal 10 to
properly match to the 50 input of the comparator.
PULSED RF
INPUT

50dB

30dB

20dB

ILOG
+4
3.13k

1.5pF

VOUT
CLPF
CFLT

10dB

04853-042

RESPONSE TIME CAPABILITY

Figure 41. Lowering the Postdemodulation Bandwidth

CFLT is selected by
AD8318
OUTPUT

CFLT =
04853-041

COMPARATOR
OUTPUT

100

200

300

400

500

600

700

800

TIME (ns)

Figure 40. Pulse Response of AD8318 and Comparator for RF Pulses

of Varying Amplitudes

( 3.13 k VideoBandwidth ) 1.5 pF

(19)

Set the video bandwidth to a frequency equal to about onetenth the minimum input frequency. This ensures that the
output ripple of the demodulated log output, which is at twice
the input frequency, is well filtered.

Rev. B | Page 18 of 24

AD8318
In many log amp applications, it may be necessary to lower the
corner frequency of the postdemodulation filtering to achieve
low output ripple while maintaining a rapid response time to
changes in signal level. For an example of a 4-pole active filter,
see the AD8307 data sheet.

CONTROLLER MODE
The AD8318 provides a controller mode feature at the VOUT
pin. Using VSET for the setpoint voltage, it is possible for the
AD8318 to control subsystems, such as power amplifiers (PAs),
variable gain amplifiers (VGAs), or variable voltage attenuators
(VVAs) that have output power that increases monotonically
with respect to their gain control signal.
To operate in controller mode, the link between VSET and
VOUT is broken. A setpoint voltage is applied to the VSET
input; VOUT is connected to the gain control terminal of the
VGA, and the detector RF input is connected to the output of
the VGA (usually using a directional coupler and some
additional attenuation). Based on the defined relationship
between VOUT and the RF input signal when the device is in
measurement mode, the AD8318 adjusts the voltage on VOUT
(VOUT is now an error amplifier output) until the level at the
RF input corresponds to the applied VSET.

The basic connections for operating the AD8318 as an analog

controller with the AD8367 are shown in Figure 43. The
AD8367 is a low frequency to 500 MHz VGA with 45 dB of
dynamic range. This configuration is very similar to the one
shown in Figure 42. For applications working at high input
frequencies, such as cellular bands or WLAN, or those
requiring large gain control ranges, the AD8318 can control
the 10 MHz to 3 GHz ADL5330 RF VGA. For further details
and an application schematic, refer to the ADL5330 data sheet.
The voltage applied to the GAIN pin controls the gain of the
AD8367. This voltage, VGAIN, is scaled linear-in-dB with a slope
of 20 mV/dB and runs from 50 mV at 2.5 dB of gain up to
1.0 V at +42.5 dB.
The incoming RF signal to the AD8367 has a varying amplitude
level. Receiving and demodulating it with the lowest possible
error requires that the signal levels be optimized for the highest
signal-to-noise ratio (SNR) feeding into the analog-to-digital
converters (ADC). This is done by using an automatic gain
control (AGC) loop. In Figure 43, the voltage output of the
AD8318 modifies the gain of the AD8367 until the incoming
RF signal produces an output voltage that is equal to the
setpoint voltage VSET.
+3V
RF INPUT SIGNAL

DIRECTIONAL
COUPLER

RFIN

INHI

AD8318
INLO
1nF

VSET

57.6
GAIN

CFLT

R2
261

DAC

+VSET
SETPOINT
VOLTAGE
CFLT
100pF

R1
1k

VOUT
VSET

HPFL

+5V
VPOS
INHI

CHP
100pF
RHP
100

100MHz
BANDPASS
FILTER

1nF

AD8318
CLPF

INLO
GND

1nF

If the AD8367 output drives a 50 load, such as an oscilloscope

or spectrum analyzer, use a simple resistive divider network.
The divider used in Figure 43 has an insertion loss of 11.5 dB.
Figure 44 shows the transfer function of output power vs. VSET
voltage for a 100 MHz sine wave at 40 dBm into the AD8367.

DAC

CLPF
04853-034

52.3

174

The AGC loop is capable of controlling signals over ~45 dB

dynamic range. The output of the AD8367 is designed to drive
loads 200 . As a result, it is not necessary to use the 53.6
resistor at the input of the AD8318; the nominal input impedance of 2 k is sufficient.

VOUT

1nF

0.1F

Figure 43. AD8318 Operating in Controller Mode to Provide Automatic Gain

Control Functionality in Combination with the AD8367

GAIN
CONTROL
VOLTAGE

ATTENUATOR

AD8367 VOUT
VGA

INPT

In order for this output power control loop to be stable, a

ground-referenced capacitor is connected to the CLPF pin.
This capacitor, CFLT, integrates the error signal (in the form of a
current) to set the loop bandwidth and ensure loop stability. For
further details on control loop dynamics, refer to the AD8315
data sheet.

VGA/VVA

RF OUTPUT SIGNAL
VPOS GND

04853-047

When the AD8318 operates in controller mode, there is no

defined relationship between VSET and VOUT voltage; VOUT settles
to a value that results in the correct input signal level appearing
at INHI/INLO.

Figure 42. AD8318 Controller Mode

Decreasing VSET, which corresponds to demanding a higher

signal from the VGA, tends to increase VOUT. The gain control
voltage of the VGA must have a positive sense. A positive
control voltage to the VGA increases the gain of the device.
Rev. B | Page 19 of 24

10

0.8

15

0.6

20

0.4

25

0.2

30

35

0.2

40

0.4

45

0.6

50

0.8

55

1.0

60
0.6

0.8

1.0

1.2

1.4

1.6

1.8

1.2
2.0

10
0
MAXIMUM INPUT LEVEL
10
20

MINIMUM INPUT LEVEL

60
70
80
0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

VSET (V)

Figure 44. AD8367 Output Power vs. AD8318 Setpoint Voltage

For the AGC loop to remain locked, the AD8318 must track the
envelope of the VGA output signal and provide the necessary
voltage levels to the AD8367 gain control input. Figure 45
shows an oscilloscope screen image of the AGC loop depicted
in Figure 43. A 50 MHz sine wave with 50% AM modulation is
applied to the AD8367. The output signal from the VGA is a
constant envelope sine wave with an amplitude corresponding
to a setpoint voltage at the AD8318 of 1.0 V.

Figure 46. Setpoint Voltage vs. Input Power. Optimal

signal levels must be used to achieve the full 45 dB
dynamic range capabilities of the AD8367.

In some cases, if VGAIN is >1.0 V it can take an unusually long

time for the AGC loop to recover; that is, the output of the
AD8318 remains at an abnormally high value and the gain is set
to its maximum level. A voltage divider is placed between the
output of the AD8318 and the AD8367 GAIN pin to ensure that
VGAIN does not exceed 1.0 V.
In Figure 43, CHP and RHP are configured to reduce oscillation
and distortion due to harmonics at higher gain settings. Some
additional filtering is recommended between the output of the
AD8367 and the input of the AD8318. This helps to decrease
the output noise of the AD8367, which can reduce the dynamic
range of the loop at higher gain settings (smaller VSET).

AM MODULATED INPUT

AD8318 V OUT
2

Response time and the amount of signal integration are controlled

by CFLT. This functionality is analogous to the feedback capacitor
around an integrating amplifier. Though it is possible to use
large capacitors for CFLT, in most applications, values under 1 nF
provide sufficient filtering.

AD8367 OUTPUT

04853-045

CH2 200mV

40
50

VSET (V)

CH1 50.0mV
CH3 20.0mV

30

04853-049

1.0

PIN (dBm)

1.2

ERROR (dB)

0
5

04853-048

POUT (dBm)

AD8318

M4.00ms

A CH2

Calibration in controller mode is similar to the method used in

measurement mode. Do a simple 2-point calibration by applying
two known VSET voltages or DAC codes and measuring the
output power from the VGA. Slope and intercept are calculated
using Equation 20 to Equation 22:

64.0mV

Figure 45. Oscilloscope Screen Image Showing an AM Modulated

Input Signal to the AD8367. The AD8318 tracks the envelope
of this input signal and applies the appropriate voltage to ensure
a constant output from the AD8367.

The 45 dB control range is constant for the range of VSET

voltages. The input power levels to the AD8367 must be optimized
to achieve this range. In Figure 46, the minimum and maximum
input power levels are shown vs. setpoint voltage.

Slope = (VSET1 VSET2)/(POUT1 POUT2)

(20)

Intercept = POUT1 VSET1/Slope

(21)

VSET = Slope (Px Intercept)

(22)

For more information on AGC applications, refer to the

AD8367 data sheet or ADL5330 data sheet.

Rev. B | Page 20 of 24

AD8318
CHARACTERIZATION SETUP AND METHODS

To measure noise spectral density, the 0 resistor in series with

the VOUT pin is replaced with a 1 F dc blocking capacitor.
The capacitor is used because the Rohde & Schwarz FSEA
spectrum analyzer cannot handle dc voltages at its RF input.
The CLPF pin is left open for data collected for Figure 19. For
Figure 20, a 1 F capacitor is placed between CLPF and ground.
The large capacitor filters the noise from the detector stages
of the log amp. Noise spectral density measurements are taken
using the FSEA spectrum analyzer and the SMT06 signal
generator. The signal generator frequency is set to 2.2 GHz.
The spectrum analyzer has a span of 10 Hz, resolution
bandwidth of 50 Hz, video bandwidth of 50 Hz, and averages
the signal 100. Data is adjusted to account for the dc blocking
capacitor impedance on the output at lower frequencies.

The general hardware configuration used for the AD8318

characterization is shown in Figure 47. The primary setup used
for characterization is measurement mode. The characterization
board is similar to the customer evaluation board with the
exception that the RF input has a Rosenberger SMA connector
and R10 has changed to a 1 k resistor to remove cable
capacitance from the bench characterization setup. Slope and
intercept are calculated in this data sheet and in the production
environment using linear regression from 50 dBm to 10 dBm.
The slope and intercept generate an ideal line. Log conformance
error is the difference from the ideal line and the measured
output voltage for a given temperature in dB. For additional
information on the error calculation, refer to the Device
Calibration and Error Calculation section.
The hardware configuration for pulse response measurement
replaces the 0 series resistor at the VOUT pin with a 40
resistor; the CLPF pin remains open. Pulse response time is
measured using a Tektronix TDS5104 digital phosphor
oscilloscope. Both channels on the scope are configured for
50 termination. The 10 internal series resistance at VOUT,
combined with the 40 resistor, attenuates the output voltage
level by two. RF input frequency is set to 100 MHz with
10 dBm at the input of the device. The RF burst is generated
using a Rohde & Schwarz SMT06 with the pulse option with a
period of 1.5 s, a width of 0.1 s, and a pulse delay of 0.04 s.
The output response is triggered using the video output from
the SMT06. Refer to Figure 47 for an overview of the test setup.

ROHDE & SCHWARZ

SMT06

TEKTRONIX
TDS5104

RF OUT
7dBm

5V

3dB
SPLITTER 1nF
INHI
52.3

VPOS
VOUT

40

*50
TERMINATION

AD8318
INLO

1nF

CH1* CH3* TRIGGER

VSET
GND
04853-046

VIDEO
OUT

Figure 47. Pulse Response Measurement Test Setup

Rev. B | Page 21 of 24

AD8318
EVALUATION BOARD
Table 6. Evaluation Board (Rev. A) Bill of Materials
Component
VP, GND
SW1, R3

R1, C1, C2

R2
R4

R7, R8, R9, R10

R7, R8, R9, R10

C5, C6, C7, C8, R5, R6

C9

Function
Supply and Ground Connections
Device Enable. When in Position A, the ENBL pin is connected to VP and the
AD8318 is in operating mode. In Position B, the ENBL pin is grounded through
R3, putting the device in power-down mode. The ENBL pin may be exercised
by a pulse generator connected to ENBL SMA and SW1 in Position B.
Input Interface. The 52.3 resistor (R1) combines with the AD8318 internal
input impedance to give a broadband input impedance of 50 . C1 and C2 are
dc-blocking capacitors. A reactive impedance match can be implemented by
replacing R1 with an inductor and C1 and C2 with appropriately valued
capacitors.
Temperature Sensor Interface. The temperature sensor output voltage is
available at the SMA labeled TEMP via the current limiting resistor, R2.
Temperature Compensation Interface. The internal temperature compensation
resistor is optimized for an input signal of 2.2 GHz when R4 is 500 . This circuit
can be adjusted to optimize performance for other input frequencies by
changing the value of Resistor R4. See the Temperature Compensation of
Output Voltage section.
Output InterfaceMeasurement Mode. In measurement mode, a portion of
the output voltage is fed back to the VSET pin via R7. The magnitude of the
slope at VOUT can be increased by reducing the portion of VOUT that is fed back
to VSET. R10 can be used as a back-terminating resistor or as part of a singlepole, low-pass filter.
Output InterfaceController Mode. In this mode, R7 must be open. In
controller mode, the AD8318 can control the gain of an external component. A
setpoint voltage is applied to the VSET pin, the value of which corresponds to
the desired RF input signal level applied to the AD8318 RF input. The
magnitude of the control voltage is optionally attenuated via the voltage
divider comprised of R8 and R9, or a capacitor can be installed in R8 to form a
low-pass filter along with R9. See the Controller Mode section for more details.
Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF
filter capacitor placed physically close to the AD8318, a 0 series resistor, and
a 0.1 F capacitor placed closer to the power supply input pin.

Loop Filter Capacitor. The low-pass corner frequency of the circuit that drives
the VOUT pin can be lowered by placing a capacitor between CLPF and
ground. Increasing this capacitor increases the overall rise/fall time of the
AD8318 for pulsed input signals. See the Output Filtering section for more details.

Rev. B | Page 22 of 24

Default Conditions
Not Applicable
SW1 = A
R3 = 10 k (Size 0603)

R1 = 52.3 (Size 0402)

C1 = 1 nF (Size 0402)
C2 = 1 nF (Size 0402)
R2 = 1 k (Size 0402)
R4 = 499 (Size 0603)

R7 = 0 = (Size 0402)
R8 = open (Size 0402)
R9 = open (Size 0402
R10 = 0 (Size 0402)
R7 = open (Size 0402)
R8 = open (Size 0402)
R9 = 0 (Size 0402)
R10 = 0 (Size 0402)

C5 = 0.1 F (Size 0603)

C6 = 100 pF (Size 0402)
C7 = 100 pF (Size 0402)
C8 = 0.1 F (Size 0603)
R5 = 0 (Size 0603)
R6 = 0 (Size 0603)
C9 = open (Size 0603)

AD8318
VPOS
R4
499

12

ENBL

R1
52.3

C2 1nF

A
R3
10k

C6
100pF

SW1

13

TEMP

14

INHI

15

INLO

16

ENBL

CMOP 8

AD8318

GND

VOUT 6

R8
OPEN
R7
0

VPSI

VPSI

VP

R6
0

VPOS

R9
OPEN
R10
0

CLPF 5

CMIP CMIP
VPOS

VSET 7

VSET
VOUT

C9
OPEN

C7
100pF
C8
0.1F

04853-035

C1 1nF
RFIN

10

C5
0.1F

CMIP CMIP TADJ VPSO

R2
1k

TEMP

11

R5
0

04853-036

04853-037

Figure 48. Evaluation Board Schematic

Figure 50. Component Side Silkscreen

Figure 49. Component Side Layout

Rev. B | Page 23 of 24

AD8318
OUTLINE DIMENSIONS
4.00
BSC SQ

PIN 1
INDICATOR

0.65 BSC

TOP
VIEW

12 MAX

3.75
BSC SQ

0.75
0.60
0.50

(BOTTOM VIEW)

13
12

16

PIN 1
INDICATOR
1

2.25
2.10 SQ
1.95

EXPOSED
PAD
9

0.25 MIN
1.95 BSC

0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM

SEATING
PLANE

0.35
0.30
0.25

0.20 REF

COPLANARITY
0.08

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

010606-0

1.00
0.85
0.80

0.60 MAX
0.60 MAX

Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters

ORDERING GUIDE
Model
AD8318ACPZ-REEL7 1
AD8318ACPZ-R21
AD8318ACPZ-WP1, 2
AD8318-EVALZ1
1
2

Temperature Range
40C to +85C
40C to +85C
40C to +85C

Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board

Z = RoHS compliant part.

WP = waffle pack.

2004-2007 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04853-0-4/07(B)

Rev. B | Page 24 of 24

Package Option
CP-16-4
CP-16-4
CP-16-4

Ordering
Quantity
1,500
250
64