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Slide Set 3 Pass Transistor Logic / Transmission Gates

This document summarizes a lecture on implementing logic functions using pass-transistor logic and transmission-gate logic. It discusses how NMOS pass-transistor logic has degraded output signals but can implement some functions efficiently. It then introduces CMOS transmission-gate logic, which avoids output degradation by using complementary signals but requires more control lines. Examples of implementations discussed include multiplexers, XOR gates, parity generators, shifters, and 2-1 multiplexers. Students are assigned to design an XOR gate using both CMOS gates and transmission gate logic.

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56 views20 pages

Slide Set 3 Pass Transistor Logic / Transmission Gates

This document summarizes a lecture on implementing logic functions using pass-transistor logic and transmission-gate logic. It discusses how NMOS pass-transistor logic has degraded output signals but can implement some functions efficiently. It then introduces CMOS transmission-gate logic, which avoids output degradation by using complementary signals but requires more control lines. Examples of implementations discussed include multiplexers, XOR gates, parity generators, shifters, and 2-1 multiplexers. Students are assigned to design an XOR gate using both CMOS gates and transmission gate logic.

Uploaded by

MalliKarjun
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Slide Set 3

Pass Transistor Logic / Transmission Gates

Steve Wilton
Dept. of ECE
University of British Columbia
stevew@ece.ubc.ca

Slide Set 3, Slide 1

Overview

Reading
Wolf 3.4, 4.7

Introduction
In the last lecture, we talked about how simple CMOS gates can be
built. In this lecture, we will talk about another way to implement logic
functions using transistors: pass-transistor logic (NMOS only) and
transmission-gate logic (NMOS and CMOS transistors). For some
types of functions, this can lead to much more efficient implementations
than using gates.

Slide Set 3, Slide 2

Switch Networks
Board Notes:
- Series Connections, Parallel Connections
- Multiplexer circuit

Slide Set 3, Slide 3

Multiplexer

A very useful switch network in an input multiplexer. It simply selects


one of the inputs to the output. This structure can be used to easily
map any logical function into switch logic -- all that needs to be done is
present the right constant vector to the inputs of the multiplexer.

Z
Output

Constants
Slide Set 3, Slide 4

Muxes

For some functions you can do better than just using constants
and a multiplexer. You can implement an XOR gate in only two
transistors (if you assume that both the inputs and their
complements are available)

Notice also the change in floorplan with the inputs staying on


poly makes it more compact

B
A

Slide Set 3, Slide 5

Parity
A more complex switch logic function:
A XOR B XOR C XOR D

XOR

XOR

XOR

XNOR

XNOR

XNOR

Each stage looks like:


Even

Even Out

Odd

Odd Out
A_b

Slide Set 3, Slide 6

Parity of Three Inputs

A_b

Even

Odd
B_b

C_b

Can cascade them to form a larger structure

Slide Set 3, Slide 7

Binary Shifter
Right nop Left

Ai

Bi

Ai-1

Bi-1
Bit-Slice i

...
Source: Jan Rabaey, 1995

Slide Set 3, Slide 8

Barrel Shifter
A3

B3

Sh1
A2
B2

Sh2

: Data Wire

A1
B1

: Control Wire

Sh3
A0
B0

Sh0

Sh1

Sh2

Sh3

Source: Jan Rabaey, 1995


Slide Set 3, Slide 9

Barrel Shifter Layout


A3

A2

A1

A0

Sh0

Sh 1

S h2

Sh3

Buffer
Source: Jan Rabaey, 1995
Slide Set 3, Slide 10

NMOS Switch Logic


Problem: there must be at least Vth between gate and source for
transistor to conduct.
What does this mean?
Vdd
This is > Vth so we are OK
Drive signal

Slide Set 3, Slide 11

NMOS Switch Logic


Problem: there must be at least Vth between gate and source for
transistor to conduct.
What does this mean?
Vdd

Vdd
This is < Vth. Problem!

Drive signal

Vdd

Vdd?

Slide Set 3, Slide 12

NMOS Switch Logic


Problem: there must be at least Vth between gate and source for
transistor to conduct.
What does this mean?
Vdd

Vdd
This is < Vth. Problem!

Drive signal

Vdd

Vdd?
Vdd-Vth

Moral: NMOS transistors:


Degraded signal
- pass 0 well
- when passing a 1, there is a Vth voltage drop
Slide Set 3, Slide 13

NMOS Switch Logic


What about this?
Vdd

Vdd

Vdd

Vdd

Vdd

Slide Set 3, Slide 14

NMOS Switch Logic


What about this?
Vdd

Vdd

Vdd

Dont drive gates with degraded signals

Slide Set 3, Slide 15

CMOS Transistors

NMOS
connected when gate is high
high output is degraded

PMOS
connected when gate is low

Vdd -Vth - weak


Gnd

-strong

Vdd

- strong

Vth

- weak

low output is degraded

Slide Set 3, Slide 16

CMOS Switches
By using both NMOS and PMOS neither output is degraded
But you need the true and complement of the control signal

Other symbols used

A
Full Swing Output

Slide Set 3, Slide 17

CMOS Switches
Example: 2-1 Mux:
SelA

SelA

CMOS switch logic need a large number of control wires


Each control is needed in true and complement form
For 2-1 Mux this works out well, but for a 3-1 mux, this
means 6 control signals
SelA, SelB, SelC and their complements
Slide Set 3, Slide 18

2-1 Mux Stick Diagram


Vdd
A

Out

ndiff
pdiff

B
poly
metal1
metal2
Gnd
Often M2 or poly (see note)
Note: usually, all metals lines in one direction are on one layer
and all metal lines in other direction are on another layer.
Here we cheated a bit.
Slide Set 3, Slide 19

Take Home Exercise

Design an exclusive-or gate in two ways:


1. Using CMOS gates
2. Using transmission gate logic
How many transistors does each use? Which is more efficient?

Slide Set 3, Slide 20

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