A paper in IEEE 2015 NEWCAS conference describing a charge-pump phase-locked loop with ultra-low power and high temperature stability for implant systems.
A paper in IEEE 2015 NEWCAS conference describing a charge-pump phase-locked loop with ultra-low power and high temperature stability for implant systems.
A paper in IEEE 2015 NEWCAS conference describing a charge-pump phase-locked loop with ultra-low power and high temperature stability for implant systems.
A paper in IEEE 2015 NEWCAS conference describing a charge-pump phase-locked loop with ultra-low power and high temperature stability for implant systems.
Anh Chu, Navneeta Deo, Waqas Ahmad, Markus Trmnen and Henrik Sjland Department of Electrical and Information Technology (EIT), Lund University, Lund, Sweden Email: soc13ac1@student.lu.se, soc13nna@student.lu.se
AbstractAn ultra-low power fully-integrated frequency synthesizer was designed and implemented in 130 nm CMOS technology. Based on integer-N phase locked loop architecture, the frequency synthesizer operates from 13.8 to 61 MHz. Current consumption has been minimized by the use of a mix of analog and digital blocks and a prior planning of current distribution amongst each blocks. The measured phase noise is -89.6 dBc/Hz @ 500 kHz offset and the current consumption is 77 A from 1.2 V supply at 32 MHz output. The reference frequency of 1 MHz is generated from an on-chip RC based oscillator whose output frequency varies by only 0.025% when temperature varies between -10 C to 110 C.
I. I NTRODUCTION Phase locked loops have been described in literature ever since 1923 [1]. But it was only in late 1970s that PLLs were used in modern communication systems due to the rapid development of integrated circuits. Since then the use of PLLs has been shifted from high precision instruments to more reliable consumer electronic products. A PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as in phase. In the synchronized (locked) state, the phase error between the oscillators output signal and the reference signal is zero, or it remains constant [2]. PLLs have wide applications such as frequency selective demodulation, signal conditioning, reference signal source, grid utility [3], [4]. From luxury items to indispensable tools, wireless systems have quickly penetrated into all aspects of our lives. All these devices have common requirements of a preferred monolithic implementation, low power, reduced physical size and high accuracy [5], [6]. This paper presents the design of a fully integrated low power phase locked loop system in 130 nm CMOS technology to be used as a clock generator for ultra-low power applications. To achieve full integration, reference signal is generated by an on-chip temperature independent RC oscillator thus avoiding an external reference source like crystal oscillator. The phase of reference signal is compared with output signal coming from the frequency divider in the phase frequency detector. Depending on the phase error, the charge pump in next stage pumps current into or out of the loop filter. In the next stage is a voltage controlled oscillator whose frequency keeps changing until lock is obtained, that is, until there is no phase error between reference and output signal. Once in locked state, VCO frequency becomes N times the reference frequency, where N is the division value of the divider. The c 978-1-4799-8893-8/15/$31.00
2015 IEEE
complete design including the RC oscillator occupies 0.8 mm2
excluding pads. The operating frequency is 13.861 MHz, hence it has potential for use in implantable medical devices. II. C IRCUIT I MPLEMENTATION The circuit consists of six main blocks: RC oscillator, phase frequency detector, charge pump, loop filter, voltage controlled oscillator and a frequency divider. A multiplexer which is used to select between the internal clock provided by RC oscillator or external clock serves as an auxiliary block. The complete block diagram is shown in Fig. 1. Charge pump
0.7-1.5 MHz RCO
step=25 kHz 1 0
VCO (13.8-61 MHz)
UP
fout=32fin
DOWN
ext_clk
Mux Loop filter f/32
Fig. 1. PLL block diagram
A. RC Oscillator (RCO) The RC relaxation oscillator works by continuously charging and discharging a capacitor [7] and is shown in Fig. 2a. The oscillation frequency is calculated as f = 0.722/(RC). The importance of the reference clock is that it must be robust to process, voltage and temperature variation (PVT) to keep the PLL output frequency stable. A design procedure including 2 steps was adopted: (1) Temperature compensation: Choosing values for R and C so that 1 MHz output is obtained, and R is large enough to compensate for temperature variation of the inverter resistance, which has a negative temperature coefficient. This step is done assuming typical corner. (2) Process compensation: Measure the maximal and minimal frequencies over process corners, break R into a base resistor connected in series with an array of 5 binary-weighted resistors. The resistance of the binary-weighted resistor array is activated by switches, so that an exact frequency of 1 MHz can be tuned in a post production step regardless of the process corner. 3.3 V NMOS transistors are used as switches as the 1.2 V NMOS is easily pushed into cut-off due to the full swing oscillating voltages at its drain and source terminals. Since the switch
control pins use 01.2 V, level shifter is used to convert this
range into 03.3 V. From step 1, component values of 210 k and 2 pF were selected. From step 2, R was found to be in range of 130 k 300 k to compensate for process corners. Since 5 switches were used, the base resistor is 130 k and the resistor array includes 5.5 k, 11 k, 22 k, 44 k and 88 k resistors. These values translate into a resolution of 25 kHz for trimming the frequency. 130-300Mk M 0.16/0.13
D. Voltage-Controlled Oscillator The VCO is a ring oscillator including 4 delay cells biased by a replica bias circuit. A CML to CMOS converter is used to convert the differential signal from the VCO to rail-to-rail square wave. The complete schematic is depicted by Fig. 3. The delay cells consist of two symmetric load blocks made up from a diode-connected PMOS in parallel with an equally sized PMOS. This load structure demonstrates a symmetric IV characteristic around the DC operating point and is capable of cancelling first-order coupling dynamic supply noise and improving the VCO phase noise [9] [10]. The small-signal gain of 1.7 V/V is chosen for delay cells, as a higher gain degrades phase noise due to broad range noise amplification, and a lower gain makes the oscillation process less robust to PVT [11]. The replica bias circuit generates bias voltages for the symmetric load and tail current source inside the delay cell, so that the symmetric load is biased at exactly its symmetric point [9] [10]. The circuit consists of an amplifier, a half-replica buffer and an output buffer. The amplifier is designed for high gain at dc to null its differential input, then the symmetric load of the half-replica buffer is biased at dc current doubled that of the symmetric loads inside the delay cell. As there are two load branches inside the delay cell, the delay cells are biased at their symmetric dc point. The output buffer is to isolate the control voltage from the delay cell, which may contribute lots of parasitic capacitance.
B. Phase-Frequency Detector The PFD circuit is shown in Fig. 2b. Two static D flipflops are used to detect rising edges of reference clock and feedback signal. The Q outputs are combined by an AND gate to reset the flip-flop states. Whenever there is a phase difference between the reference and feedback signals, a short pulse is generated at either UP or DOWN pins to charge or discharge the loop filter to minimize the phase error. The pulse duration is lengthened by a 50 ns RC delay block to eliminate the dead zone problem, which can put a lower limit on the PFD phase error in locked condition [8].
Vctrl
VbP
VbP
VbN
VbN
VbP
VbN
VbN
V Replica) bP VbN Bias
2a5 Symmetric Load
Vctrl
1/0.63
1/0.63
1/0.63
1/0.63 VbP
1/0.63
1/0.63 VbP
inM 3/5.4
2/2.6
2/2.6
in-
3/5.4 VbN
Amplifier
1/0.63
out- outM
4/2.6
4/2.6
C. Charge Pump A charge pump circuit is used to convert the logical state of phase frequency detector to voltage related information. This is done by generating charging or discharging current of 2 A depending on the output coming from phase frequency detector. The output from the charge pump enters the loop filter which controls the VCO. A topology which provides equal delay on both PMOS and NMOS current mirror is chosen as shown in Fig. 2c. Vbias of 600 mV is selected to put the switch transistors P2 and M2 in saturation. Then, P1-P2 and M1-M2 are in cascode configuration to increases the output impedance of the current sources. This reduces variations in charging/discharging currents which in turn help in maintaining VCO control voltage constant which results in reduction of spurs.
E. Frequency Divider The circuit includes five divide-by-two blocks in cascade to obtain a division of 32. The divide-by-two block consists of two cascaded static complementary D latches [12] connected within a negative feedback loop.
F. Loop Filter A second order passive loop filter was realized. The loop bandwidth and phase margin were selected to be 100 kHz (i.e. 1/10 of the reference frequency) and 50 degree, respectively. The component values are calculated from linear model [13] with VCO gain obtained from schematic simulations. Values of (21 k + 207 pF)//31.7 pF were selected. The simulated loop gain and phase margin are shown in Fig. 4.
instead of the designed 100 kHz. We suspect this due to the
process variation of the VCO, which affects the VCO gain. Phase noise is measured to be -78.3 dBc/Hz at 250 kHz offset and -89.6 dBc/Hz at 500 kHz offset. The reference spur is 29.7 dBc.
Fig. 4. Simulated phase margin and loop bandwidth in Matlab
6.2 dBm x
III. M EASUREMENT R ESULTS
The PLL chip was fabricated in a 130 nm CMOS process. Chip micrograph is shown by Fig. 5. Die area is 0.8 mm2 excluding pads.
29.7 dBc
1.28 mm
0.62 mm
Loop Filter
PFD RCO
VCO
Fig. 5. Chip micrograph. Die area = 0.8 mm2 (excl. pads)
The PLL output spectrum was measured using an FSEA20
Rhode&Schwarz Spectrum Analyzer. By using internal oscillator the output range is 21.447.5 MHz, indicating a range of 0.71.5 MHz of the internal oscillator. When driven by an external clock from a DG1000Z Rigol Waveform Generator the output range is 13.861 MHz. Fig. 6 and Fig. 7 show phase noise and reference spur at 32 MHz output when using the internal oscillator as the reference. The observed loop bandwidth is about 250 kHz
Fig. 7. Peak power and reference spur at 32 MHz output (internal clock selected)
Phase noise variation with output frequency is shown in
Fig. 8. Phase noise is stable when either internal or external clock is selected. This behavior is different from LC oscillator in which phase noise is improved with lower oscillation frequency [14]. The reason is the fundamental signal power is increased with frequency to compensate, as confirmed from VCO simulation. The measured current consumption of different blocks and whole PLL are as shown in Table I at 32 MHz output. The total current is 77 A, which is equivalent to 92.4 W from 1.2V supply. The total current dependence on output frequency is depicted in Fig. 8, which shows a linear increase of 3 A/MHz.
TABLE I C URRENT C ONSUMPTION @ 32MH Z OUTPUT. U NIT: A
Temperature Stability
0.025% (-10 110 C)
Die area
0.8 mm2 (excl. pads)
Output Frequency Range
200 -86
Phase Noise (ext. clk.)
Phase Noise (int. clk.)
-88 150 -90
-92
100
-94
-96
50
-98
-100
0 10
20
30
40
50
60
70
f_out (MHz)
Fig. 8. Current consumption and phase noise (500 kHz offset) versus frequency
The PLL performance variation with temperature is shown
in Fig. 9. Here the PLL is driven by the internal oscillator at 1 MHz. The output frequency is highly stable, with change of 0.025% over range of -10110 C. A peak frequency is observed at around 50 C and decreases with lower and higher temperature. This high stability shows the effectiveness of temperature stability technique used in the circuit. The phase noise and spur level are improved at higher temperature. The summary of PLL measured parameters is presented in Table II. -28 fmax
32.225 -85
32.220 -90
32.215
fmin
-95 -10
10
30
50
70
90
-30
-32
-34
-36
Reference Spur (dBc)
-80 Phase Noise (dBc/Hz)
f_out (MHz)
32.230
-38
110
Temperature (C)
Fig. 9. Variation with temperature of output frequency, phase noise (500 kHz offset from 32 MHz output) and reference spur (from on-chip oscillator)
IV. C ONCLUSION We have demonstrated a low frequency PLL for ultra-low power applications. The PLL multiplies a reference frequency provided by an on-chip RC oscillator or by an external clock source by 32 times. The VCO frequency range is 13.8 61 MHz. A low power of 92.4 W from 1.2 V supply is
measured for 32 MHz output. The RC oscillator shows good
temperature stability with 0.025% frequency variation over range -10110 C. The PLL was implemented in a 130 nm CMOS process by master students in the course analog IC-project at Lund University. Chip verification was done in RF Lab at the same university. ACKNOWLEDGMENT Thanks to Gran Jnsson at EIT, Lund University for support in chip measurements. R EFERENCES [1] E. V. Appleton, "Automatic synchronization of triode oscillators" in Proc. Cambridge Phil. Society, vol. 21, pt. III, p. 231, 1922-23. [2] Floyd M. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Trans. On Commun., pp. 18491858, Nov. 1980. [3] G. C. Hsieh and J. C. Hung, "Phase-locked loop techniquesA survey," IEEE Trans. Ind. Electron., vol. 43, no. 6, pp. 609615, Dec. 1996. [4] L. R. Limongi, R. Bojoi, C. Pica, F. Profumo, and A. Tenconi, "Analysis and comparison of phase locked loop techniques for grid utility applications," in Proc. IEEE Power Convers. Conf., pp. 674681, 2007. [5] Ippolito, C. M. , Italia A. , Palmisano G. , "An ultra low-power CMOS frequency synthesizer for low data-rate sub-GHz applications," in Ph.D. Research in Microelectronics and Electronics (PRIME) Conf., pp. 14, 2010. [6] B. Razavi, "Challenges in the design of frequency synthesizers for wireless applications," in Proc. IEEE Custom Integrated Circuits Conf., Santa Clara, CA, USA, pp. 395402, May 1997. [7] Paul Horowitz and Winfielf Hill, The Art of Electronics, 2nd ed. Cambridge, UK: Cambridge Univ. Press, 1994. [8] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill, 2001. [9] John G. Maneatis and Mark Horowitz, "Precise Delay Generation Using Coupled Oscillators," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 12731282, Dec. 1993. [10] John G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 17231732, Nov. 1996. [11] Todd Charles Weigandt, "Low-Phase-Noise, Low-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers," University of California, Berkeley, PhD dissertation, 1998. [12] J. Rabaey, Digital Integrated Circuits - A Design Perspective, 2nd ed. Eagle Cliffs, NJ: Prentice-Hall, 2003. [13] Dean Banerjee, PLL Performance Simulation and Design Handbook, 2nd ed.: National Semiconductor Technical Documents, 2001. [14] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge University Press, 1998.
