Required reading

ECE 545
Lecture 5

P. Chu, RTL Hardware Design using VHDL

Chapter 4, Concurrent Signal Assignment
Statements of VHDL

Data Flow Modeling of

Combinational Logic

George Mason University

VHDL Design Styles

VHDL Design
Styles
Testbenches

dataflow

Dataflow VHDL Design Style

Concurrent
statements

structural
Components and
interconnects

behavioral
(sequential)
Sequential statements
Registers
State machines
Instruction decoders

Subset most suitable for synthesis

ECE 448 FPGA and ASIC Design with VHDL

Register Transfer Level (RTL) Design Description

Synthesizable VHDL

Todays Topic

Dataflow VHDL
Design Style

VHDL code
synthesizable
Combinational
Logic

Dataflow VHDL
Design Style

Combinational
Logic

VHDL code
synthesizable
Registers

Data-Flow VHDL

Data-flow VHDL

Concurrent Statements

Major instructions

concurrent signal assignment

()

conditional concurrent signal assignment

(when-else)

selected concurrent signal assignment

(with-select-when)

generate scheme for equations

(for-generate)

Concurrent statements

concurrent signal assignment

()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)

Data-flow VHDL: Example

Data-flow VHDL: Example (1)

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

x
y

cin

ENTITY fulladd IS
PORT ( x
: IN
y
: IN
cin
: IN
s
: OUT
cout : OUT
END fulladd ;

cout

STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;

Data-flow VHDL: Example (2)

10

Logic Operators
Logic operators
and

ARCHITECTURE dataflow OF fulladd IS

BEGIN
s
<= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END dataflow ;

or

nand

nor

xor

not

Logic operators precedence

only in VHDL-93
or later

Highest
and

or

nand

not
nor

xnor

xor

xnor

Lowest

11

12

No Implied Precedence

E.g.,
status <= '1';
even <= (p1 and p2) or (p3 and p4);
arith_out <= a + b + c - 1;

Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d

Implementation of last statement

Correct
y <= (a and b) or (c and d) ;
RTL Hardware Design

Chapter 4

14

13

Signal assignment statement with a

closed feedback loop

Data-flow VHDL
Major instructions

a signal appears in both sides of a

concurrent assignment statement
E.g.,
q <= ((not q) and (not en)) or (d and en);
Syntactically correct
Form a closed feedback loop
Should be avoided
RTL Hardware Design

Chapter 4

Concurrent statements

concurrent signal assignment

()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)

15
16

Conditional concurrent signal assignment

Most often implied structure

When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

Value N
Value N-1

0
1

0
1

0
1

Value 2

Target Signal

Value 1

Condition N-1
Condition 2

Condition 1

17

18

2-to-1 abstract mux

sel has a data type of boolean
If sel is true, the input from T port is connected
to output.
If sel is false, the input from F port is connected
to output.

RTL Hardware Design

Chapter 4

19

RTL Hardware Design

Chapter 4

20

RTL Hardware Design

Chapter 4

21

RTL Hardware Design

Chapter 4

22

Chapter 4

24

E.g.,

RTL Hardware Design

E.g.,

Chapter 4

23

RTL Hardware Design

 E.g.,

RTL Hardware Design

Chapter 4

25

RTL Hardware Design

Signed and Unsigned Types

Chapter 4

26

Operators
Relational operators

Behave exactly like

STD_LOGIC_VECTOR
plus, they determine whether a given vector
should be treated as a signed or unsigned number.
Require
USE ieee.numeric_std.all;

/=

<

<=

>

>=

Logic and relational operators precedence

Highest
Lowest

not
=
and

/=
or

<
nand

<=
nor

>
xor

27

>=
xnor

28

VHDL operators

Priority of logic and relational operators

compare a = bc
Incorrect
when a = b and c else
equivalent to
when (a = b) and c else
Correct
when a = (b and c) else

29

30

Selected concurrent signal assignment

Data-flow VHDL
Major instructions
Concurrent statements

With Select-When

concurrent signal assignment

()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)

with choice_expression select

target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

31

32

Allowed formats of choices_k

Most Often Implied Structure

With Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

expression1

choices_1

expression2

choices_2

expressionN

choices_N

WHEN value
WHEN value_1 | value_2 | .... | value N
WHEN OTHERS

target_signal

choice expression
33

34

Allowed formats of choice_k - example

Syntax
Simplified syntax:

WITH sel SELECT

y <= a WHEN "000",
c WHEN "001" | "111",
d WHEN OTHERS;

with select_expression select

signal_name <=
value_expr_1 when choice_1,
value_expr_2 when choice_2,
value_expr_3 when choice_3,
...
value_expr_n when choice_n;
RTL Hardware Design

Chapter 4

36

35

E.g., 4-to-1 mux

select_expression
Discrete type or 1-D array
With finite possible values

choice_i
A value of the data type

Choices must be
mutually exclusive
all inclusive
others can be used as last choice_i

RTL Hardware Design

Chapter 4

37

RTL Hardware Design

Chapter 4

38

E.g., 2-to-22 binary decoder

Can 11 be used to replace others?

RTL Hardware Design

Chapter 4

39

RTL Hardware Design

Chapter 4

40

Chapter 4

42

E.g., 4-to-2 priority encoder

Can we use -?

RTL Hardware Design

Chapter 4

41

RTL Hardware Design

E.g., simple ALU

RTL Hardware Design

Chapter 4

E.g., Truth table

43

RTL Hardware Design

Chapter 4

44

Conceptual implementation
select_expression is with a data type of 5
values: c0, c1, c2, c3, c4

Achieved by a
multiplexing circuit
Abstract (k+1)-to-1
multiplexer
sel is with a data type
of (k+1) values:
c0, c1, c2, . . . , ck

RTL Hardware Design

Chapter 4

45

RTL Hardware Design

Chapter 4

46

Chapter 4

48

E.g.,

RTL Hardware Design

Chapter 4

47

RTL Hardware Design

3. Conditional vs. selected signal

assignment

From selected assignment to

conditional assignment

Conversion between conditional vs.

selected signal assignment
Comparison

RTL Hardware Design

Chapter 4

49

RTL Hardware Design

From conditional assignment to

selected assignment

Chapter 4

50

Comparison
Selected signal assignment:
good match for a circuit described by a
functional table
E.g., binary decoder, multiplexer
Less effective when an input pattern is given a
preferential treatment

RTL Hardware Design

Chapter 4

51

good match for a circuit a circuit that needs to

give preferential treatment for certain
conditions or to prioritize the operations
E.g., priority encoder
Can handle complicated conditions. e.g.,

Chapter 4

Chapter 4

52

May over-specify for a functional table

based circuit.
E.g., mux

Conditional signal assignment:

RTL Hardware Design

RTL Hardware Design

53

RTL Hardware Design

Chapter 4

54

MLU Block Diagram

0

A1

MUX_0

MUX_4_1

NEG_A

MLU Example

MUX_1
MUX_2

Y1

IN0
IN1
IN2

OUTPUT

SEL0
IN3
SEL1

NEG_Y
0

B1

L1 L0

MUX_3

NEG_B

55

56

MLU: Architecture Declarative

Section

MLU: Entity Declaration

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ARCHITECTURE mlu_dataflow OF mlu IS

SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL

ENTITY mlu IS
PORT(
NEG_A : IN STD_LOGIC;
NEG_B : IN STD_LOGIC;
NEG_Y : IN STD_LOGIC;
A:
IN STD_LOGIC;
B:
IN STD_LOGIC;
L1 :
IN STD_LOGIC;
L0 :
IN STD_LOGIC;
Y:
OUT STD_LOGIC
);
END mlu;

A1 : STD_LOGIC;
B1 : STD_LOGIC;
Y1 : STD_LOGIC;
MUX_0 : STD_LOGIC;
MUX_1 : STD_LOGIC;
MUX_2 : STD_LOGIC;
MUX_3 : STD_LOGIC;
L: STD_LOGIC_VECTOR(1 DOWNTO 0);

57

58

MLU - Architecture Body

BEGIN
A1<= NOT A WHEN (NEG_A='1') ELSE
A;
B1<= NOT B WHEN (NEG_B='1') ELSE
B;
Y <= NOT Y1 WHEN (NEG_Y='1') ELSE
Y1;
MUX_0 <= A1
MUX_1 <= A1
MUX_2 <= A1
MUX_3 <= A1

Modeling Common Combinational

Logic Components
Using Dataflow VHDL

AND B1;
OR B1;
XOR B1;
XNOR B1;

L <= L1 & L0;

with (L) select
Y1 <= MUX_0
MUX_1
MUX_2
MUX_3

WHEN "00",
WHEN "01",
WHEN "10",
WHEN OTHERS;

END mlu_dataflow;
59

ECE 448 FPGA and

ASIC Design with VHDL

10

Signals
SIGNAL a : STD_LOGIC;

a
1

Wires and Buses

wire

SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

b
bus

ECE 448 FPGA and ASIC Design with VHDL

61

Merging wires and buses

62

Splitting buses

a
4

10

10
5

c
SIGNAL
SIGNAL
SIGNAL
SIGNAL

b
c

a:
b:
c:
d:

SIGNAL
SIGNAL
SIGNAL
SIGNAL

STD_LOGIC_VECTOR(3 DOWNTO 0);

STD_LOGIC_VECTOR(4 DOWNTO 0);
STD_LOGIC;
STD_LOGIC_VECTOR(9 DOWNTO 0);

a:
b:
c:
d:

STD_LOGIC_VECTOR(3 DOWNTO 0);

STD_LOGIC_VECTOR(4 DOWNTO 0);
STD_LOGIC;
STD_LOGIC_VECTOR(9 DOWNTO 0);

a <= d(9 downto 6);

b <= d(5 downto 1);
c <= d(0);

d <= a & b & c;

63

64

Fixed Shift in VHDL

SIGNAL A :
STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);

A(3) A(2) A(1) A(0)

Fixed Shifters & Rotators

A
A>>1
AshiftR
0

A(3) A(2) A(1)

AshiftR <=
ECE 448 FPGA and ASIC Design with VHDL

65

66

11

Fixed Rotation in VHDL

SIGNAL A :
STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);

A(3) A(2) A(1) A(0)

Buffers

A
A<<<1
ArotL
A(2) A(1) A(0) A(3)

ArotL <=
67

ECE 448 FPGA and ASIC Design with VHDL

68

Four types of Tri-state Buffers

Tri-state Buffer
e
x

f
e=0

(a) A tri-state buffer

0
0
1
1

0
1
0
1

Z
Z
0
1

e=1
x

(b) Equivalent circuit

(c) Truth table

69

Tri-state Buffer example (1)

70

Tri-state Buffer example (2)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ARCHITECTURE dataflow OF tri_state IS

BEGIN
output <= input WHEN (ena = 1) ELSE Z;
END dataflow;

ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC;
output: OUT STD_LOGIC
);
END tri_state;

71

72

12

2-to-1 Multiplexer

s
f

s
w

Multiplexers

0
1

(b) Truth table

(a) Graphical symbol

ECE 448 FPGA and ASIC Design with VHDL

73

VHDL code for a 2-to-1 Multiplexer

74

Cascade of two multiplexers

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
w

ENTITY mux2to1 IS
PORT ( w0, w1, s : IN
STD_LOGIC ;
f
: OUT STD_LOGIC ) ;
END mux2to1 ;

3
2

0
0
1

y
1

s2

ARCHITECTURE dataflow OF mux2to1 IS

BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;

s1

75

76

VHDL code for a cascade of

two multiplexers

4-to-1 Multiplexer

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
s

ENTITY mux_cascade IS
PORT ( w1, w2, w3: IN STD_LOGIC ;
s1, s2
: IN STD_LOGIC ;
f
: OUT STD_LOGIC ) ;
END mux_cascade ;

w
w
w
w

ARCHITECTURE dataflow OF mux2to1 IS

BEGIN
f <= w1 WHEN s1 = 1' ELSE
w2 WHEN s2 = 1 ELSE
w3 ;
END dataflow ;

00

01

10

11

(a) Graphic symbol

77

0
1
2
3

(b) Truth table

78

13

VHDL code for a 4-to-1 Multiplexer

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3
s
f
END mux4to1 ;

: IN
: IN
: OUT

STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;

Decoders

ARCHITECTURE dataflow OF mux4to1 IS

BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END dataflow ;

79

2-to-4 Decoder

ECE 448 FPGA and ASIC Design with VHDL

80

VHDL code for a 2-to-4 Decoder

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

En w w
1 0

(a) Truth table

ENTITY dec2to4 IS
PORT ( w : IN
En : IN
y
: OUT
END dec2to4 ;

0
w
1
w
0

y
y
y

En

3
2

STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

ARCHITECTURE dataflow OF dec2to4 IS

SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= 0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
1000" WHEN "111",
"0000" WHEN OTHERS ;
END dataflow ;

1
0

(b) Graphical symbol

81

82

Priority Encoder
w0

y0

w1

y1

w2

w3

Encoders

w3 w 2 w 1 w0
0
0
0
0
1
ECE 448 FPGA and ASIC Design with VHDL

83

0
0
0
1
x

0
0
1
x
x

0
1
x
x
x

y 1 y0

d
0
0
1
1

0
1
1
1
1

d
0
1
0
1

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14

VHDL code for a Priority Encoder

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT ( w : IN
y : OUT
z : OUT
END priority ;

STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;

ARCHITECTURE dataflow OF priority IS

BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END dataflow ;
85

15