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FPGA Implementation and Analysis of DES and

TWOFISH Encryption Algorithms
Thesis report submitted towards the partial fulfillment of
requirements for the award of the degree of
Master of Technology
In
VLSI Design & CAD

Submitted by
Amandeep Singh
Roll No. 600861002
Under the Guidance of
Mrs. Manu Bansal
Assistant Professor, ECED

Department of Electronics and Communication Engineering

THAPAR UNIVERSITY
PATIALA - 147004, INDIA
JULY - 2010

ACKNOWLEDGEMENT

First of all, I thank the Almighty God, who gave me the opportunity and strength to carry out this
work.
I would like to thank Mrs. Manu Bansal, Assistant Professor (ECED) for the opportunity to
work with her, and also for her encouragement, trust and untiring support. Mrs. Manu Bansal
has been an advisor in the true sense both academically and morally throughout this project
work.
Much appreciation is expressed to Prof. Abhijit Mukherjee, Director, Thapar University, and
Prof. R.K. Sharma, Dean of Academic Affairs to provide me moral support to go ahead with
my M.Tech Thesis work.
I thank to Mrs. Alpana Agarwal, Assistant Professor and PG Coordinator, ECED, Dr. A.K.
Chatterjee, Professor and Head, ECED and all the faculty of ECED for their continuous
inspiration during this thesis work.
The paucity of words does not compromise for extending my thanks to my all family members
and friends of M.Tech (VLSI & CAD Design) who were always there at the need of hour and
helped me in completing this research report.
I am also thankful to the authors whose work has been consulted, utilized and cited in my
dissertation.
Amandeep Singh
Roll No. 600861002

iii

ABSTRACT

There are many aspects to security ranging from secure commerce and payments to private
communications and protecting passwords. One essential aspect for secure communications is
that of secret key Cryptography. It is the automated method in which security goals are
accomplished. It includes the process of encryption that converts plain-text into cipher-text. The
process of decryption reconverts the cipher-text into plain-text. Secure communication is the
prime requirement of every organization. To achieve this, one can use many techniques or
algorithms available for Cryptography. Various models were developed for the encryption in
which keys were generated from the available data. Data Encryption Standard (DES) is the most
commonly used algorithm for security purpose that was announced by National Bureau of
Standard. It is the strongest algorithm but due to large processing time, it can be easily broken by
the eavesdroppers. Twofish algorithm is nowadays a strongest algorithm due to its large key
stream. An efficient encryption algorithm should consist of two factors fast response and
reduced complexity. Cryptosystems must satisfy three general requirements 1) the enciphering
and deciphering transformations must be efficient for all keys. 2) System must be easy to use. 3)
Security of the system should depend only on the secrecy of the keys and not on the secrecy of
the algorithms.
The main objective of this dissertation is to analyze the various aspects of DES and
Twofish algorithms.

iv

TABLE OF CONTENTS
CERTIFICATE

ii

ACKNOWLEDGEMENT

iii

ABSTRACT

iv

TABLE OF CONTENTS

LIST OF FIGURES

vii

LIST OF TABLES

viii

CHAPTER 1: INTRODUCTION

1.1 TERMS OF CRYPTOGRAPHY

1.2 OBJECTIVES

1.3 CRYPTOGRAPHY TECHNIQUES

1.3.1 DIGITAL SIGNATURES

1.4 TYPES OF CIPHERS

1.5 KEY MANAGEMENT

1.5.1 RULES FOR KEYS AND KEY MANAGEMENT

1.6 ORGANIZATION OF THESIS

8
8

CHAPTER 2: LITERATURE SURVEY

CHAPTER 3: DES ALGORITHM

16

3.1 DES CORE

17

3.2 DES ALGORITHM

18

3.3 STEPS FOR DES ALGORITHM

21

CHAPTER 4: TWOFISH ALGORITHM

35

4.1 WHITENING OPERATION

36

4.2 F FUNCTION

36

4.3 S BOXES

37

4.4 MDS MATRICES

38

4.5 PSEUDO-HADAMARD TRANSFORMS (PHT)

39

4.6 STEPS FOR TWOFISH ALGORITHM

39

CHAPTER 5: FPGA OVERVIEW

41

5.1 INTRODUCTION TO FPGA

41

5.2 DESIGN FLOW

43

5.2.1 DESIGN ENTITY

44

5.2.2 BEHAVIORAL SIMULATION

44

5.2.3 SYNTHESIS

44

5.2.4 DESIGN IMPLEMENTATION

44

5.2.5 FUNCTIONAL SIMULATION

44

5.2.6 STATIC TIMING ANALYSIS

45

5.2.7 DEVICE PROGRAMMING

45

CHAPTER 6: EXPERIMENTAL RESULTS

46

6.1 SIMULATION RESULTS OF DES ALGORITHM

46

6.2 FPGA IMPLEMENTATION OF DES ALGORITHM

48

6.3 SIMULATION RESULTS OF TWOFISH ALGORITHM

49

6.4 SYNTHESIS REPORT OF LCD PROGRAMMING

51

6.5 DESIGN STATISTICS OF DES ALGORITHM

55

6.6 DEVICE UTILIZATION SUMMARY OF DES ALGORITHM

57

6.7 MACRO STATISTICS OF DES ALGORITHM

59

6.8 TIMING SUMMARY OF DES ALGORITHM

61

6.9 DESIGN STATISTICS OF TWOFISH ALGORITHM

63

6.10 DEVICE UTILIZATION SUMMARY OF TWOFISH ALGORITHM

65

6.11 MACRO STATISTICS OF TWOFISH ALGORITHM

67

6.12 TIMING SUMMARY OF TWOFISH ALGORITHM

70

CONCLUSION AND FUTURE SCOPE

74

REFERENCES

75

vi

LIST OF FIGURES
Figure 1.1: Symmetric cryptography

Figure 1.2: Asymmetric cryptography

Figure 1.3: Steps for digital signature generation

Figure 1.4: Steps for digital signature verification

Figure 3.1: DES Flow

16

Figure 3.2: DES Core

17

Figure 3.3: DES Algorithm

19

Figure 3.4: DES Fiestel Structure

20

Figure 4.1: Feistel Structure for Twofish Algorithm

36

Figure 4.2: Structure for S-boxes

37

Figure 4.3: q-Permutation Structure

38

Figure 5.1: FPGA Architecture

42

Figure 5.2: FPGA Design Flow

43

Figure 5.3: FPGA Spartan 3E Kit

45

Figure 6.1: DES Block

46

Figure 6.2: Simulation result of DES Encryption by Model Sim

47

Figure 6.3: Programming Completion of DES Encryption

48

Figure 6.4: Output Display of DES Encrypted Data

49

Figure 6.5: Twofish Encryption Block

49

Figure 6.6: Simulation result of Twofish Encryption by Model Sim

50

vii

LIST OF TABLES
Table 3.1: Pin Configuration of DES Core

18

Table 3.2: Permuted Choice 1

21

Table 3.3: Sub-key Rotation Table

22

Table 3.4: Permuted Choice 2

24

Table 3.5: Initial Permutation

25

Table 3.6: E-bit Selection Table

27

Table 3.7: S-box 1

29

Table 3.8: S-boxes

31

Table 3.9: P-Permutation Table

32

Table 3.10: Inverse Initial Permutation

33

viii

CHAPTER

1
INTRODUCTION
Security attacks against network are increasing significantly with time. Our
communication media should also be secure and confidential. For this purpose, these
three suggestions arrive in every ones mind: (i) one can transmit the message secretly, so
that it can be saved from hackers, (ii) the sender ensures that the message arrives to the
desired destination, and (iii) the receiver ensures that the received message is in its
original form and coming from the right sender. For this, one can use two techniques, (i)
one can use invisible ink for writing the message or can send the message through the
confidential person, and (ii) one can use a scientific approach called Cryptography.
Cryptography is the technique used to avoid unauthorized access of data. For
example, data can be encrypted using a cryptographic algorithm in conjunction with the
key management. It will be transmitted in an encrypted state, and later decrypted by the
intended party. If a third party intercepts the encrypted data, it will be difficult to
decipher. The security of modern cryptosystems is not based on the secrecy of the
algorithm, but on the secrecy of a relatively small amount of information, called a secret
key. The fundamental and classical task of cryptography is to provide confidentiality by
encryption methods.
Cryptography is used in applications present in technologically advanced
societies; examples include the security of ATM cards, computer passwords, and
electronic commerce, which all depend on cryptography.
Cryptanalysis is the study used to describe the methods of code-breaking or
cracking the code without using the security information, usually used by hackers.

CHAPTER 1 INTRODUCTION

1.1 Terms of Cryptography

The basic terms of Cryptography are:
Plain-text: the original message or data that is in readable form is known as plain-text.
Cipher-text: the encoded message is known as cipher-text.
Encryption: the process to convert the original message into coded form with the help of
key, i.e., plain-text into cipher-text is known as encryption.
Decryption: the reverse process of encryption, i.e., to convert cipher-text into plain-text
with the help of key is known as decryption.
Key: the key is used to encrypt or decrypt the message. It is of two types:
Private key
Public key

1.2 Objectives:
Cryptography is used to achieve the following goals:
Confidentiality:

Protection

against

unauthorized

disclosure

of

information.

Confidentiality may be applied to whole messages, parts of messages, and even existence
of messages [9]. Confidentiality is the protection of transmitted data from passive attacks.
Authentication: The authentication service is concerned with assuring that a
communication is authentic. It is the corroboration of the claimed source of a message.
Authentication is of two types: (i) Peer entity, and (ii) Data origin
Data integrity: The integrity can apply to a stream of messages, a single message, or
selected fields within a message. It assures that messages are received as sent, with no
duplication, insertion, modification, reordering, or replays. The destruction of data is also
covered under this service.
Access control: It is the ability to limit and control the access to host systems and
applications via communications links. To achieve this, each entity trying to gain access
must first be identified, or authenticated, so that access rights can be tailored to the
individual.
Nonrepudiation: Nonrepudiation prevents either sender or receiver from denying a
transmitted message. When a message is sent, the receiver can prove that the alleged
sender in fact sent the message.

CHAPTER 1 INTRODUCTION

1.3 Cryptography Techniques

There are two techniques used for data encryption and decryption, which are:
1. Symmetric Cryptography

If sender and recipient use the same key then it is known as symmetrical
or private key cryptography. It is always suitable for long data streams. Such
system is difficult to use in practice because the sender and receiver must know
the key. It also requires sending the keys over a secure channel from sender to
recipient.

Figure 1.1: Symmetric cryptography

The main concern behind symmetric encryption is how to share the secret
key securely between the two parties. If the key gets known for any reason, the
whole system collapses. The key management for this type of encryption is
troublesome when a unique secret key is used for each peer-to-peer connection.
The total number of secret keys to be saved and managed for n-nodes will
be nn 1 / 2 .
There are two cipher methods that are used in symmetric key
cryptography: Block cipher and Stream cipher. The block cipher method divides a
large data set into blocks and encrypts each block separately. Finally the blocks
are combined to produce encrypted data. The stream cipher method encrypts the
data as a stream of bits without separating the data into blocks. The stream of bits
from the data is encrypted sequentially using some of the results from the
previous bit until all the bits in the data are encrypted as a whole.
2. Asymmetric Cryptography

If sender and recipient use different keys then it is known as asymmetrical

or public key cryptography. The key used for encryption is called the public key

CHAPTER 1 INTRODUCTION
and the key used for decryption is called the private key. Such technique is used
for short data streams and also requires more time to encrypt the data.

Figure 1.2: Asymmetric cryptography

To encrypt a message, a public key can be used by anyone, but the owner having
private key can only decrypt it. There is no need for a secure communication
channel for the transmission of the encryption key. Asymmetric algorithms cannot
be applied to variable-length streams of data. Asymmetric keys are also called a
key-exchange pair. Asymmetric encryption techniques are slower than symmetric
techniques, because they require more computational processing power.
To get the benefits of both methods, a hybrid technique is usually used. In
this technique, asymmetric encryption is used to exchange the secret key;
symmetric encryption is then used to transfer data between sender and receiver. It
is easy to convert the private key into public key, but the reverse is very difficult.

1.3.1 Digital Signatures

Public key cryptography gives a major benefit by providing a method for
employment of digital signatures. Digital signatures and hand-written signatures both rely
on the fact that it is very hard to find two people with the same signature. The
authentication and data integrity are the two features of digital signatures by providing a
seal over a document or a handwritten signature. Anyone with access to the public key of
the signer may verify the signature. For example, in the field of E-commerce, an
instruction to your bank to transfer money can be authenticated with a digital signature.
Digital signatures cannot be copied to another document.

CHAPTER 1 INTRODUCTION
Digital Signature Generation:

Figure 1.3: Steps for digital signature generation [48]

The steps for the digital signature generation are as follows:
1) The message digest of the plain-text is computed, i.e., what type of data is text,
video, image, etc. and what is the length of the data is, etc.
2) This message digest will be encrypted using key techniques and a digital signature
is also attached before sending to the receiver.
3) The encrypted plain-text (including plain-text and digital signature) is sent to the
receiver.

CHAPTER 1 INTRODUCTION
Digital Signature Verification:

Figure 1.4: Steps for digital signature verification [48]

The steps for the digital signature verification are as follows:
1) The message digest of the file is evaluated for the verification purpose.
2) The encrypted file, i.e., cipher-text is decrypted using the key techniques.
3) After then the decrypted file and original file are compared for the verification. If
two files are same then the decrypted file will be accepted, otherwise, it will be
rejected.

CHAPTER 1 INTRODUCTION

1.4 Types of Ciphers

1. Substitution Cipher
A substitution cipher substitutes one piece of information for another. This
is most frequently done by offsetting letters of the alphabet. For example, if we
encode the word SECRET using Caesars key value of 3, we offset the alphabet
so that the 3rd letter down (D) begins the alphabet.
So starting with
ABCDEFGHIJKLMNOPQRSTUVWXYZ
and sliding everything up by 3, you get
DEFGHIJKLMNOPQRSTUVWXYZABC
where D=A, E=B, F=C, and so on.
Example:
THIS IS A SECRET (key n=3)
WKLV LV D VHFUHW
2. Transposition Cipher
Transposition means rearranging elements in the plain-image. The
permutation of bits decreases the perceptual information, whereas the permutation
of pixels and blocks produce high-level security. In the bit permutation
techniques, the bits in each pixel are permuted using the permutation keys with
the key length equal to 8. The number of permutations is = 8! = 40320 and the
number of keys are 121. In the pixel permutation, 8 pixels are taken as a group
and permuted with the same size key. The block size is (8 8) then it is difficult
to decrypt. To extract the image, a combinational sequence of permutations and
the permutation keys using pseudo random index generators should be known.
Example:

CHAPTER 1 INTRODUCTION

1.5 Key Management

Cryptography can be used as a security mechanism to provide confidentiality,
integrity, and authentication, but not if the keys are compromised in any way. The keys
have to be distributed to the right entities and updated continuously. The keys need to be
protected as they are being transmitted and while they are being stored on each
workstation and server. The keys need to be generated, destroyed, and recovered
properly. Key management can be handled through manual or automatic processes. The
frequency of use of a cryptographic key can have a direct correlation to how often the key
should be changed. The more a key is used, the more likely it is to be captured and
compromised. Keeping keys secret is a challenging task. Keys should not be in clear-text
outside the cryptography device

1.5.1 Rules for keys generation and their handling:

1. The key length should be of variable size for the highly secure communication.
2. Keys should be randomly selected by using the full spectrum of available key-space.
3. Multiple use of keys leads to short lifetime.
4. Keys should be properly destroyed when their lifetime is over.
5. For the secure communication, the keys are to be kept secret.

1.6 Organization of Thesis

The organization of the thesis is as follows:
Chapter 2: Gives the survey of literature conducted by various authors in the field of
Cryptography.
Chapter 3: Describes the details of DES Algorithm. In this chapter, the overview and the
steps of DES algorithm are discussed.
Chapter 4: Describes the details of Twofish Algorithm. In this chapter, the overview and
the steps of Twofish algorithm are discussed.
Chapter 5: Gives the overview of FPGA Spartan 3-E kit used for the implementation of
DES algorithm.
Chapter 6: Gives the results and conclusion of work done in thesis.
8

CHAPTER

2
LITERATURE SURVEY
Cryptography has a long and fascinating history. The most complete nontechnical account of the subject is Kahns The Code breakers that include cryptography
from its initial and limited use by the Egyptians some 4000 years ago, to the twentieth
century where it played a crucial role in the outcome of both world wars [1].
Beginning with the work of Feistel at IBM in the early 1970s and culminating in
1977 with the adoption as a U.S. Federal Information Processing Standard for encrypting
unclassified information, DES, the Data Encryption Standard, is the most well-known
cryptographic mechanism in history. The most striking development in the history of
cryptography came in 1976 when Diffie and Hellman published a transaction New
Directions in Cryptography. This paper introduced the revolutionary concept of publickey cryptography and also provided a new and ingenious method. Before the modern era,
cryptography was concerned solely with message confidentiality (i.e. encryption)
conversion of messages from a comprehensible form into an incomprehensible one and
back again at the other end, rendering it unreadable without secret knowledge (namely,
the key) [2]. In recent decades, the field has expanded beyond confidentiality concerns to
include techniques for authentication, digital signatures, interactive proofs, and secure
computation. For secure communication simple encryption devices such as Enigma
machine were used during World War II having improvement using three rotors to
substitute letters, a plug board, and a reflecting rotor. The advancement in encryption
methods came with the existence of computers.

CHAPTER 2 LITERATURE SURVEY

In 1978, Ruth M. Davis provides a hardware-implementable algorithm for
enciphering data, which has been adopted as a Federal standard to provide a high level of
cryptographic protection against various attacks [3].
In 1981, Whitfleld Diffie describes cryptographic technology, which examines
the forces driving public development of cryptography [4]. The paper describes how one
can secure the message over the telephone lines.
In 1988, Ingrid Verbauwhede describes Security and Performance Optimization
of a New DES Data Encryption Chip. Novel CAD tools are used at different steps in the
design process for simulation. The result is a single chip of 25 mm in 3-pm double-metal
CMOS. Functionality tests show that a clock of 16.7 MHz can be applied, which means
that a 32-Mbit/s data rate can be achieved for all eight byte modes [5].
In 1990, James E. Katz provides Social Aspects of Telecommunications Security
Policy that describes a system that offers a variety of convenient and powerful services
while meeting the legitimate needs of the individual for privacy and of society for
security [6].
In 1991, H. Bonnenbergt describes the VLSI implementation of a new block
cipher. The chip that runs with a maximum clock frequency of 33 MHz permitting a data
conversion rate of more than 55 Mbits/s performs data encryption and decryption in a
single hardware unit [7].
In 1992, K.H. Mundt SUPERCRYPT ASIC technology facilitates a new device
family for data encryption in which semi-custom cell-based ASIC technology is
described to get 100Mbits/s encryption speed on silicon applying 1 micron design rules
[8].
In 1993, C. Boyd provides the modern data encryption in which proposed
standard for digital signatures based on RSA were introduced [9]. A. Curigert describes
VINCI: VLSI Implementation of the new secret-key block Cipher IDEA. VINCIs IDEA
premier

silicon

realization,

integrates

high-speed

encryption

and

decryption,

comprehensive key management functions, and all standardized cipher modes of

operation in their ordinary and high-speed adapted versions [10].
In 1994, R. Zimmermann provides a 177 Mb/s VLSI implementation of the
international data encryption algorithm in which the VLSI chip implements data

10

CHAPTER 2 LITERATURE SURVEY

encryption and decryption in a single hardware unit. All-important standardized modes of
operation of block ciphers, such as ECB, CBC, CFB, OFB, and MAC, are supported.
Moreover, with a system clock frequency of 25 MHz the device permits a data
conversion rate of more than 177 Mb/s [11].
In 1995, Stefan Wolter provides the implementation of the IDEA architecture that
includes a concurrent self-test based on a mod3 residue code self-checking system. It
allows the detection of permanent and temporary single and multiple-bit errors in the
IDEA data-path. Hence it provides the secure prevention of faulty encrypted or decrypted
data [12].
In 1996, Seung-Jo Han describes the improved DES algorithm in which a 96-bit
data block is divided into three 32-bit sub-blocks to increase the Unicity Distance (UD)
by performing different f-functions on each of the sub-block [13].
In 1997, Toby Schaffer describes a Flip-Chip implementation of the DES. The
flip-chip/MCM environment provides advantages in driver performance, reduced die area
requirements, and high bandwidth for triple DES operation [14]. Suan-Suan Chew
provides IAuth: An Authentication System for Internet Applications that provides secure
distribution of cryptographic keys while establishing authenticity between a user and a
Web-based application [15].
In 1998, Hassina Guendouz describes rapid prototype of a fast data encryption
standard with integrity processing for cryptographic applications. It implements the DES
algorithm in the same silicon area with high-speed performance based on VHDL
specifications [16]. K. Wong provides a single-chip FPGA implementation of the Data
Encryption Standard (DES) algorithm describing the DES algorithm is secured in a single
chip FPGA by loading the configuration data into the chip during the initialization cycle.
Once the key is loaded, it is secured inside the chip [17].
In 1999, Yeong-Kang Lai provides a novel VLSI architecture for a variablelength key, 64-bit Blowfish block cipher. It performs thorough evaluation of initialized
sub-keys, basic sub-keys generating, establishing a six-stage pipelined data path, and
mapping of the algorithm onto the data path for the low power consumption to improve
the chip performance [18].

11

CHAPTER 2 LITERATURE SURVEY

In 2000, M.P. Leong described a bit-serial implementation of the International
Data Encryption Algorithm (IDEA) using a novel bit-serial architecture to perform
multiplication modulo 216 1 by having minimal amount of hardware [19]. R. G. Sixel
describes a high level language implementation of the DES and bit-slice architecture.
This implementation had two objectives: (i) testing the whole algorithm prior to a VHDL
description for future synthesis, and (ii) by making DES available for other applications
requiring a software implementation [20]. Teo Pock Chueng provides implementation of
pipelined DES using Altera CPLD. The architecture contains of three main parts, DES
module, pipeline module and control unit module. Four segments pipeline is used in this
architecture to burst the throughput of DES and Altera Hardware Description Language
(AHDL) is used to implement the pipelined DES design for better output [21]. Cameron
Patterson provides high performance DES encryption in Virtex FPGAs using Jbits. Jbits
provides a Java-based Application Programming Interface (API) for the run-time creation
and also for the modification of the configuration bit-stream. This allows dynamic circuit
specialization based on a specific key and mode and when combined with a speed
efficient layout, the result is a throughput of over 10 Gbits/s [22].
In 2001, Pui-Lam Siu provides a low power asynchronous DES that can be used
in contactless smart cards with some advantages like low power consumption and no
global clock [23]. N. Sklavos describes asynchronous low power VLSI implementation
of IDEA. This approach proved efficiently the lowest power consumption of the
asynchronous implementation compared to the existing synchronous [24]. Ahmet
Eskicioglu provides a paper on cryptography. It concludes that early classical ciphers
substitution and transposition operations form the building blocks for todays powerful
ciphers such as DES. Key agreement schemes allow communicating parties to establish a
shared cipher key [25]. Deng Liang describes an efficient and scalable VLSI
implementation of DES by using 1.2m CMOS technology to implement a testing chip
for testing the performance of the design [26].
In 2002, Yeong-Kang Lai represents the VLSI Architecture Design and
Implementation for TWOFISH Block Cipher. In this paper the security of the Twofish
Encryption algorithm was increased by using loop-folding technique with efficient
hardware mapping [27]. Touria ARICH provides Hardware implementations of the Data

12

CHAPTER 2 LITERATURE SURVEY

Encryption Standard in Electronic Code Book mode (ECB) using hardware description
language VHDL [28]. Chih-Chung Lu describes an Integrated Design of Advanced
Encryption Standard (AES) Encrypter and Decrypter. This method is used to make it a
very low-complexity architecture, especially in saving the hardware resource in
implementing the AES (Inv) Sub-Bytes module and (Inv) Mix columns module, etc [29].
In 2003, G. Catalini provides Modified Twofish Algorithm for increasing Security
and Efficiency in the Encryption of video signals. The proposed system was tested on H
263+ coded signals [30]. M. McLoone provides high-performance FPGA implementation
of DES using a novel method for implementing the key schedule based on Xilinx Virtex
technology. Utilizing the novel method, a 16-stage pipelined DES design is achieved,
which can run at an encryption rate of 3.87 Gbits/s [31].
In 2004, Bo Yang describes scan based side channel attack on dedicated hardware
implementations of Data Encryption Standard. Scan chains can be used as a side channel
to recover secret keys from a hardware implementation of the Data Encryption Standard
[32]. Liakot Ali describes the implementation of triple data encryption algorithm and
VHDL [33]. Tariq Jamil provides the Rijndael algorithm: A brief introduction to the new
encryption standard. In overall performance, based on speed of encryption/decryption
process and key set-up time, the Rijndael algorithm has attained top scores in tests
conducted by NIST [34].
In 2005, Aamer Nadeem provides a performance comparison of data encryption
algorithms in which various algorithms were compared and it was found that Blowfish
algorithm is the best algorithm in view of processing time and security [35]. A. Ammar
introduced random data encryption algorithm in pseudo-randomized cipher keys were
used for greater security and higher throughput [36]. Jingmei Liu provides an AES S-box
to increase complexity and cryptographic analysis. An improved AES S-box is presented
to improve the complexity of AES S-box algebraic expression with terms increasing from
9 to 255 and algebraic degree invariable. The improved AES S-box also has better
properties of Boolean functions in SAC and balance, and is capable of attacking against
differential cryptanalysis with high reliable security [37].
In 2006, Chih-Hsu Yen described simple error detection methods for hardware
implementation of AES by using a n 1, n CRC where n can be 4,8,16 [38]. Alireza

13

CHAPTER 2 LITERATURE SURVEY

Hodjat describes Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES
Processors. This paper describes different pipelined implementations of the AES
algorithm as well as the design decisions and the area optimizations that lead to a low
area and high throughput AES encryption processor are presented. Moreover, by
pipelining the composite field implementation of the byte substitution phase of the AES
algorithm (inner-round pipelining), the area consumption is reduced up to 35 percent
[39].
In 2007, A.Chandra Sekhar provides data encryption technique using Random
number generator using the recurrence matrices and a quadruple vector. It provides data
encryption at two levels and hence security against crypto analysis is achieved at
relatively low computational overhead using the mod function [40]. M.R.M. Rizk
described an optimized area and optimized speed hardware implementations of AES on
FPGA, the code was written in VHDL and synthesized and verified using Xilinx ISE 7.1
and simulated using Modelsim [41].
In 2008, Jing Wang provides improved DES algorithm based on irrational
numbers. An improved scheme based on irrational numbers that enhances the
randomness of sub-Key is proposed. The permutation is controlled by irrational number,
i.e., considered as false chaos [42]. Md. Nazrul Islam describes the effect of security
increment to symmetric data encryption through AES methodology. A new algorithm
was proposed that was more securing than Rijndael algorithm but with less efficiency
[43]. The diffusive property of three encryption algorithms Rijndael, Twofish, and
Safer+ is compared by using simple test vectors. It was conducted by Sapiee Haji Jamel
and Mustafa Mat Deris [44].
The performance evaluation approach for a model was proposed in 2009 by
Hung-Min Sun [45]. It provides the information about the Security of an Efficient TimeBound Hierarchical Key Management Scheme. Tingyuan Nie describes a study of DES
and Blowfish Encryption Algorithm. In this paper the function run time of both
algorithms was compard [46]. Ashwini M. Deshpande describes FPGA Implementation
of AES Encryption and Decryption by using VHDL language and ModelSim SE PLUS
5.7g software for Simulation. Encryption and decryption routines are fully functional at
50 and 100 MHz [47].

14

CHAPTER 2 LITERATURE SURVEY

Many approaches for encryption have been studied in this chapter. The ideas of different
authors have been explained. The different methods for reducing the processing time and
for enhancing the security have also been explained. The need of Cryptography and the
benefits of using it have been explained. As a result, the processing time of DES
algorithm is very large. In order to reduce it, many techniques can be used such as,
addition, subtraction, or any other logical implementation.

15

CHAPTER

3
DES ALGORITHM
Data Encryption Standard (DES) is a cryptographic standard that was proposed as
the algorithm for secure and secret items in 1970 and was adopted as an American federal
standard by National Bureau of Standards (NBS) in 1973. DES is a block cipher, which
means that during the encryption process, the plain-text is broken into fixed length blocks
and each block is encrypted at the same time. Basically it takes a 64 bit input plain text
and a key of 64-bits (only 56 bits are used for conversion purpose and rest bits are used
for parity checking) and produces a 64 bit cipher text by encryption and which can be
decrypted again to get the message using the same key.

Figure 3.1: DES Flow

CHAPTER 3 DES ALGORITHM

3.1 DES Core

Figure 3.2: DES Core [52]

Pin name

I/O

Function

CLK

Core clock signal

RESET

Core reset signal

CEN

Synchronous enable signal. When LOW the core

ignores all its inputs and all its outputs must be
ignored

START

When goes HIGH, a cryptographic operation is started

E/D

Encrypt 1 / Decrypt 0

MODE [1:0]

DES Mode
0 Single DES
1 Double DES
2 Triple DES

17

CHAPTER 3 DES ALGORITHM

READY

Output data ready and valid

K1 [1:64]

First Encryption Key

K2 [1:64]

Second Encryption Key (used only in Double or triple

mode)

K3 [1:64]

Third Encryption Key (used only in Triple mode)

D [1:64]

Input Plain or Cipher Text Data

Q [1:64]

Output Cipher or Plain Text Data

Table 3.1: Pin configuration of DES core [52]

3.2 DES Algorithm

The algorithm's overall structure is shown in fig 3.2 and the Fiestel diagram is
shown in fig 3.3. The algorithm employs three different types of operations:
Permutations, Rotations, and Substitutions. Between the initial and final transpositions,
the algorithm performs 16 iterations of a function. The general depiction of DES
encryption algorithm which consists of initial permutation of the 64 bit plain text and
then goes through 16 rounds, where each round consists permutation and substitution of
the text bit and the inputted key bit, and at last goes through a inverse initial permutation
to get the 64 bit cipher text. DES standard is used very rarely because of its less keyspace as the security of DES algorithm resides in the key-length. It is improved using
irrational numbers as irrational numbers provide high security during encryption by
controlling the permutation. The key-space can also be increased using this technique or
performing the DES operation three times can also increase it. DES standard can also be
made secure by loading the data configuration into single chip FPGA during the
initialization cycle.
Basically, FPGAs provide a flexible, reliable and efficient way of synthesizing the
complex logic in a regular structure consisting of predefined programmable blocks and
predefined programmable routing resources. Encryption process in case of DES requires
various operations and multiple iterations. It also includes sub-keys, which are the subset
18

CHAPTER 3 DES ALGORITHM

of 56 bits key used in initial round. The section describes the steps for encryption used in
DES. Utilizing the steps of DES, the model is proposed in which variable key length is
used to encrypt the data. Key generation mechanism used in the model, generates the sub
keys from the S-Boxes. Model also includes the recovery mechanisms in order to provide
strength to the keys.
Modern applications of DES cover a wide variety of applications, such as secure
internet (ssl), electronic financial transactions, remote access servers, cable modems,
secure video surveillance and encrypted data storage.

Figure 3.3: DES Algorithm [49]

19

CHAPTER 3 DES ALGORITHM

Figure 3.4: DES Fiestel Structure [51]

20

CHAPTER 3 DES ALGORITHM

3.3 Steps for Algorithm [54]

Step 1: Create 16 sub-keys, each of which is 48-bits long.
The 64-bit key is permuted according to Permuted Choice 1 table as shown in
table 3.2. The first bit of K+ will be the 57th bit of K and the 2nd bit of K+ will be the 49th
bit of K and so on. The last bit of K+ will be the 4th bit of K. Here it must be noted that K
(i.e., original key) is of 64 bits and K+ (i.e., permuted key) is of 56 bits.

PC-1: Permuted Choice 1

Bit

57

49

41

33

25

17

58

50

42

34

26

18

15

10

59

51

43

35

27

22

19

11

60

52

44

36

29

63

55

47

39

31

23

15

36

62

54

46

38

30

22

43

14

61

53

45

37

29

50

21

13

28

20

12

Table 3.2: Permuted Choice 1

Example: The original 64-bit key
K = 00010011 00110100 01010111 01111001 10011011 10111100 11011111 11100001
we get the 56-bit permuted key
K+ = 11110000 11001100 10101010 01110101 01010110 01100111 10001111
Next split this key into left and right halves, C0 and D0, each having 28 bits.
Example: From the permuted key K+, we get

21

CHAPTER 3 DES ALGORITHM

C0 = 11110000 11001100 10101010 0111
D0 = 0101 01010110 01100111 10001111
Now we can create sixteen blocks C n and. Dn , where n ranges from 1 to 16.
Each pair of blocks Cn and Dn is formed from the previous pair Cn-1 and Dn-1,
respectively, for n = 1, 2, ..., 16, using the sub-key rotation mechanism of "left shifts" of
the previous block.

Round
Number
Number of
bits to rotate

Sub-key Rotation Table

5
6
7
8
9
10

11

12

13

14

15

16

Table 3.3: Sub-key Rotation Table

This means, for example, C3 and D3 are obtained from C2 and D2, respectively, by
two left shifts, and C16 and D16 are obtained from C15 and D15, respectively, by one left
shift. In all cases, by a single left shift is meant a rotation of the bits one place to the left
Example: From original pair C0 and D0 we obtain:
C1 = 1110000110011001010101001111
D1 = 1010101011001100111100011110
C2 = 1100001100110010101010011111
D2 = 0101010110011001111000111101
C3 = 0000110011001010101001111111
D3 = 0101011001100111100011110101
C4 = 0011001100101010100111111100
D4 = 0101100110011110001111010101

22

CHAPTER 3 DES ALGORITHM

C5 = 1100110010101010011111110000
D5 = 0110011001111000111101010101
C6 = 0011001010101001111111000011
D6 = 1001100111100011110101010101
C7 = 1100101010100111111100001100
D7 = 0110011110001111010101010110
C8 = 0010101010011111110000110011
D8 = 1001111000111101010101011001
C9 = 0101010100111111100001100110
D9 = 0011110001111010101010110011
C10 = 0101010011111110000110011001
D10 = 1111000111101010101011001100
C11 = 0101001111111000011001100101
D11 = 1100011110101010101100110011
C12 = 0100111111100001100110010101
D12 = 0001111010101010110011001111
C13 = 0011111110000110011001010101
D13 = 0111101010101011001100111100
C14 = 1111111000011001100101010100
D14 = 1110101010101100110011110001
C15 = 1111100001100110010101010011
D15 = 1010101010110011001111000111
C16 = 1111000011001100101010100111
D16 = 0101010101100110011110001111
23

CHAPTER 3 DES ALGORITHM

Now we will obtain the keys Kn, for 1<=n<=16, by using the permuted choice 2
table to each of the concatenated pairs CnDn. Here the input to the table is of 56 bits, but
the output will be of only 48 bits.
PC-2: Permuted Choice 2
Bit

14

17

11

24

28

15

21

10

13

23

19

12

26

19

16

27

20

13

25

41

52

31

37

47

55

31

30

40

51

45

33

48

37

44

49

39

56

34

53

43

46

42

50

36

29

32

Table 3.4: Permuted Choice 2

Therefore, the first bit of Kn is the 14th bit of CnDn, the second bit the 17th, and so
on, ending with the 48th bit of Kn being the 32th bit of CnDn.
Example: For the first key we have C1D1 = 11100001 10011001 01010100 11111010
10101100 11001111 00011110
which, after we apply the permutation PC-2, becomes
K1 = 000110 110000 001011 101111 111111 000111 000001 110010
For the other keys we have
K2 = 011110 011010 111011 011001 110110 111100 100111 100101
K3 = 010101 011111 110010 001010 010000 101100 111110 011001
K4 = 011100 101010 110111 010110 110110 110011 010100 011101
K5 = 011111 001110 110000 000111 111010 110101 001110 101000
24

CHAPTER 3 DES ALGORITHM

K6 = 011000 111010 010100 111110 010100 000111 101100 101111
K7 = 111011 001000 010010 110111 111101 100001 100010 111100
K8 = 111101 111000 101000 111010 110000 010011 101111 111011
K9 = 111000 001101 101111 101011 111011 011110 011110 000001
K10 = 101100 011111 001101 000111 101110 100100 011001 001111
K11 = 001000 010101 111111 010011 110111 101101 001110 000110
K12 = 011101 010111 000111 110101 100101 000110 011111 101001
K13 = 100101 111100 010111 010001 111110 101011 101001 000001
K14 = 010111 110100 001110 110111 111100 101110 011100 111010
K15 = 101111 111001 000110 001101 001111 010011 111100 001010
K16 = 110010 110011 110110 001011 000011 100001 011111 110101
Step 2: Encode each 64-bit block of data.
In this step, we have to obtain the initial permutation of data input D. This
rearranges the bits according to the table as shown in table 3.5. The 58th bit of D
becomes the first bit of IP. The 50th bit of D becomes the second bit of IP. The 7th bit of
D is the last bit of IP.
IP: Initial Permutation
Bit

58

50

42

34

26

18

10

60

52

44

36

28

20

12

17

62

54

46

38

30

22

14

25

64

56

48

40

32

24

16

33

57

49

41

33

25

17

41

59

51

43

35

27

19

11

49

61

53

45

37

29

21

13

57

63

55

47

39

31

23

15

Table 3.5: Initial Permutation

25

CHAPTER 3 DES ALGORITHM

Example: Applying the initial permutation to the block of text M, given previously, we
get
D = 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110
1111
IP = 1100 1100 0000 0000 1100 1100 1111 1111 1111 0000 1010 1010 1111 0000 1010
1010
Here the 58th bit of D is "1", which becomes the first bit of IP. The 50th bit of D
is "1", which becomes the second bit of IP. The 7th bit of D is "0", which becomes the
last bit of IP.
Next divide the permuted block IP into a left half L0 of 32 bits, and a right half R0
of 32 bits.
Example: From IP, we get L0 and R0
L0 = 1100 1100 0000 0000 1100 1100 1111 1111
R0 = 1111 0000 1010 1010 1111 0000 1010 1010
We now proceed through 16 rounds, for 1<=n<=16, using a function f which
operates on two blocks--a data block of 32 bits and a key Kn of 48 bits--to produce a
block of 32 bits. Let + denote XOR addition, (bit-by-bit addition modulo 2). Then for n
going from 1 to 16 we calculate
Ln = Rn-1
Rn = Ln-1 + f(Rn-1,Kn)
This results in a final block, for n = 16, of L16R16, i.e., in each round, we take the
right 32 bits of the previous result and make them the left 32 bits of the current step. For
the right 32 bits in the current step, we XOR the left 32 bits of the previous step with the
calculation f .
Example: For n = 1, we have

26

CHAPTER 3 DES ALGORITHM

K1 = 000110 110000 001011 101111 111111 000111 000001 110010
L1 = R0 = 1111 0000 1010 1010 1111 0000 1010 1010
R1 = L0 + f(R0,K1)
Procedure to compute f Function:
To calculate f, we first expand each block Rn-1 from 32 bits to 48 bits. This is done
by using a E bit selection table (shown in table 3.6) that repeats some of the bits in Rn-1 .
Thus E(Rn-1) has a 32 bit input block, and a 48 bit output block. Let E be such that the 48
bits of its output, written as 8 blocks of 6 bits each.
E-Bit Selection Table
Bit

32

13

10

11

12

13

19

12

13

14

15

16

17

25

16

17

18

19

20

21

31

20

21

22

23

24

25

37

24

25

26

27

28

29

43

28

29

30

31

32

33

Table 3.6: E-bit Selection Table

Thus the first three bits of E(Rn-1) are the bits in positions 32, 1 and 2 of Rn-1 while
the last 2 bits of E (Rn-1) are the bits in positions 32 and 1.
Example: We calculate E(R0) from R0 as follows:
R0 = 1111 0000 1010 1010 1111 0000 1010 1010
E (R0) = 011110 100001 010101 010101 011110 100001 010101 010101

27

CHAPTER 3 DES ALGORITHM

Next in the f calculation, we XOR the output E(Rn-1) with the key Kn:
Kn + E (Rn-1).
Example: For K1 , E(R0), we have
K1 = 000110 110000 001011 101111 111111 000111 000001 110010
E (R0) = 011110 100001 010101 010101 011110 100001 010101 010101
K1+E(R0) = 011000 010001 011110 111010 100001 100110 010100 100111.
We have not yet finished calculating the function f . To this point we have
expanded Rn-1 from 32 bits to 48 bits, using the selection table, and XORed the result
with the key Kn . We now have 48 bits, or eight groups of six bits. We now do something
strange with each group of six bits: we use them as addresses in tables called "S boxes".
Each group of six bits will give us an address in a different S box. Located at that address
will be a 4 bit number. This 4 bit number will replace the original 6 bits. The net result is
that the eight groups of 6 bits are transformed into eight groups of 4 bits (the 4-bit outputs
from the S boxes) for 32 bits total.
Write the previous result, which is 48 bits, in the form:
Kn + E (Rn-1) =B1B2B3B4B5B6B7B8,
where each Bi is a group of six bits. We now calculate
S1(B1)S2(B2)S3(B3)S4(B4)S5(B5)S6(B6)S7(B7)S8(B8)
where Si(Bi) referres to the output of the i-th S box and B is a block of 6 bits.
To repeat, each of the functions S1, S2,..., S8, takes a 6-bit block as input and
yields a 4-bit block as output. The table to determine S1 is shown and explained below:

28

CHAPTER 3 DES ALGORITHM

S-Box 1: Substitution Box 1
Row/
0
Column
14
0

10

11

12

13

14

15

13

15

11

10

12

15

14

13

10

12

11

14

13

11

15

12

10

15

12

11

14

10

13

Table 3.7: S-box 1

The first and last bits of B represent in base 2 a number in the decimal range 0 to
3 (or binary 00 to 11). Let that number be i. The middle 4 bits of B represent in base 2 a
number in the decimal range 0 to 15 (binary 0000 to 1111). Let that number be j. Look up
in the table the number in the i-th row and j-th column. It is a number in the range 0 to 15
and is uniquely represented by a 4 bit block. That block is the output S1(B) of S1 for the
input B. For example, for input block B = 011011 the first bit is "0" and the last bit "1"
giving 01 as the row. This is row 1. The middle four bits are "1101". This is the binary
equivalent of decimal 13, so the column is column number 13. In row 1, column 13
appears 5. This determines the output; 5 is binary 0101, so that the output is 0101. Hence
S1 (011011) = 0101. The tables defining the functions S1,...,S8 are the following:
S-Box 1: Substitution Box 1
Row/
0
Column
14
0

10

11

12

13

14

15

13

15

11

10

12

15

14

13

10

12

11

14

13

11

15

12

10

15

12

11

14

10

13

S-Box 2: Substitution Box 2

Row/
0
Column
15
0

10

11

12

13

14

15

14

11

13

12

10

29

CHAPTER 3 DES ALGORITHM

1

13

15

14

12

10

11

14

11

10

13

12

15

13

10

15

11

12

14

S-Box 3: Substitution Box 3

Row/
0
Column
10
0

10

11

12

13

14

15

14

15

13

12

11

13

10

14

12

11

15

13

15

11

12

10

14

10

13

15

14

11

12

S-Box 4: Substitution Box 4

Row/
0
Column
7
0

10

11

12

13

14

15

13

14

10

11

12

15

13

11

15

12

10

14

10

12

11

13

15

14

15

10

13

11

12

14

S-Box 5: Substitution Box 5

Row/
0
Column
2
0

10

11

12

13

14

15

12

10

11

15

13

14

14

11

12

13

15

10

11

10

13

15

12

14

11

12

14

13

15

10

S-Box 6: Substitution Box 6

Row/
0
Column
12
0

10

11

12

13

14

15

10

15

13

14

11

10

15

12

13

14

11

14

115 5

12

10

13

11

30

CHAPTER 3 DES ALGORITHM

3

12

15

10

11

14

13

S-Box 7: Substitution Box 7

Row/
0
Column
4
0

10

11

12

13

14

15

11

14

15

13

12

10

10

14

12

15

13

11

113 12

14

10

15

11

13

10

15

14

12

S-Box 8: Substitution Box 8

Row/
0
Column
13
0

10

11

12

13

14

15

15

11

10

14

12

15

13

10

12

11

14

11

12

14

10

13

15

14

10

13

15

12

11

Table 3.8: S-boxes

Example: For the first round, we obtain as the output of the eight S boxes:
K1 + E (R0) = 011000 010001 011110 111010 100001 100110 010100 100111.
S1(B1)S2(B2)S3(B3)S4(B4)S5(B5)S6(B6)S7(B7)S8(B8) = 0101 1100 1000 0010 1011 0101
1001 0111
The final stage in the calculation of f is to do a permutation P of the S-box output
to obtain the final value of f:
f = P (S1 (B1) S2 (B2)...S8 (B8))
The permutation P is defined in the following table. P yields a 32-bit output from
a 32-bit input by permuting the bits of the input block.

31

CHAPTER 3 DES ALGORITHM

P Permutation
Bit
1

0
16

1
7

2
20

3
21

29
1

12
15

28
23

17
26

18

31

10

2
32

8
27

24
3

14
9

19

13

30

22

11

25

9
13
17
21
25
29

Table 3.9: P-Permutation Table

Example: From the output of the eight S boxes:
S1(B1)S2(B2)S3(B3)S4(B4)S5(B5)S6(B6)S7(B7)S8(B8) = 0101 1100 1000 0010 1011 0101
1001 0111
we get
f = 0010 0011 0100 1010 1010 1001 1011 1011
R1 = L0 + f(R0 , K1 )
= 1100 1100 0000 0000 1100 1100 1111 1111
+ 0010 0011 0100 1010 1010 1001 1011 1011
= 1110 1111 0100 1010 0110 0101 0100 0100
In the next round, we will have L2 = R1, which is the block we just calculated, and
then we must calculate R2 =L1 + f(R1, K2), and so on for 16 rounds. At the end of the
sixteenth round we have the blocks L16 and R16. We then reverse the order of the two
blocks into the 64-bit block
R16L16
and apply a final permutation IP-1 as defined by the following table:
32

CHAPTER 3 DES ALGORITHM

IP^(-1): Inverse Initial Permutation

Bit

40

48

16

56

24

64

32

39

47

15

55

23

63

31

17

38

46

14

54

22

62

30

25

37

45

13

53

21

61

29

33

36

44

12

52

20

60

28

41

35

43

11

51

19

59

27

49

34

42

10

50

18

58

26

57

33

41

49

17

57

25

Table 3.10: Inverse Initial Permutation

That is, the output of the algorithm has bit 40 of the preoutput block as its first bit,
bit 8 as its second bit, and so on, until bit 25 of the preoutput block is the last bit of the
output.
Example: If we process all 16 blocks using the method defined previously, we get, on the
16th round,
L16 = 0100 0011 0100 0010 0011 0010 0011 0100
R16 = 0000 1010 0100 1100 1101 1001 1001 0101
We reverse the order of these two blocks and apply the final permutation to
R16L16 = 00001010 01001100 11011001 10010101 01000011 01000010 00110010
00110100
IP-1 = 10000101 11101000 00010011 01010100 00001111 00001010 10110100
00000101

33

CHAPTER 3 DES ALGORITHM

which in hexadecimal format is
69BE85B7C35D19EE.
This is the encrypted form of D = 0123456789ABCDEF
Decryption is simply the inverse of encryption, following the same steps as above,
but reversing the order in which the sub-keys are applied.

34

CHAPTER

4
TWOFISH ALGORITHM
Twofish is a 128-bit block cipher proposed by Schneier et al. It can also work
with 192- or 256-bit key lengths. A Feistel network structure, which was made
specifically for DES algorithm and was a successful one, can also be used for Twofish
algorithm having 16 rounds. A Feistel network is a general method of transforming any
function (usually called the F function) into a permutation. It was invented by Horst
Feistel. In a Feistel network, the round function consists of taking one part of the data
being encrypted, feeding it into some key dependent function F, and then XORing the
result into another part of the block. Two rounds of Feistel network are known to be as
one cycle, therefore, Twofish algorithm is an 8-cycle algorithm having 16 rounds. The
structure of the Twofish algorithm is shown in figure 4.1. The only difference between
the two Feistel network structures is the two fixed rotations by one bit, performed
together with the XOR operations on outputs of the F-function.
Twofish exhibits fast and versatile performance across most platforms; it performs well
both in hardware and in memory-constrained environments. Twofish can be optimized
for speed, key setup, memory, code size in software, or space in hardware. Encrypt data
in less than 500 clock cycles per block on an Intel Pentium, Pentium Pro, and Pentium II,
for a fully optimized version of the algorithm.
The Twofish algorithm consists of two types of operations (as shown in figure 4.1)
Byte-oriented: It includes the whitening operation and F-function.
Non-byte-oriented: It includes two sub-key additions modular 2 32 comprising of 1-bit
rotates, addition with sub-keys, and PHT (pseudo-Hadamard transform).

CHAPTER 4 TWOFISH ALGORITHM

Figure 4.1: Feistel Structure for Twofish Algorithm [55]

4.1 Whitening Operation [55, 56]

It includes the XORing of input and output data with eight sub-keys (K0 K7).
Thus this operation is performed only at the input level, i.e., before 1st round, hence
called input whitening and at the output level, i.e., after 16th round, hence called output
whitening (as mentioned in figure 4.1). The whitening operation is actually used to
increases the difficulty for the attackers, to search for key, by hiding the inputs to 1 st and
last round. The sub-keys (K0 K7) used in this operation are also calculated in the same
manner as the other round sub-keys, and are not be used in other operations.

4.2 F function [55, 56]

It consists of five operations:

36

CHAPTER 4 TWOFISH ALGORITHM

1. Fixed left rotation by 8 bits
2. Key-dependent S-boxes
3. Maximum Distance Separable (MDS) matrices
4. Pseudo-Hadamard Transform (PHT)
5. Two sub-key additions modular 2 32

4.3 S-boxes [55, 56]

An S-box is a table-driven substitution operation used in many algorithms. It can
vary in both input and output size and can be made randomly or algorithmically. There
are four kinds of S-boxes used in Twofish algorithm. Four different S-boxes together
with the MDS matrix form an h-function. This h-function appears two times in the
algorithm, which causes significant redundancy. In Twofish, each S-box consists of three
8-by-8-bit fixed permutations chosen from a set of two possible permutations, q0 and q1.
The structure of all S-boxes is shown in figure 4.2.

Figure 4.2: Structure for S-boxes

The XOR operations are performed with sub-keys S0, S1 between the three
permutations. These sub-keys are computed only once for a particular global key, and
stay fixed during the entire encryption and decryption process.

37

CHAPTER 4 TWOFISH ALGORITHM

Each q-permutation represents a fixed function by having a regular structure as
shown in figure 4.3. The main components of the q-permutations are 4-by-4-bit fixed Sboxes t0...t3. Both permutations q0 and q1 have the same internal structure, and differ
only in the contents of the S-boxes t0...t3.

Figure 4.3: q-permutation Structure

4.4 MDS Matrices [55, 56]

Twofish algorithm uses a single 4-by-4 Maximum Distance Separable (MDS)
matrix. The transformation performed by this matrix is described by the formula:

38

CHAPTER 4 TWOFISH ALGORITHM

z0

z1
z =
2
z
3

01

5B
EF

EF

EF

5B

EF
5B

EF
01

01

EF

5B

01
EF

5 B

y0

y1
y
2
y
3

where y3...y0 are consecutive bytes of the input 32-bit word (y3 is the most significant
byte), and z3...z0 form the output word.
This matrix multiplies a 32-bit input value by 8-bit constants, with all
multiplications performed (byte by byte) in the Galois field GF (28). The primitive
polynomial is x8 + x6 + x5 + x3 + 1. Only three different multiplications are used
effectively in the MDS matrix, namely multiplication
- by 5B16 = 0101 10112 (represented in GF(28) by a polynomial x6 + x4 + x3 + x + 1),
- by EF16 = 1110 11112 (x7 + x6 + x5 + x3 + x2 + x + 1), and
- by 0116 = 0000 00012 (equivalent element in GF(28) is just 1) - obviously the result is
equal to the input value.
MDS matrices are useful building blocks for ciphers because they guarantee a
certain degree of diffusion. If one of the input elements is changed, all the output
elements must change. If two input elements are changed, all but one of the output
elements must change, etc.

4.5 Pseudo-Hadamard Transforms [55, 56]

A pseudo-Hadamard transform (PHT) is a simple mixing operation that is very
efficient in software. Given two inputs, a and b, the 32-bit PHT is defined as:
a = a + b mod 232
b = a + 2b mod 232
Twofish uses a 32-bit PHT to mix the outputs from its two parallel 32-bit hfunctions.

4.6 Steps for Twofish Algorithm [55, 56]

Step 1: The plaintext is split into four 32-bit words, i.e, P0 - P3 .

39

CHAPTER 4 TWOFISH ALGORITHM

Step 2: In the input whitening step, these are XORed with four key words.
R0,i = Pi Ki i = 0,...,3
This is followed by 16 rounds.
Step 3: In each round, the two words on the left are used as input to the h-functions; one
of them is rotated by 8 bits first. The h-function consists of four byte-wide key-dependent
S-boxes, followed by a linear mixing step based on an MDS matrix. The third word is
XORed

with the first output of F and then rotated right by one bit. The fourth word is

rotated left by one bit and then XORed with the second output word of F. Finally, the two
halves are exchanged. Thus,

, Fr ,1

R r 1, 0

R r 1,1

ROL R r ,3 ,1 Fr ,1

Rr 1, 2

Rr ,0

Rr 1,3

Rr ,1

r ,0

F R r , 0 , R r ,1 , r

ROR R r , 2 Fr , 0 ,1

Step 4: The results of the two h-functions are combined using a Pseudo-Hadamard
Transform (PHT), and two round key words are added.
Step 5: These two results are then XORed into the words on the right (one of which is
rotated left by one bit first, the other is rotated right by one bit afterwards).
Step 6: The left and right halves are then swapped for the next round.
Step 7: After all the rounds, the swap of the last round is reversed, and the four words are
XORed

with four more key words to produce the cipher-text, which is known as output

whitening.

40

CHAPTER

5
FPGA OVERVIEW
The Xilinx Spartan 3E (XC3S500) FPGA kit is used for implementation of
encryption algorithms [57]. The Xilinx ISE 9.2i tool is used for the design. Some
specifications of Spartan 3E kit are as following:
Upto 232 user I/O pins
Over 10,000 logic cells
2 line, 16 character LCD screen
PS/2 mouse or keyboard port
VGA display port
Two 9 pin RS 232 ports (DTE/DCE)
50 MHz clock oscillator
Chipscope SoftTouch debugging port
Eight discrete LEDs
Four slide switches
Four push-button switches
Speed Grade -4
FG320 package

5.1 Introduction to FPGA

A Field Programmable Gate Array (FPGA) is a reprogrammable logic device used as
a reprogrammable alternative to ASIC chip devices. FPGAs can be used for specific

CHAPTER 5 FPGA OVERVIEW

operational behavior, or general purpose CPU functionality depending on the complexity of
the device. FPGA applications include DSP applications, imaging, speech recognition,
cryptography, hardware emulation and for many other application specific uses. Many
FPGAs are implementing shared general purpose CPUs on chip for shorter latency times
between operations resulting in higher performance of the overall system.

FPGA is an integrated circuit (IC) that includes a two-dimensional array of

Configurable Logic Blocks (CLBs)
Configurable I/O Blocks (IOBs)

Figure 5.1: FPGA Architecture

FPGAs can be classified as:

One time programmable

Fuses (destroy internal links with current)

Anti-fuses (grow internal links)

PROM

Reprogrammable

42

CHAPTER 5 FPGA OVERVIEW

EPROM

EEPROM

Flash

SRAM - volatile

5.2 Design Flow

Figure 5.2: FPGA Design Flow

43

CHAPTER 5 FPGA OVERVIEW

5.2.1 Design Entity
The HDL languages Verilog or VHDL are used to design the architecture of the
system. A VHDL design can be processed by its entity and architecture declarations. The
architecture declaration can be of behavioral, dataflow, or structural modeling style.
5.2.2 Behavioral Simulation
By using behavioral simulation we can verify the functionality of the code
designed for our system. Various modifications can be done in case of getting errors in
the code.
5.2.3 Synthesis
The synthesis process includes the compilation of the sub-modules in the main
module and the analysis of the hierarchy of the design. It checks the syntax of the design
gives the output in the netlist format which is saved to an Native Generic Circuit (NGC).
5.2.4 Design Implementation
It includes the following three processes:
1. Translation
2. Mapping
3. Place & Route
Translation process compiles all the input netlists and constraints to a logic design file,
namely Native Generic Database (NGD) file having extension .ngd. In this process, the
ports are assigned to physical elements such as pins, switches, buttons, etc. This
information is stored in the UCF (User Constraint file) file.
Mapping process divides the whole circuit into sub-blocks so that they can fit into FPGA
blocks. It includes the mapping of input NGD file logic into targeted FPGA elements
such as CLBs and IOBs
Place and Route process places the sub-blocks from map process into the logic blocks
according to the constraints and connects the logic blocks. This can be done by using
Place And Route (PAR) program. This program takes the mapped NCD file as input and
gives the completely routed NCD file as output.
5.2.5 Functional Simulation
This simulation process is used to verify the functionality of the design after the
design implementation

44

CHAPTER 5 FPGA OVERVIEW

5.2.6 Static Timing Analysis
The static timing analysis can be done by using following three types:
1. Post-fit Static Timing Analysis
2. Post-Map Static Timing Analysis
3. Post-Place and Route Static Timing Analysis
5.2.7 Device Programming
At last the FPGA device is to be programmed by configuring the device. In this process
the .bit file is to be assigned to the device which is to be programmed and bye-passing the
other devices.

Figure 5.3: FPGA Spartan 3E Kit

45

CHAPTER

6
EXPERIMENTAL RESULTS
6.1 Simulation Results of DES Algorithm

Figure 6.1: DES Block

CHAPTER 6 EXPERIMENTAL RESULTS

Figure 6.1 shows the block of DES algorithm showing input and output pins. In this we
give 64-bit data and 64-bit key, so that it gives us 64-bit encrypted data after processing
through the whole encryption process including 16 rounds. In this, function select is to be
1 for the encryption process. The simulation results are shown in figure 6.2.

Figure 6.2: Simulation result of DES Encryption by Model Sim

Description:key_in

64 bit (11111111111111110000000000000000
10101010101010100101010101010101)

function_select

1 for encryption
0 for decryption

data_in

64 bit (00000001001000110100010101100111
10001001101010111100110111101111)

lddata

data_out

64 bit (01101001101111101000010110110110
11111000001101011101000110011110)

47

CHAPTER 6 EXPERIMENTAL RESULTS

reset

clock

core_busy

6.2 FPGA Implementation of DES Algorithm

Figure 6.3: Programming Completion of DES Encryption

Figure 6.3 shows the successful completion of programming of device by showing a
message Program Succeeded. The final output, i.e., the 64-bit encrypted data in the
form of cipher-text is as shown in figure 6.4. The final output is shown on LCD of FPGA
Spartan 3E kit.

48

CHAPTER 6 EXPERIMENTAL RESULTS

Figure 6.4: Output Display of DES Encrypted Data

6.3 Simulation Results of TWOFISH Algorithm

Figure 6.5: Twofish Encryption Block

49

CHAPTER 6 EXPERIMENTAL RESULTS

Figure 6.5 shows the encryption block of Twofish algorithm showing input and output
pins. In this we give 128-bit data in four parts each of 32-bit and 128-bit key, so that it
gives us 128-bit encrypted data after processing through the whole encryption process
including 16 rounds. The simulation results are shown in figure 6.6.

Figure 6.6: Simulation result of Twofish Encryption by Model Sim

Description:in1_ter128

32 bit (11111111000000001111111100000000)

in2_ter128

32 bit (10101010101010101010101010101010)

in3_ter128

32 bit (01010101010101010101010101010101)

in4_ter128

32 bit (11001100110011001100110011001100)

in_Sfirst_ter128

32 bit (10011001100110011001100110011001)

in_Ssecond_ter128

32 bit (11110000000011111111000000001111)

in_key_up_ter128

32 bit (10011111100111111001111110011111)

in_key_down_ter128 :

32 bit (01100110011001100110011001100110)

out1_ter128

32 bit (10011011001110010101101010110000)

out2_ter128

32 bit (11111001110111000011000010110010)

out3_ter128

32 bit (11111111000000001111111100000000)
50

CHAPTER 6 EXPERIMENTAL RESULTS

out4_ter128

32 bit (10101010101010101010101010101010)

to_left_shift

32 bit (00110110011100101011010101100001)

from_right_shift

32 bit (10011001100110011001100110011001)

to_xor_with3

32 bit (01100011001001111100000000110100)

to _xor_with4

32 bit (01100000010001011010100100101011)

6.4 Synthesis Report of LCD Programming

---- Source Parameters
Input File Name

: "lcd_des.prj"

Input Format

: mixed

Ignore Synthesis Constraint File

: No

---- Target Parameters

Output File Name

: "lcd_des"

Output Format

: NGC

Target Device

: xc3s500e-4-fg320

---- Source Options

Top Module Name

: lcd_des

Automatic FSM Extraction

: Yes

FSM Encoding Algorithm

: Auto

Safe Implementation

: No

FSM Style

: lut

RAM Extraction

: Yes

RAM Style

: Auto

ROM Extraction

: Yes

Mux Style

: Auto

Decoder Extraction

: Yes

Priority Encoder Extraction

: Yes

Shift Register Extraction

: Yes

Logical Shifter Extraction

: Yes
51

CHAPTER 6 EXPERIMENTAL RESULTS

XOR Collapsing

: Yes

ROM Style

: Auto

Mux Extraction

: Yes

Resource Sharing

: Yes

Asynchronous To Synchronous

: NO

Multiplier Style

: auto

Automatic Register Balancing

: No

---- Target Options

Add IO Buffers

: Yes

Global Maximum Fanout

: 500

Add Generic Clock Buffer(BUFG)

: 24

Register Duplication

: Yes

Slice Packing

: Yes

Optimize Instantiated Primitives

: No

Use Clock Enable

: Yes

Use Synchronous Set

: Yes

Use Synchronous Reset

: Yes

Pack IO Registers into IOBs

: auto

Equivalent register Removal

: Yes

---- General Options

Optimization Goal

: Speed

Optimization Effort

:1

Library Search Order

: lcd_des.lso

Keep Hierarchy

: No

RTL Output

: Yes

Global Optimization

: All Clock Nets

Read Cores

: YES

Write Timing Constraints

: No

Cross Clock Analysis

: No

52

CHAPTER 6 EXPERIMENTAL RESULTS

Hierarchy Separator

:/

Bus Delimiter

: <>

Case Specifier

: Maintain

Slice Utilization Ratio

: 100

BRAM Utilization Ratio

: 100

Verilog 2001

: Yes

Auto BRAM Packing

: No

Slice Utilization Ratio Delta

:5

Macro Statistics
64x6-bit ROM

:1

26-bit up counter

:1

1-bit register

:8

6-bit register

:1

7-bit register

:1

1-bit xor2

:1

# IOs

:9

# BELS

: 104

GND

:1

INV

:2

LUT1

: 25

LUT2

:1

LUT4

: 13

MUXCY

: 25

MUXF5

:7

MUXF6

:4

VCC

:1

XORCY

: 25

# FlipFlops/Latches

: 34

FD

: 33

FDR

:1

53

CHAPTER 6 EXPERIMENTAL RESULTS

# Shift Registers

:7

SRL16

:7

# Clock Buffers

:1

BUFGP

:1

# IO Buffers

:8

:8

OBUF

Number of Slices

: 26 out of 4656

0%

Number of Slice Flip Flops

: 34 out of 9312

0%

Number of 4 input LUTs

: 48 out of 9312

0%

Number used as logic

: 41

Number used as Shift registers

:7

Number of IOs

:9

Number of bonded IOBs

: 9 out of 232

3%

Number of GCLKs

: 1 out of

4%

24

NET clk PERIOD = 20 nS HIGH 10 nS

Clock period

: 4.823ns (frequency: 207.340MHz)

Total number of paths / destination ports: 425 / 42

54

6.5 Design Statistics of DES Algorithm

Particulars

Des_cipher_top

Key_scheduling

Des_top

Block_top

Add_key

E_expansion_function

IOs
BELS
GND
INV
LUT2
LUT2_D
LUT3
LUT3_D
LUT3_L
LUT4
LUT4_D
LUT4_L
MUXF5
MUXF6
VCC
FlipFlops/Latches
FDR
FDE
FDRS
I/O Buffers
IBUF
OBUF
BUFGP
(Clock)

198
18
1
1
2
2
10
1
1
11

119
415
1
1
2
318
11
70
12
1
57

187
660
1
1
21
27
37
2
1
347
4
65
121
32
1
144

176
368
1
48
190
96
32
1
-

144
48
48
-

80
-

10
1
68
2
66
1

1
56
110
61
49
1

11
132
1
186
116
70
1

176
112
64
-

144
96
48
-

80
32
48
-

55

Particulars
IOs
BELS
GND
INV
LUT2
LUT2_D
LUT3
LUT3_D
LUT3_L
LUT4
LUT4_D
LUT4_L
MUXF5
MUXF6
VCC
FlipFlops/Latches
FDR
FDE
FDRS
I/O Buffers
IBUF
OBUF
BUFGP (Clock)

S_box
80
257
1
158
65
32
1
-

S1_box
10
33
1
19
8
4
1
-

S2_BOX
10
33
1
19
8
4
1
-

S3_box
10
34
1
20
8
4
1
-

S4_box
10
34
1
20
8
4
1
-

S5_box
10
34
1
20
8
4
1
-

S6_box
34
34
1
20
8
4
1
-

S7_box
10
34
1
20
8
4
1
-

S8_box
10
35
1
20
-9
4
1
-

80
48
32
-

10
6
4
-

10
6
4
-

10
6
4
-

10
6
4
-

10
6
4
-

10
6
4
-

10
6
4
-

10
6
4
-

56

6.6 Device Utilization Summary of DES Algorithm

Particulars

Des_cipher_top

Key_scheduling

Des_top

Block_top

Add_key

E_expansion_function

No. of Slices
(4656)

188

275

142

28

No. of Slice
F/Fs (9312)

11

144

No. of 4-i/p
LUTs (9312)

15

332

505

238

48

Bonded IOBs
(232)

69

111

187

176

144

80

GCLKs (24)

57

Particulars

S_box

S1_box

S2_BOX

S3_box

S4_box

S5_box

S6_box

S7_box

S8_box

No. of Slices
(4656)

13

13

13

13

13

13

13

13

13

No. of Slice
F/Fs (9312)

No. of 4-i/p
LUTs (9312)

20

20

20

20

20

20

20

20

20

Bonded IOBs
(232)

10

10

10

10

10

10

10

10

10

GCLKs (24)

58

6.7 Macro Statistics of DES Algorithm

Particulars

Des_cipher_top

Key_scheduling

Des_top

Block_top

Add_key

E_expansion_function

FSMs

4-bit adder

4-bit add/sub

Registers/FlipFlops

135

57

141

48-bit 16-1 MUX

32-bit XOR2

6-bit XOR2

64*4-bit ROMs

59

Particulars

S_box

S1_box

S2_BOX

S3_box

S4_box

S5_box

S6_box

S7_box

S8_box

FSMs

4-bit adder

4-bit add/sub

Registers/FlipFlops

48-bit 16-1
MUX

32-bit XOR2

6-bit XOR2

64*4-bit
ROMs

60

6.8 Timing Summary of DES Algorithm

Particulars

Des_cipher_top

Key_scheduling

Des_top

Block_top

Add_key

E_expansion_function

Timing Constraint (1)

Source
Destination

round_counter_0 (FF)
des_out_ready (FF)

reset (PAD)
k3_47 (FF)

r_in_internal_o (FF)
r_in_internal_20 (FF)

r_in (PAD)
r_out (PAD)

x_in (PAD)
block7_out (PAD)

4.45
2
2.910
1.535
59/10

4.194
2
2.47
1.717
113/113

6.735
6
4.174
2.561
3147/209

10.513
8
2.748
7.765
1864/64

key (PAD)
x6_out
(PAD)
6.209
3
5.194
1.015
96/48

lddata (PAD)
data_ready_internal (FF)
3.63
2
2.833
0.840
11/11

k3_31 (FF)
key_out (PAD)
10.659
6
7.383
3.276
769/49

key_round_in (PAD)
r_in_internal (FF)
7.321
7
4.801
2.520
1886/249

core_busy (FF)

key_select
(PAD)
key_out (PAD)
12.083
1
8.010
4.073
739/48
17.48/17.94
18.00/18.00

key_select_0 (FF)

key_select (PAD)
4.571
1
3.863
0.708
70/70
24.47/24.81
24.00/25.00

18.55/18.91
19.00/19.00

7.19/7.53
7.00/7.00

8.83/10.83
9.00/11.00

Delay Time (ns)

Levels of Logic
Logic Time (ns)
Route Time (ns)
Paths/Destination Ports
Timing Constraint (2)
Source
Destination
Delay Time (ns)
Levels of Logic
Logic Time (ns)
Route Time (ns)
Paths/Destination Ports
Timing Constraint (3)
Source
Destination
Delay Time (ns)
Levels of Logic
Logic Time (ns)
Route Time (ns)
Paths/Destination Ports
CPU Time (s)
Elapsed Time (s)

core_busy (PAD)
4.31
1
3.68
0.447
2/2
17.19/17.52
17.00/17.00

4.937
2
4.490
0.447
48/48

61

157052

Memory (kB)
Particulars

S_box

153980

S1_box

158396

S2_BOX

155004

148860

147836

S3_box

S4_box

S5_box

S6_box

S7_box

S8_box

Timing
Constraint (1)
Block7_in
(PAD)

A (PAD)

A (PAD)

A (PAD)

A (PAD)

A (PAD)

A (PAD)

A (PAD)

A (PAD)

X7_out
(PAD)

SPO (PAD)

SPO (PAD)

SPO (PAD)

SPO (PAD)

SPO (PAD)

SPO (PAD)

SPO (PAD)

SPO (PAD)

Delay Time (ns)

9.295

8.964

8.947

8.947

8.964

8.964

8.964

8.964

9.295

Levels of Logic

Logic Time (ns)

7.061

6.740

6.740

6.740

6.740

6.740

6.740

6.740

7.061

Route Time (ns)

2.234

2.224

2.207

2.207

2.224

2.224

2.224

2.224

2.254

Paths/Destination
Ports

688/82

84/4

84/4

84/4

84/4

84/4

84/4

84/4

100/4

CPU Time (s)

11.36/11.70

7.75/8.09

9.02/9.34

7.98/8.34

7.73/8.08

7.53/7.88

7.58/7.94

8.92/9.28

8.67/9.02

Elapsed Time (s)

11.00/11.00

8.00/8.00

9.00/10.00

8.00/8.00

8.00/8.00

8.00/8.00

7.00/7.00

9.00/10.00

9.00/9.00

152756

148860

148860

148860

148860

148860

148860

148860

148860

Source

Destination

Memory (kB)

62

6.10 Device Utilization Summary of TWOFISH Algorithm

Particulars
s128

No. of Slices (4656)

No. of 4-i/p LUTs (9312)

Bonded IOBs (232)

394

692

192

374

655

192

data_input

256

data_output

256

f_128

704

1235

256

g_128

282

495

128

q0

18

32

16

q1

18

32

16

mds

57

102

64

mul_ef

16

mul_5b

16

pht

70

123

128

adder

encryption_round128

706

1239

384

decryption_round128

706

1239

384

h_128

240

423

104

keysched128

550

968

208

whit_keysched128

1803

3184

384

reed-solomon128

65

Particulars
mul01
mula4
mul55
mul87
mul5a
mul58
muldb
mul9e
mul56
mul82
mulf3
mul1e
mulc6
mul68
mule5
mul02
mula1
mulfc
mulc1
mul47
mulae
mul3d
mul19
mul03

No. of Slices (4656)

0
3
4
4
4
5
6
5
4
5
6
6
6
6
4
2
5
6
6
4
5
5
5
4

No. of 4-i/p LUTs (9312)

6
8
7
8
9
10
10
8
9
11
11
11
11
7
3
9
11
10
8
9
9
9
8

Bonded IOBs (232)

16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

66

6.11 Macro Statistics of TWOFISH Algorithm

1-bit xor2

1-bit xor3

1-bit xor4

8-bit xor8

32-bit xor2

4-bit xor2

4-bit
xor3

8-bit
xor4

16*4bit
ROM

s128

504

128

20

reed-solomon128

504

128

20

data_input

data_output

f_128

400

24

48

48

96

g_128

72

12

24

24

48

q0

q1

mds

72

12

mul_ef

mul_5b

10

pht

128

encryption_round128

400

24

48

48

96

decryption_round128

400

24

48

48

96

h_128

72

12

24

24

48

keysched128

272

24

48

48

96

whit_keysched128

1088

96

16

192

192

32

384

Particulars

adder

67

Particulars

1-bit xor2

1-bit xor3

1-bit xor4

mul01

mula4

mul55

10

mul87

mul5a

mul58

muldb

11

mul9e

mul56

mul82

mulf3

11

mul1e

mulc6

12

mul68

11

mule5

mul02

mula1

10

68

mulfc

10

mulc1

mul47

mulae

mul3d

mul19

mul03

69

6.9 Design Statistics of TWOFISH Algorithm

Particulars

IOs

BELS

LUT2

LUT3

LUT4

MUXF5

I/O
Buffers

IBUF

OBUF

s128

192

715

119

144

429

23

192

128

64

reed-solomon128

192

673

151

113

391

18

192

128

64

data_input

256

256

128

128

data_output

256

256

128

128

f_128

256

1243

258

296

681

256

192

64

g_128

128

498

128

47

320

128

96

32

q0

16

32

14

16

16

q1

16

32

14

16

16

mds

64

112

34

60

10

64

32

32

mul_ef

16

10

16

mul_5b

16

16

pht

128

125

85

36

128

64

64

encryption_round128

384

1251

257

237

745

12

384

256

128

decryption_round128

384

1251

257

237

745

12

384

256

128

h_128

104

426

91

42

290

104

72

32

keysched128

208

976

183

170

615

208

144

64

whit_keysched128

384

3227

585

633

1966

43

384

128

256

adder

63

Particulars

IOs

BELS

LUT2

LUT3

LUT4

MUXF5

mul01
mula4
mul55
mul87
mul5a
mul58
muldb
mul9e
mul56
mul82
mulf3
mul1e
mulc6
mul68
mule5
mul02
mula1
mulfc
mulc1
mul47
mulae
mul3d
mul19
mul03

16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

6
8
8
8
10
10
12
8
9
11
11
11
12
8
3
9
11
10
8
10
9
10
8

3
2
2
2
3
4
3
5
3
1
3
3
2
1
3
1
2
5

2
1
4
2
5
2
1
1
2
3
2
1
2
5
1
4
4
5
1
3

1
5
5
4
5
5
8
4
4
8
4
8
6
5
4
4
8
1
4
2
8
-

1
1
2
1
1
1
1
-

I/O
Buffers
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

IBUF

OBUF

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

64

6.12 Timing Summary of TWOFISH Algorithm

Particulars

Source

Destination

s128

data_input

in_key_ts128(
PAD)
in_rs128
(PAD)
in_tdi (PAD)

data_output
f_128

Levels
of
Logic

Logic
Time
(ns)

Route Paths/
Time Destination
(ns)
Ports

out_Sfirst_ts128 10.764
(PAD)
out_Ssecond_rs 11.941
128 (PAD)
out_tdi (PAD)
4.910

7.306

3.458

8.010

3.931

4.490

0.420

in_tdo (PAD)

out_tdo (PAD)

4.910

4.490

0.420

up_out_f128
(PAD)
out_g128
(PAD)
out_q0 (PAD)

71.244

49

27.455

19

q0

low_in_f128
(PAD)
in_g128
(PAD)
in_q0 (PAD)

10.578

37.19
5
16.07
5
7.306

34.04
9
11.38
0
3.272

q1

in_q1 (PAD)

out_q1 (PAD)

10.578

7.306

3.272

mds

y2 (PAD)

z1 (PAD)

9.615

6.602

3.013

mul_ef

in_ef (PAD)

out_ef (PAD)

7.823

5.898

1.925

mul_5b

in_5b (PAD)

out_5b (PAD)

6.422

5.194

1.228

pht

down_in_pht
(PAD)
in2_adder

up_out_pht
49.066
(PAD)
out_carry_adder 6.236

33

25.93
1
5.194

23.13
5
1.042

reed-solomon128

g_128

adder

Delay
Time
(ns)

1951/64

CPU
Time
(s)

20.86 /
21.19
1939/64
19.30/
19.64
128/128
7.37/
7.70
128/128
7.69/
8.03
3891031348 93.83 /
68 / 64
94.16
109530836 / 37.20/
32
37.59
576/8
8.81/
9.14
576/8
9.64/
9.98
431/32
12.66/
13.00
35/8
7.45/
7.80
22/8
6.98/
7.41
13915/64
10.42/
10.77
6/2
6.84/

Elapsed Memory
Time (s) (kB)
21.00 /
21.00
19.00/
19.00
7.00/
7.00
8.00/
8.00
94.00/
94.00
37.00/
37.00
9.00/
9.00
9.00/
10.00
12.00/
13.00
8.00/
8.00
7.00/
7.00
10.00/
10.00
7.00/

165564
161468
146812
147836
185020
177468
148860
148860
151932
146812
147836
149884
147836

70

(PAD)
in2_ter128
(PAD)

(PAD)
out2_ter128
(PAD)

72.623

50

37.89
9

34.72
4

7.20
4334212114 96.28/
36 / 128
96.64

decryption_round128

in2_tdr128
(PAD)

out2_tdr128
(PAD)

72.623

50

37.89
9

34.72
4

4334212114 102.64/ 103.00/

36 / 128
102.98 103.00

187068

h_128

in_h128
(PAD)

out_h128
(PAD)

27.805

19

16.07
5

11.73
0

109530836 / 34.09/
32
34.42

34.00/
35.00

175804

keysched128

even_in_tk12
8 (PAD)

out_key_down_
tk128 (PAD)

69.899

48

36.49
1

33.40
8

4583479222 85.20/
4 / 64
85.55

85.00/
85.00

192508

whit_keysched128

in_key_twk12
8 (PAD)

out_K7_twk128
(PAD)

63.544

43

32.97
1

30.57
3

2601538728 158.47/ 158.00/

/ 256
158.81 159.00

encryption_round128

7.00
96.00/
97.00

187068

202812

71

Particulars Source

mul01
mula4
mul55
mul87
mul5a
mul58
muldb
mul9e
mul56
mul82
mulf3
mul1e
mulc6
mul68

in_mul01
(PAD)
in_mula4
(PAD)
in_mul55
(PAD)
in_mul87
(PAD)
in_mul5a
(PAD)
in_mul58
(PAD)
in_muldb
(PAD)
in_mul9e
(PAD)
in_mul56
(PAD)
in_mul82
(PAD)
in_mulf3
(PAD)
in_mul1e
(PAD)
in_mulc6
(PAD)
in_mul68

Destination Delay
Time
(ns)
out_mul01 4.910
(PAD)
out_mula4
6.320
(PAD)
out_mul55 7.481
(PAD)
out_mul87 7.391
(PAD)
out_mul5a
7.506
(PAD)
out_mul58 6.697
(PAD)
out_muldb 7.608
(PAD)
out_mul9e
7.608
(PAD)
out_mul56 7.475
(PAD)
out_mul82 7.481
(PAD)
out_mulf3
7.608
(PAD)
out_mul1e
7.562
(PAD)
out_mulc6
7.586
(PAD)
out_mul68 7.992

Levels
of Logic

Route
Time
(ns)
0.420

Paths/
CPU
Elapsed
Destination Time (s) Time (s)
Ports
8/8
6.59/6.92 7.00/7.00

Memory
(kB)

Logic
Time
(ns)
4.490

5.194

1.126

18/8

7.09/7.44 7.00/7.00

146812

5.898

1.583

33/8

8.20/8.55 8.00/9.00

148860

5.898

1.493

28/8

9.30/9.84 10.00/10.00 147836

5.898

1.608

30/8

7.25/7.59 7.00/7.00

147836

5.515

1.182

31/8

7.41/7.73 7.00/7.00

147836

5.898

1.710

43/8

7.45/7.78 8.00/8.00

147836

5.898

1.710

42/8

7.53/7.86 7.00/8.00

146812

5.898

1.577

28/8

7.25/7.59 7.00/7.00

147836

5.898

1.583

32/8

7.44/7.78 7.00/8.00

148860

5.898

1.710

40/8

7.59/7.92 8.00/8.00

147836

5.898

1.664

33/8

7.58/8.00 8.00/8.00

147836

5.898

1.688

41/8

7.51/7.86 7.00/8.00

147836

6.219

1.773

39/8

7.45/7.80 8.00/8.00

147836

147836

72

mule5
mul02
mula1
mulfc
mulc1
mul47
mulae
mul3d
mul19
mul03

(PAD)
in_mule5
(PAD)
in_mul02
(PAD)
in_mula1
(PAD)
in_mulfc
(PAD)
in_mulc1
(PAD)
in_mul47
(PAD)
in_mulae
(PAD)
in_mul3d
(PAD)
in_mul19
(PAD)
in_mul03
(PAD)

(PAD)
out_mule5
(PAD)
out_mul02
(PAD)
out_mula1
(PAD)
out_mulfc
(PAD)
out_mulc1
(PAD)
out_mul47
(PAD)
out_mulae
(PAD)
out_mul3d
(PAD)
out_mul19
(PAD)
out_mul03
(PAD)

7.531

5.898

1.633

29/8

7.34/7.70 8.00/8.00

147836

6.280

5.194

1.086

11/8

6.86/7.22 7.00/7.00

147836

7.646

5.898

1.748

32/8

7.39/7.75 7.00/8.00

147836

7.606

5.898

1.708

37/8

8.28/8.63 8.00/9.00

148860

7.577

5.898

1.679

40/8

8.55/8.89 9.00/9.00

146812

6.376

5.194

1.182

22/8

7.44/7.77 8.00/8.00

147836

6.779

5.515

1.264

31/8

7.45/7.80 8.00/8.00

147836

7.531

5.898

1.633

31/8

7.64/8.01 7.00/8.00

148860

6.818

5.515

1.303

36/8

7.53/7.89 8.00/8.00

147836

6.326

5.194

1.132

19/8

7.34/7.80 7.00/8.00

147836

73

CONCLUSION__________________________________________________
The information security can be easily achieved by using Cryptography technique. A large
number of encryption algorithms have been developed to secure our confidential data from
the hackers. But some algorithms have been broken by using Cryptanalysis method. A key is
the strongest point of any algorithm but it can become the weakest point if it is not secured.
Our information can be secured if it is encrypted by using multiple keys or a large bit stream
of key (i.e., 128 bit, 256 bit, etc.). But to achieve this a large computational time is
required, giving a large delay which can be harmful to us. The hacker can hack the
information during this time. The use of FPGAs can help us to improve this limitation
because FPGAs can give enhanced speed. This is due to fact that the hardware
implementation of most encryption algorithms can be done on FPGA.
In this thesis, DES encryption algorithm is implemented on Xilinx Spartan 3E (XC3S500)
FPGA kit. The Twofish encryption algorithm is analysed by using Xilinx ISE 9.2i tool.

___________

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78