Eugen

Annamaria
MESARO$

LUPU

Aurel

SUCIU

MICROPROCESSORS
Architectures and Applications

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Editura RISOPRINT
Cluj-Napoca 2003

Conten ts

CONTENTS
PREFACE

1.

..... ... . ................................... ............ ............................

X86 PROCESSORS IDENTIFICATION

1.1. Introduction

.. . ........ .. ................ . ................

1.2. CPUID detection

1.3. CPUID outcome
1.4. The processor signature
1.5. The processor feature flags
1.6. The processor name
1. 7. The processor serial number
1.8. The access to the processor serial number

2.

3.

1.9. Applications
1.1a.Exercise

THE TIMER CIRCUIT

2.1. Functional Description
2.2. The timer pin assignment
2.3. The timer circuit programming
2.4. The timer circuit in PC
2.5. Applications and exercises
THE REAL TIME CLOCK AND THE CMOS MEMORY
3.1. General information

... . ................... ................... ..........................

19

.. .. ... ...... . ... . .......

29

3.2. MC 146818 circuit

.
3.3. The content of the memory and its accessing mode

3.4. System services for CMOS - RTC data access

4.

3.5. Applications and exercises

THE PROGRAMMABLE INTERRUPT CONTROLLER
4.1. Interrupts in data processing
4.2. The 8259A overview

39

............ ... . .. .. . ....

.

4.3. PIC Programming

4.4. 18259A controller modes
4.5. The PIC employment in PC

5.
6.

4.6. Exercise
APPLICATIONS ON THE INTERRUPT SYSTEM
5.1. The application support

... ........... . .... . ............

5.2. Exercise

OMA 18237A CONTROLLER

6.2. OMA controller overview

6.3. Functional Description of DMA Controller
6.4. Connecting the 18237 A controller.
6.5. The DMA controller in IBM-PC
6.6. Exercise

55

..... . .. . ................... . ......... ....... . . .. . . . ......

6.1. DMA transfer principle

51

Contents
7.

OMA DATA TRANSFER ON PC-AT.................................................71

7.1. The application description

7.2. The program

8.

7.3. Exercise

DESIGNING THE ISA-BUS COMPLIANT BOARDS ............................79

8.1. Buses in PC
8.2. The ISA bus
8.3. General considerations for designing a board on ISA-bus
8.4. Application

9.

8.5. Exercise

THE PARALLEL PORT IN IBM-PC COMPUTERS

....... . .

...

..

9.1. Generalities regarding the parallel port

. . . .. . . . ... . ... 91

9.2. The Standard Parallel Port (SPP)

9.3. Data transfer modes between standard ports
9.4. Parallel port-related BIOS services
9.5. Extensions of the parallel port
9.6. Application
9.7. Exercise

10. THE PARALLEL PORT IN IEEE 1284/94 STANDARD ......................103

10.1. IEEE 1284-1994 standard
10.2. Enhanced Parallel Port (EPP)
10.3. Extended Capabilities Port (ECP)
10.4. Application
10.5. Exercise

11. ON THE MEMORY IN PC SYSTEMS .............................................117

11.1. The memory organization
11.2. The PC memory map
11.3. Applications
11.4. Exercise

12. THE CACHE MEMORY ...............................................................129

12.1. An overview of cache memory
12.2. Architecture of the cache memory
12.3. Cache memory components
12.4. Cache memory organization
12.5. The Pentium processors cache memory
12.6. Cache memory characteristics identification
12.7. Exercise

APPENDIX 1: X86 PROCESSORS IDENTIFICATION

141

..... . . . . ............

APPENDIX 2: THE REAL TIME CLOCK AND THE CMOS MEMORY

APPENDIX 3 : DESIGNING THE ISA-BUS COMPLIANT BOARDS .

144
149

...

.....

APPENDIX 4: THE PARALLEL PORT IN IBM-PC COMPUTERS

APPENDIX 5: THE CACHE MEMORY

REFERENCES

...

...

. . . ....

..

. ...

.....

. .
.

...

. ....151

154

..............

157

. . . . . .................. . ............ . . . . ........ . .. ...... . . . . . . . . . . ........

PREFACE

This book is split i nto 1 2 chapters, which present aspects closely

connected to the PC hardware. Besides the topic d iscussed , each chapter
presents several applications linked to that topic. The book presents
aspects concerning the processor, the memory, the programmable
controllers employed , the buses and the parallel port of the PC .
It is recommended to the students i n electrical engineering and to
anyone i nterested to get deeper understanding of computers hardware .
The fi rst chapter covers the different aspects regarding the
identification of the processor used in the PC , its type and resources that
can be obtained usi ng the CPU I D instruction .
The second one presents the timer circuit ( 18253/8254 ) , its
employment mode and its role in a PC. Some applications using this circuit
are proposed as wel l .
The Real Time Clock and the CMOS memory ( M C 1 468 1 8) are
detailed in the third chapter.
Chapters 4 and 5 describe the Programmable I nterrupt Controller
(18259A) and propose some applications on the PC i nterrupt system .
Aspects on the Direct Memory Access Controller ( 1 8237A ) a n d a OMA
data transfer application on a PC-AT are presented i n the following two
chapters.
In chapter 8 , an overview of the PC buses is envisaged , focusing on
the ISA-AT bus. Aspects on designing the I SA bus compliant cards and a
design example are also presented .
The chapters 9 and 1 O present the

PC

Standard Parallel Port and

enhanced version d escribed i n the I EEE 1284/94 standard.

applications of these peripherals are discussed as well .

its

Some

MICROPROCESSORS

The following chapter deals with the memory organization i n PC

systems and with the way of connecting a memory extension (SRAM and
EPROM) to the PC-ISA bus.
The role and the operation principle of the cache memory and the
way its characteristics can be obtained by using the CPU I D instruction are
covered in the l ast chapter.
The attached appendices contain data book information concerning
some circuits and devices used i n the presented applications.
The authors wish to thank prof. Sergiu NEDEVSCHI and assoc. prof.
Zoltan BARUCH from the Computer Science and Automation Faculty of

Cluj-Napoca for reviewing the material and to assoc. prof. GRANESCU

MARINELA for the l i n g uistic review.
We also thank to all of those who hel ped us in publishing this book,
especially to our sponsors the compan ies SOJZA (Sighetul-Marmafiei) and
INFOMIN (Baia-Mare) and to Mr. Cristian Vasi/ache for h is contri bution to

the figure editi n g .

Ph .D. eng . Eugen LU PU

E lectronics&Telecommunications
Faculty of Cluj-Napoca
Comm unications Department
Eugen .Lupu@com. utcluj . ro

XB6 Processors Identification

1. X86 PROCESSORS IDENTIFICATION

1.1

Introduction

At the same time with I ntel Architecture progress, in new processor

generations and models it became essential to provide a software modality
to detect the processor featu res. This mechanism of identification evolved
at the same time with I ntel architecture:
1 . Initially, I ntel published code sequences which could detect minor
implementations or differences in architecture for processor generation
identification.
2. With 386-processor development, I ntel implemented the identification
signature of the processor, which provides the family and the model of the
processor.
3. The processor identification signature expanded at one time with the
implementation of CPUID instruction for the new versions of 486. This
instruction provides not only the processor signature but also information
about the offered facilities, the producer, the type of the processor, the
model number, stepping and cache memory dimension and organization .
1.2

CPUIQ detection

Starting with the I ntel 486 processor family, the processors are able to
execute the CPU I D instruction . To execute the CPUID instruction , the
program has to establish if the processor supports the instruction. This can be
done in two ways:

The instruction is executed and then one verifies if there appeared an

exception due to an illegal operation

One verifies if the I D flag 21st bit of EFLAG register (see Appendix 1 ) can
be modified . If the program can change this flag value, then the processor
supports the CPU I D instruction. For this test the following sequence can
be used:
pushfd
pop eax
mov ebx , eax
xor eax , 0 0 2 0 0 0 0 0h
'
push eax
popfd
pushfd
pop eax
cmp eax , ebx
j z NO CPUID
,

s ave s EFLAGS on s tack

l oads E FLAGS in EAX
s ave s E F LAGS in EBX
S e t s ID bit ( 2 1 s t )
save s EAX on s t ack
EFLAGS=EAX

save s EFLAGS
l oads E FLAGS
has the 2 1 s t
Z = 1 CPUID is

on s t ack
in EAX
b i t change?
not supported

XB6 Processors Identification

1.3 CPUID

outcome

The CPUID instruction has multiple functions, depending on the

content of EAX register. The execution of CPUID for different values in EAX
provides a complete image of the processor and its capabilities. The
functions can be divided in two categories: standard functions, that provide
usual information of x86 processors and extended functions, that provide
additional information about the producer (Intel, AMO etc). To determine
the highest value supported by the CPUID instruction in the EAX register
for the standard functions, the program must set the register value to "O"
and then execute the CPUID instruction as follows:
MOV EAX,OOh
CPU ID

After the execution of this sequence, a value is returned in EAX as a

parameter of CPUID; this is the maximum value for EAX.
The extended functions of CPUID instruction were introduced by AMO; they
return additional information about the processor. To determine the highest
value accepted in the EAX register by the CPUID instruction, in order to
return the extended information about the processor the program must set
EAX register to "8000_0000h", then run the instruction that returns the
needed value in EAX.
MOV EAX, eopoOOOH
CPU ID

The extended functions are supported by the processors provided by other

producers too, starting with:

AMO K6 K6-2
Cyrix GXm Cyrix Ill "Joshua"
IDT C6-2
VIA Cyrix Ill
Transmeta Crusoe
Intel Pentium 4

Additionally, one can check the ASCII string that identifies the producer. If
EAX=O, the CPUID instruction returns the producer identifier in the EBX, EDX
and ECX registers. These registers contain the ASCII string "Genuinelntel"
(see Table 1 . 1 ) for Intel processors or different producer specific strings (see
Table 1.2).
6

X86 Processors Identification

ECX
BDX
BBX

31...

2 3 ...

15 ...

(6C)

(65)

(74)

(6e)

(49)

(65)

(6e)

(69)

(75)

(6e)

(65)

(47)

Table 1.1 INTEL ID string

ID string

Producer

Genuineintel

Int e l

UM C UM C UMC

UMC

Authent icAMD

AMD

Cyrixinstead

Cyrix

NexGenDriven

NexGen

CentaurHauls

Centaur

RiseRiseRise

Rise Techn.

GenuineTMx86

Transmeta

Table 1 . 2 Proces sors producers ID s tring

The standard and extended functions are presented in Table 1 .3.

Differences may occur with different producers, certain functions being
supported only by some processors (example 8084_000xh for Transmeta
or 8FFF _FFFxh for AMD), therefore specific documentation is
recommended.
Parame ter
EAX "O

Information re turned
EAX

highest

the

by

CPUID instruction

value

recognized

EBX:EDX:ECX ID of the producer

EAX " l

EAX

the

processor

by

CPUID

(ASCII string)
32

signature:

MSB

(95-64)

from

the 96 bits of the processor serial number

EDX processor feature flags

EBX Brand ID on bits 7 .. 0

EAX ,,2"

EAX:EBX:ECX:EDX
descriptors

EAX,, 3"

EDX:ECX

EAX .. aooo_ooooh
EAX .. 0000_0001h

information

about

EAX,,8000 0002h
0003h

EAX,,8000 0004h

EAX .. 0000 0005h"

EAX .. aooo 0006h"

EAX .. aooo 0007h"

EAX .. aooo 0008h"

TLB

the

64

LS B

from

the

96

of

the

CPUID

for

bits

processor serial number

EAX

the

highest

value

recognized

by

extended functions

EAX

extended

processor

signature

feature flags

EAX .. aooo

and

cache

(Translation Lookaside Buffer)

EAX:EBX:ECX:EDX processor name

EAX:EBX:ECX:EDX processor name

EAX:EBX:ECX:EDX processor name

Ll TLB/

cache information

L2 TLB/ cache information

Advanced power management feature lags
Physical address and linear address size

* Int e l proce s sors

#AMD proces sors

Table 1 . 3

CPUID outcome

and

extended

X86 Processors Identification

Figure 1. 1 is a capture of the values returned by an application executed on

a PC with Intel processor, for EAX set at different values.

:
EAX=00000003
)
:
EAX=00000686
:
EDX=038?F9FF
Flags =000B?046

EAX=03020101
EBX=00000000
ECX=00000000
EDX=0C040882

Fig 1.1 Processor identifying application

1.4

The processor signature

Beginning with the Intel 486 family, the processor will return an
identification signature in the EDX register after RESET (see Fig 1.2). The
identification signature is a 32 bits value, consisting of 8 fields; two of them
are reserved (see Fig 1 .2}.
EDX
31 .. 28 27 ..

20 19

1615 14 13 12 11

Family

Model

extension

extel\sion

Type

Family

Model

ID

code

number

version

Fig.1.2 The EDX register value after RESET

The processors which recognize ------CPUID return the processor

identification-filg!l_ture in EAX for EAX=4_ see Fig 1. 1)_,_Figure 1.2 indicates
the signature formatTorTnTel processors s arting with 486. The Table A 1 in
Appendix 1 shows the values returned to EAXJor the Intel processors. The
processor type specified by th_e_biisJD positions 12_JJQ _13 indicates if the
proc-ess6r is OEM original Overdrive orTfTfls-a-aual processor (capable of
working simultaneously with another processor in a system). Table 1.4
indicates the returned bit values in the positions 1_2 and 13 of the EAX
register, depending on the processor type:

Value

__

Description

00

Original OEM processor

01

Overdrive processor

10

Dual processor

11

Intel reserved

Table 1.4

The processor type

(bits 12

and 13)

X86 Processors Identification

1 1 indicate if the processor

The family values specified by the bits 8
belongs to I ntel 386 family, Intel 486, Pentium, P6 or Pentium 4. The P6
processor family includes all the processors based on Pentium Pro
architecture that have a family code equal with 6 and Pentium 4 processors
have the code F.
The model number specified by the bits 4 . . . 7 indicate the processor
family mos from indicate the version number of that
model . Older versions of I ntel 486 processors SX/DX/DX2 do not know
CPUID, so they can return the signature only on RESET.

1.5 The

processor feature flags

When EAX=1 , CPUID will load the EDX register with the processor
feature or resources flags. The current flag indicates which features the
processor supports. Table 1 .5 indicates the different values of the features
flags. For future processors flags values one should consult the reference
guide or user guide or own documentation .
B y testing the processor feature flags in developed applications, the
software can detect and avoid eventual errors and incompatibilities.
it j Name
Description when
Comments
I
I
flag=l
0

FPU

VME

DE

Floating point unit

on-chip

The processor contains on chip a FPU

which supports the 387 coprocessor

floating point instructions set

Virtual Mode
extension

The processor supports extensions for

8086 virtual mode

Debug. Extension

The processor supports

interruption

I O

PSE

Page size extension

The processor supports 4MB pages

TSC

Time stamp counter

RDTSC instruction is supported

including CR4.TSR bit for access
privHege control

MSR

Model Specific
registers

Model specific egisters are

implemented with RDMSR,WRMSR
instructions

PAE

MCE

cx0

9
10

Physical Address

extension

APIC
-

11

SEP

12

MTRR

Physical addresses greater than 32

bits are supported

exception

Machine check exception 18 and

CR4.MCE bit are supported

CMPXCHG8 instruction

The compare and exchange instruction

Machine check

on 8 bits is supported

supported

CMPXCHG8,

On-chip APIC
hardware suooorted

The processor contains a softwareaccessible local APIC

Reserved

Fast system call

Indicates if the processor supports

SYSENTER SYSEXIT instructions

Memory type range

registers

The processor supports memory type

range registers (MTRR CAP register)

XB6 Processors Identification

13

PGE

Page Global Enable

The global bit from PDE and PTE are

supported, indicating TLB entries.
CR4.PGE bit controls this feature

14

MCA

15

Machine check
architecture

Machine check architecture is

supported (MCG CAP register)

CMOV

16

Conditional move
instruction
supported

FPU flag (bO)is set, it supports

FCMOVCC and FCOMI instructions too

PAT

PSE36

17

PSN

18

CLFSH

20
21

DS

22

ACPI

/23

'--"'

MMX

24

FXSR

S'

SSE

SSE2

27

SS

Page attribute table

Indicates if the processor supports

PAT- allows an Operation System to
specify attributes of memory on 4KB
granularity through a linear address

36-bit Page size

Indicates if the processor supports

4MB pages capable to access physical
addresses greater that 4GB

extension
The processor serial
number is present
and enabled

19

CLFSH instruction is
supported

Thermal Monitor and

Software Controlled
Clock Facilities
s upp orted

The processor implements internal

MSRs for processor temperature
monitoring and performance modulation
under software control

Intel Architecture
MMX technology
Supported

The processor supports MMX technology

specific instruction set

Fast floating point

save and restore

Indicates if the processor supports

FXSAVE and FXRSTOR instructions

Streaming SIMD
extensions supported

The processor supports Streaming

extension SIMD to Intel architecture

Streaming SIMD
extension 2

The processor supports the streaming

SIMD extension 2 instructions

Self-Snoop

The processor manages memory conflicts

by executing a cache snoop for
transactions issued to the bus

Reserved

30

Reserved

Table

Indicates that the processor supports

the CLFSH instruction
The processor can rewrite the history
of the branch to/from addresses into
a memory buffer

serial number and this option is

activated

Reserved

TM

31

The processor supports a 96 bits

Debug store

29

28

The processor supports CMOSVcc and if

Thermal monitor
supported

The processor implements the thermal

control circuit TCC

Reserved

1.5

The f eature flags values reported in the EDX regi ster

10

XB6 Processors Identification

1.6 The processor name

At the same time with Pentium Ill, Pentium I l l Xeon and Intel Celeron
model 8, Intel extended the identification concept by adding the Brand ID
information, which is an 8-bit number accesible by CPUID instruction.
When EAX=1, CPUID loads the processor Brand ID in the O -7 bits in EBX.
This field was introduced to eliminate identity ambiguities (such as the
difference between Pentium II and Pentium II Xeon
51 2 K L2 cache),
providing a unique value for every processor name. Table 1.6 shows the
correspondence between the bits from the EBX and the corresponding
names.
EBX o 7
Description
-

...

ooh
Olh
02h
03h
04 h
08h
OEh
A l l other values

Table

1 .6

No t supported
I nt e l C e l e ron processor
Int e l Pentium I I I pro c e s s o r
I nt e l Pent ium I I I Xeon proce s s o r
I n t e l Pent i um I I I proce s s o r
I n t e l Pent ium 4 proc e s so r
I n t e l Xeon proce s s or
Re s e rved

Brand ID corresponding to values in EBX (bits

0)

1. 7 The processor serial number

The Pentium Ill and Pentium Ill Xeon processors extend the
identification concept by attaching the processor serial number. The serial
number is a 96-bit number accessible by CPUID. This number can be used
by applications to identify the processor and the system.
The serial number of the processor creates a software identity accessible to
an individual processor. Combined with other features, the serial number can
be applied to user identification. Applications include authentication data,
backup/restore protection, file access protection or documents exchange
between users. The serial number is a modality to check the products. In the
case of system service, the serial number can be used to differentiate users
or for error report.
The serial number provides an identifier for the processor but one
should not consider it as a unique number. There are some ways that can
report wrong serial numbers. For example, if a processor operates outside a
specified operating system, the processor will not read correctly its serial
number. BIOS or software improper operations can produce wrong serial
numbers.
11

XB6 Processors Identification

1.8

The access to the processor serial number

To determine if the processor series' characteristic is supported, the

software must execute CPU I D with the EAX register set to "1":
MOV EAX , O lH
CPUID

After running CPU I D , EDX contains the feature flags. If the j 8th bit
fla is 1, the seri n_ller of !!Je pro.@"'-_or is suppofled. If the
fr
18th bit from the register is O, thr.o.c_es.sor serial 11umbefTsnoi supp_orted
or ltisdisaI)ledotnerwiSefue-serial number is supported. This bit can be
conlrolled from the (for the newer processors) or by specific
ap
ns provided by the producer. To disable the access to the !Iial
nJ1ter one must set to "1" th--21.s.t_Qii_gf BBL_CR_CTL MSR register
(ModeTSpecffiCReglsterfrOm-address 119h). Once set, this bit cannot be
modified until the processor reset. Tne next sequence is an example that
can be used to disable the access to the processor serial number:

pliCatiO

MOV ECX , 1 1 9h
RDMSR
OR EAX , 0 0 2 (')0,0 0 0h
WRMSR
..

;reads MSR
;set s the 2 1 s t b i t
;wr i t e s MSR

The 96-bit serial number is the concatenation of three 32-bit entities.

To access the most significant 32 bits of the serial number, the program
must set the EAX register to 1 and then execute CPU I D : .
MOV EAX , O lh
CPU I D

After running CPU I D , EAX contains the most significant 32 bits (95-64)
of the serial number. This value from EAX must be saved before obtaining the
other 64 bits of the serial number. In order to access the other 64 bits, the
program must set EAX to 3 and then execute CPU I D :
MOV EAX , 0 3 h
CPUID

After running CPU I D , EDX contains the middle 32 bits (63-32) of the
serial number and ECX contains the less significant 32 bits (31-0). The
program must then concatenate the most significant 32 bits, EDX and ECX
before returning the complete serial number on 96 bits. The serial number
must be displayed as 6 groups of 4 hex digits.
12

XB6 Processors Identification

1.9 Applications

Analyze the following programs CPU I D .CPP and CPU I D .ASM and
then run it on the PC. Analyze the results.
#pragma hdr s t op
# inc lude <conde f s.h>
# inc lude < s t dio . h>
#inc lude <Stdlib.h>
#inc lude <conio . h>
void decode_reg(int ) ;
void print reg(int reg ) ;
void PrintLeve l Cpuid( int l evel ) ;
vo i d cpu i d(uns igned inp ) ;
unsigned l ong Lax , Lbx , Lcx , Ldx;
vo i d cpu i d ( uns igned inp )

asm

. 59 6
mov eax , inp
cpu i d
mov Lax , eax
mov Lbx , ebx
mov Lcx , ecx

};

mov Ldx , edx

int main( )

int i;
uns i gned l ong l i , maxi , maxei;
/ * Print the information returned by CPUID f or the l eve l O * /
cpu i d(O ) ;
max i =Lax ;

/ /maximum parameter number

for(i= O ; i <=maxi ; i+ + )
print f("\n\nCPUID l eve l %d11 , i ) ;
PrintLeve l Cpuid ( i ) ;

/*print the

informat ion returned by CPUID for l eve l

the OxB O O O O O O O * /

cpu i d(OxB O O O O O O O ) ;
maxei= Lax ;

/ /maximum parameter number for ext ended func tions

for( l i = O x B O O O O O O O ;l i<=maxe i ; l i+ + )

printf ( "\n\nCPUID l eve l %d11 , li ) ;

PrintLeve l Cpuid( l i ) ;

if (maxei= = O )

13

XB6 Processors Identification

p r int f ( " \n\nDoes not support ext ended l evel for CPUID " ) ;
print f ( 11 \n\n " ) ;
/ * Producer ID and maximum level suppo rted by CPUID */
cpuid ( O ) ;
print f ( " I D : \ " " ) ;
for ( i= O ; i<4 ; i + + ) put char ( Lbx >> ( S *i ) ) ;
for ( i = O ; i < 4 ; i+ + ) put char ( Ldx >> ( S *i ) ) ;
for ( i= O ; i<4 ; i+ + ) put char ( Lcx >> ( S *i ) ) ;
prin t f ( " \ " ; CPUID l evel % l d\n " , maxi ) ;
//wa it for any key press
getch ( l ;
exit ( 0 ) ;
/ * Regis t e r decoding x
vo id decode_reg ( int x )

regi s t e r va lue * /

x &= Oxf f ;
printf ("%02x 11,x);

/ / Pr int reg i s t e r va lue

vo i d print reg ( int reg )

decode_ reg ( reg >> 24 ) ;

decode_reg ( reg >> 1 6 ) ;
de code_reg ( reg >> Sl
de code_reg ( reg ) ;
'

/ / Print cpuid l eve l and returned va lues

void PrintLeve l Cpuid ( int l eve l )

cpuid ( l eve l ) ;
print f ( 11\n
eax :
printreg (Lax)
print f ( " \n
ebx:
print reg ( Lbx )
e cx:
print f ( " \n
print reg ( Lex )
edx:
p r i nt f ( " \n
print reg ( Ldx )

") ;
;

") ;
;
") ;
;
") ;
;

14

X86 Processors Identification

TITLE CPU ID
JUMPS
. model small
. st a ck 1ooh
. da t a
s aved_ cpuid
vendor id
cpu_type
themode l
s tepp ing
id_ f l ag
inte l_proc
id_msg
Pent ium
in t e l
mode lmsg
s t epp ingm sg
f ami lymsg
period
data CR
int e l id
. code
.8 0 8 6
s t art:

dd

db
db
db
db
db
db
db
db
db
db
db
db
db
db
db

mov
mov
mov
and
call
cal l
mov

?
12 dup (? )
?
?
?
0
0

"Thi s sy s t em has $ "

"Pentium(TM ) microprocessor" , 1 3 , 1 0 " $ "
" In t e l Proce s sor sy s tem " , 1 3 , 1 0 " $"
" Mode l :
$"
"Ve r s i on :
$"" Fami ly : $ "
11 11 , 1 3 , 1 0 , 11 $ 1 1
? , 1 3 , 1 0 , "$ "
"Or iginal Int e l "

ax , data
ds , ax
e s , ax
sp not , 3
get_cpu id
print
ax, 4 c 0 0h
2 1h

s e t s egment reg i s t er
s e t s egment reg i s te r
al ign stack t o avo id
AC e rror
prog ram end

int
get_cpuid proc
.586
mov
i d_ f l ag , 1

s e t ind i cator f l ag
for CPU I D
paramet er for CPUI D

mov
eax , O
cpuid
dword ptr vendor_id , ebx
mov
; t e s t for I nt e l producer
dword ptr vendor_ id[ + 4 ] edx
mov
dword ptr vendor_ i d[ + 8 ] , ecx
mov
s i , o f f s e t vendor id
mov
d i , o f f set int e l id
mov
mov
cx, l ength int e l_ id
compare:
cmpsb
repe
i f I nt e l original ecx
cx , O
cmp
cpuid_data
jne

15

XB6 Processors Identification

int e l _proc essor :
mov
mov

int e l _proc , 1
[intel - 1 ) , '

adds space for message

" orig inal Inte l "

cpu id_data :
mov
eax , 1
cpui d
mov saved_cpu i d , eax
eax , O F O OH
and
eax, 8
shr
cpu_type , a l
mov
mov
mov
and

eax,saved_cpuid
stepp ing,al
st epp ing, O FH

mov
mov
and
shr

eax,saved_cpu id
themode l,al
themode l , O F
themode l , 4

end_get_cpu i d :
. 8086
ret
get_cpuid

save for u l te r i o r use

mask informat i on about fam i l y
saves CPU type
recover data

mask mode l number

mask informat ion about mode l

..

endp

; This procedure disp l ays the processor

f e a tures

proc
ax
push
push
bx
push
ex
dx
; ver i fy i f the processor supports CPU I D
push
cmp
i d_f l ag,1
; if yes disp l ay informat ion
je
p r i nt_cpu id_data
dx,of fset id_msg
mov
mov
ah , 9h
disp l ay init i a l message
int
2 1h
print_cpu id_data :
cmp
cpu_type,5
p r i nt_cpu id_cont
j ne
dx,o ffset Pent ium
mov
mov
ah 9
2 1h
int
print_cpu i d_cont :
disp l ay " f ami ly : "
dx,o f fset f ami lymsg
mov
ah 9h
mov
2 1h
int
mov
a l , cpu_type
mov
byt e ptr dat aCR,al
add
byt e ptr dat aCR,3 0H
convert t o ASC I I

print

16

XB6 Processors Identification

mov
mov
int
mov
mov
int
mov
mov
add
mov
mov
int
mov
mov
int
mov
mov
add
mov
mov
int
end_pr int :
pop
pop
pop
pop
ret
print
endp
end

1.10

'

dx , of f s et dat aCR
ah 9h
2 1h
dx , of f s e t s t eppingmsg
ah 9h
21h
al , s t epp ing
byt e ptr dataCR , al
byt e ptr dat aCR , 3 0H
dx o f f se t dataCR
ah , 9h
21h
dx , of f s e t mode lmsg
ah , 9h
21h
a l , themode l
byt e p t r dataCR , al
byt e p t r dataCR , 3 0H
dx , of f se t dataCR
ah, 9h
21h

d i sp l ay CPU type

di sp l ay " s e r i a l no : "

convert t o ASCI I
di sp . s e r i a l number

display "mode l : "

convert t o ASC I I
display mode l number

dx
ex
bx
ax

start

Exercise

a. Analyze the results from fig . 1 . 1

b. Using the turbo debugger TD32 test the standard and extended functions
of the CPUI D instruction. Analyze the results obtained on you r PC.
c. If the processor allows it, determine its serial number
d. Study the possibility of accessing the processor serial number.

17

X86 Processors Identification

1st.

Year

CPUs

PC

Number of

transistors

8086 and 8088

1978-81

29,000

80286

1984

134' 000

80386DX and 80386SX

1987-88

275,000

80486SX, 80486DX,

1990-92

1,200,000

3,100,000

Generation
2nd.
Generation
3rd.
Generation
4th.
Generation
5th.
Generation

5th.
Generation
Improved
6th.
Generation

6th.
Generation
Improved

80486DX2 and 80486DX4

Pentium

1993-95

Cyrix 6X86

1996

AMD KS

1996

IDT WinChip C6

1997

3,500,000

Pentium MMX

1997

4,500,000

IBM/Cyrix 6x86MX

1997

6,000,000

IDT WinChip2 3D

1998

6,000,000

Pentium. Pro

1995

5,500,000

AMD K6

1997

8,800,000

Pentium II

1997

7,500,000

AMD K6-2

1998

9,300,000

1999

27,400,000

Mobile

Pentium II

Mobile Celeron

18,900,000

Pentium III

9,300,000

AMD K6-3
Pentium III CuMine
7th.
Generation

28,000,000

AMD original Athlon

1999

22,000,000

AMD Athlon Thunderbird

2000

37,000,000

Pentium 4

2001

42,000,000

18

The Timer Circuit

2. THE TIMER CIRCUIT

2.1 Functional Description

The 1 8253 circuit ( 1 8254 for PC-AT) is a programmable timer/counter

that contains three independent 1 6-bit cou nters, having attached the
adequate logic for tt.le communication with the microprocessor and other
devices. The m icroprocessor sees this circuit as a successive 1/0 ports
table; the circuit can be used as a cou nter for outside events ,
programmable square wave generator, delay circuit for processes control,
etc.
The i nternal block schematic of the circuit is represented i n figure 2 . 1 .
The data bus buffer i s o n 8 bits, bi-directional, with three-states output; i t is
the 18253 circuit i nterface to the system data bus.
D0 ... 07

Data

Bus

Buffer

/RD
/WR
/CS
AO
Al

R/W

Logic

2.

word

Registe

Fig.2.l The timer

block

CLKO
GATEO

OUTO

CLKI
GATE!
OUT!

CLK2
GATE2

OUT2

diagram

Through this buffer, the data is transferred from and to the circuit; this
is the way to program the working mode for the three existing channels, by
loading the counters y.tith the adequate time values or by reading the values
from the counters.
The counters (chan nels) 0 , 1 ,2 a re identical, independent, each one
being a 1 6-bit presetable countdown counter. Each cou nter can be selected
to cou nt BCD or binary. Their content can be read anytime without being
modified .
19

The Timer Circuit

The R/W logic allows the circuit selection and the circuit registers
reading and writing control. The operations that take place for different
combinations of the control signals are presented in table 2 . 1 . The control
word register keeps the circuit programming information, which selects the
desired work mode for different channels.

/CS

/RD

/WR

Al

AO

0
0
0

0
0

1
0

1
1
0

0
0

1
1

0
1

1
0

Function

Loads coun t e r O
Loads c oun t e r 1
Loads coun t e r 2
Loads the contro l reg i s t e r
Reads coun t e r 0
Reads c oun t e r 1
Reads coun t e r 2
Not f unc t i on i ng
Unse l e c t e d c i rcu i t
Not func t i oning

Table 2 . 1 Regis ter operations for the timer

2.2 The timer p i n assignment

The circuit ha 24 pins with the functions shown in figure 2.2. Bes!de

the power, data and control signals, the typical signals for each channel are
the following:
Clk, (Clock)- are the clock entries (pulses) for the counter. The maximum
allowed frequency is 2 ,6 MHz (for 18254 is 1 0 MHz)
Gate.- these entries can work as validation gates for the clock entries or as
counting start pulses, depending on the programming mode of the circuit.
Out,- represents the channels outputs, whose evolution is dependent on
the circuit-programming mode.
8

CLKO
GO

9
11

CLKI
GI

15
14

OUTO

5
4
3
2

13

n
23
19
20
ll

10

CLKl
G2
OUTl

18

16

11

cs

8253

Fig . 2 . 2 The timer pins ass ignment

20

The Timer Circuit

2.3 The timer programming

The programming can be made by writing in the control word register

the control byte corresponding to the desired working mode. The bit
significances of the control byte are shown in figu re 2.3. The selected
channel is considered to be programmed if one has set the control word
and one or two bytes are written in the counter (according to bits 5 and 4);
this operation is followed by a rising and a fal l i ng edge of the clock signal .
The time diagrams for the channels work modes are presented i n figure
2.4.
Mode 0 - Interrupt on Terminal Count. After loading the adequate control
word , the selected counter output is forced to "O" and then the cou nter is
loaded with the programmed val ue, which will be decremented at each
clock pulse. The output wil l be " 1 " only when the value from the counter
becomes "O" and remains in this stage until a new loadi ng of the counter,
occurs . The decrementation process continues after reaching the final
value. The counter reloading stops the current operation if the first byte is
loaded or it starts a new operation if the last byte is loaded .
Q..,
'
4)
..
I
3
4
2
5
0
f f
"" O:.R.
\ \ \. t,}\n
01
N
so
M2
MO
M1
00
51
--7
. \A '

{j\ .

00
01
10
11

0- binary counting
00- reads counter
1- BCD counting
0 1 - reads/loads low byte
1 0- reads/loads h igh byte
1 1 -reads/loads low and then 000 - mode o ( lntrerrupt on Termi n al Count)
high byte
00 1 - mode 1 ( Programmable One-Shot)
x 1 0 - mode 2 ( Rate Generator)
- cou nter 0
x 1 1 - mode 3 ( Square Wave Rate Generator)
- cou nter 1
1 00 - mode 4 ( Software Triggered Strobe)
- cou nter 2
1 0 1 - mode 5 (Hardware Triggered Strobe)
- i l legal command

Fig . 2 . 3 The control byte

Mode 1 - Programmable One-Shot. The counter output changes from "1"

to "O" only after the control word and the counter had been loaded and the
signal applied to the gate has a rising edge . This edge launches the
decrementation and at passing through "O", the output wil l become "1"
again. If a new value is loaded i n the counter during the counting, it will not
affect the length of the pulse u ntil a new start. The current value of the

21

The Timer Circuit

cou nter can be read without affecting the output. If a rising edge i s present
at the GATE input at some time during the pulse, it produces a new start of
the cou nting from the last value stored in the counter (fig.2.4 )
.

Mode 2 Rate Generator (Divide by n counter). The output wil l be " 1 " for
(n- 1 )TcLK periods after the control word and the counter value loading and it
wil l became "O'' i n the n-th period . If the GATE input is forced to "O'' during
the cou nting, the output will become " 1 " and when the GATE input returns
in " 1 " , the cou nter will decrement again from the in itial value; the GATE
input can be used for the cou nter synchronization. The counter
decrementation starts immediately after the last data byte loading and if the
cou nter is reloaded d u ring this period , the change wil l be reflected in the
next period .
-

Mode

CL Ki

Interrupt on Terminal

Count

WR

OUTi

(n= 4)-----------+---+---+---+--/

------

Mode

CL Ki

GATE
OUTi
(n=3)

Programmable

Mode

CL Ki

(n=3J

Mode

CLKi

WR

OUTi
(n=4)
Mode

CLKi

___,

21

0.

._I --+I ---+---+1---+l---+-----'

1

Rate

WR

OUTi

Generator

Square Wave Rate

Generator

__..

...__

0(4)

2
4 Software Triggered Strobe

3
I

WR
OUTi-----1--'---
Mode

CL Ki

GATE

4
0
--+-- -- -(n=4,
1-l1-- -+-+- --:_
1
-+

OUTi

Fig . 2 . 4 Timer operation modes

22

____,

The Timer Circuit

Mode 3

Square Wave Rate Generator.

........-- u.

""' L(

e.ve.......

JJ

,.Z
(?1+1,Yi...
-:.

C'
(j

Mode 4- Software Triggered Strobe. After this mode programming, the

selected chan nel output becomes " 1 " and the decrementation starts after
loading the selected counter with the computed value. When the counter
wil l get to 0, the output becomes O for a clock period and then it returns to
"1 . The cou nting is inhibited by the GATE input passing to O and it is
resumed from the last loaded value when the GATE i nput passes to "1 "
again; this allows the implementation of a retriggerable.
The counter reloadi ng can appear in two cases:
- when the cou nter is generating a single-pulse (in thi s case the current
pulse is not affected , but at its ending a new single-pulse will be
generated , adequate to the new value);
- when the counter is standing-by, a pulse will be generated , adequate to
the new value stored in the counter.
"

"

"

"

"

Mode 5 - Hardware Triggered Strobe. The counter will start counting

after the cou nter value loading on the rising edge of the GATE input. When
the counter arrives in 0, for a CLK period , a rising edge on the GATE input
retriggers the counter.

I
B

Low
Or
Fal l ing Edge

Rising Edge

- Di s ab l e s coun t i ng

- Di s ab l e s Counting
- S e t s output
immediat e ly high
- Di s ab l e s counting
- S a l e s output
immediat e ly high
- Di s ab l e s counting

High
- Enab l e s
Counting

- I nitia t e s counting
- Re s e t s output a f t e r
next c l ock
- Re l oads coun t e r
- I nitiat e s counting
-

Initiat e s c ounting

- Enab l e s
counting
- Enab l e s
c ounting
- Enab l e s
c ounting

Initi a t e s c ounting

Table 2 . 2 The Gate signal operations summ a ry

2.4 The timer circuit in

PC

For compatible IBM computers, one uses a timer circuit for fulfilling
d ifferent functions. The three circuit channels are used for:
23

The Timer Circuit

the system clock - CO

DMA transfer request (on 0 DMA channel) for DRAM refresh - C 1
(for PC-XT)
loudspeaker command - C2; see fig.2.5.
The clock inputs at the three channels results from the PCLK signal,
divided by 2 , so 1 . 1 93 M Hz, starting from 1 4 . 3 1 8 1 8 M Hz chosen quarts
freque ncy oscillator. The reserved PC port addresses for the timer circuit
are between 40h-43h.
Channel 0 is programmed in mode 3, with the d ividing value 0, that is
216 ; at the OUTO output there result pulses with a period of 55ms ( 1 8,2
pulses/s) that generate interrupts at 18259A interrupt controller IRQO input.
The generated hard interrupts are type 8 interrupts and they are used for
the system clock implementation; its handler realizes:

the system clock value update

the floppy u n it motor stopping after 2 seconds of inactivity
the launching of the 1 Ch interrupt, for user routine.

Beside the 08h interrupt, the I NT 1 Ah soft i nterru pt offers services

connected to the system clock.
For PC-XT, channel 1 command the DMAC (18237A) DRQO input,
generating the DRAM memory refreshing cycles.
Channel 2 , after passing trough a gate type validation logic (controlled by
the PIO circuit at PC-XT or 18042 at PC-AT} and an amplifier stage,
commands the PC loudspeaker (fig .2.5).
1. 193MHz
.-----.. IRQO(l8259A)
---CLKO
OUTO-----+
' 1
GATEO

' l'

BO Bl

CLKl

DRQO (PC-XT)
OUTl -----

GATEl

PORT B (61H)
PIO-I8255A

Fig . 2 . 5 The use of timer channel s in PC

24

The Timer Circuit

2.5 Applications a nd exercises

2.5.1 The next application generates the fourth octave notes i n the
PC loudspeaker. The notes frequencies in Hz are showed in the following
table:
DO
2 61. 6 Fa#
370
DO# 2 7 7 . 2 Sol
3 92
Re
3 9 3 . 7 Sol# 4 1 5. 3
Re# 3 1 1. 3 La
440
Mi
3 2 9. 6 La#
466 . 2
Fa
Si
349 . 2
3 93 . 9

The notes are generated in the loudspeaker by programming the

channel 2 of the 1 8253 timer circuit with an adequate d ivid ing value,
knowing that at the CLK 2 input we have a frequency of 1 , 1 93 1 8 M Hz . The
val ues can be computed l i ke this:
k note=1, 1 93 1 8 MHz I fnote
For example for the note La, kLa=27 1 1 .
The control of the signal on the loudspeaker can be made through BO
and 8 1 bits of the 6 1 h add ress port. The channels connecting schematic of
the 1 8253 timer circuit is presented in fig .2.5.
a . Analyze and execute the fol lowing "DOREMI" program
b. Transpose the program for other octaves
c. Generate a melody.
; * - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * ;
*
*.
DOREM I
* - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *
; De f ine s CODE segment
code s egment para 'CODE'
I

org l O Oh
a s s ume c s: code ,

ds : c ode,

; s t a r t s at l O Oh a f t e r P S P
e s : c ode , s s : code

sound proc near

; - - me s s age - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ; s t r i ng print ing func t i on
mov ah , 9
mov dx , of f s e t me s _ i n
; me s s age addre ss_ o ffse t ; DOS int e r rupt
int
2lh
; - - redire c t s the t imer rout ine to the u s e r rou t i ne - - mo v ax , 3 5)- c h
; rea ds timer inte rrupt addre s s i n E S : BX
int
2 lh
;DOS int errupt
; s ave s old interrupt
o ff s e t addr e s s
m ov t ime_o l d , bx
; and s egment addre s s
mov t ime_o l d+ 2 , e s
mov dx , o f f s e t s ound_ti
; new routine o f f s e t addre s s

25

The Timer Circuit

; l oads address in TVI f rom DS : DX
mov ax , 2 5 l ch
; DOS interrupt
int
2 1h
; - - sounds generat ion - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ; st a r t w i t h Do f rom the IV o c t ave
xor bl , b l
mov d l , 9
; no t e l ength in t ime 0 . 5 se c ( 9 * 1 / 1 8 s= 0 . 5 )
; note genera t i on
next one : c a l l p l ay_note
; next not e
inc b l
; al l notes have been gene rated?
cmp b l , 1 2
- - > gene rate next note
j ne next one
; i f Not
; - - t imer old int e rrupt - - - - - - - - - - - - - ; S aves DS
mov cx , ds
mov ax , 2 5 1 ch
; func t i on number f o r ve c t o r recovery in TVI
l ds dx , dword p t r t ime_o l d ; l oads o l d address in DS : DX
; DOS inte rrupt
int 2 1 h
; DS recover
mov ds , cx
; - - end message - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - mov ah , 9
mov dx , o f fse t mes out
2 1h
int
; program end
mov ax , 4 C O O h
2 1h
int
sound endp
=

; = =ma in p rogram da t a
mes_in db O dh , O ah , " Generat ing notes f rom I V o c t ave , O dh , O ah , " $ "
mes out
db O dh , O ah , 11 End 11 , 0 dh , O ah , 11 $ 11
; - - PLAY_NOTE : Generat i ng not e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BL = note numb e r f rom Do , o c t ave IV
; - - Input
DL = note
l ength in 1 / 1 8 second mu l t ip l es
;-Output
- Reg i s t e rs : AX , ex , ES and FLAGS are mod i f i e d
i = = = = = = = == = = = = = = = ===== = = = = =

play_not e p r o c near
push dx
push bx
mov al , O b 6 h
out
xor
shl
mov
out
mov
out
in
or
mov
mov
out
play : cmp
j ne

; saves DX and BX on stack

; prepares t h e sound generat i on

; ( C2 , LSB/MSB , M3 , b inary )
4 3 h , al
; l oads the value in t ime r cont r o l reg ist e r
bh , bh
; BH= O , o f fset for note
addressing i n the t ab l e
bx , 1
; doubles the value ( t he t ab l e is f o r words )
ax , [note +bx]
; reads note va lue
4 2h , al
; loads the l ow byt e i n t imer reg i s t e r ( C2 )
a l , ah
42h, al
; l oads high byt e i n t ime r reg i st e r ( C2 )
; reads the l oudspeaker cont rol b i ts
al , 6 1 h
; B i t s B O , B l ( 6 1 h ) act ivate the l oudspeaker
al , l lb
; Note must be gene rated
end_s , 1
; S aves the note l ength
nr_s , dl
; Act ivates the loudspeaker
6 1h , a l
end_s , O
p l ay

; No t e done ?
; No
> wa i t
- -

26

The Timer Circuit

in

a l , 6 lh

; reads l oudspeake r

and

a l , l l l l l l O Ob

; S e t s to O b i t s B O , B l

out

61 h , a l

pop

bx

; D i s ab l e s l oudspeaker
; Recove rs BX and DX f rom s t ack

dx

pop
ret

cont ro l b i t s

; back in the program

pl ay_not e endp
; - - new u s e r int e r rupt ( l Ch ) of the t imer - - - - - - ; ca l l e d 1 8 t ime s p e r s e cond
proc f a r

sound_t i

dee

c s : nr s

j ne

end st

; De c rement s coun t e r
; i f # 0 j ump , = 0 done

mov

c s : end_s , O

; pa s s e d note l eng th
; back

end s t : i re t
sound ti
;

==

endp

var i ab l e s

t ime_o l d

nr s db

dw

(?)

db

end s
not e

= =

f o r rout ines = = = = = = = = = = = =
( ? ) , ( ? ) ; o l d addre s s f o r t ime r i n t e r rup t
; rema i n i ng l ength f o r a not e , i n s e c ond
; l / 1 8 mu l t ip l e s
( ? ) ; i nd i c a t e s i f the not e was gene r a t e d

dw 4 5 6 0 , 4 3 0 4 , 4 0 6 3 , 3 8 3 4

; di v i d i ng va lues f o r the not e s

dw 3 61 9 , 3 41 6 , 3 2 2 4 , 3 0 4 3

; f rom o c t ave IV :

dw 2 8 7 3 , 2 711 , 2 5 5 9, 2 4 1 5

; Fa , S o l , S o l # , La , La# , S i

End

Do , Do# , Re , Re # , M i

= = = = = = = = = == = = = = ===================== = = = = = = = = = = = = = = =

code ends

; CODE segment end

end sound

; p rogram end

*-------------------------------------------------------------*
I

2.5.2 O n a n I SA expansion slot the schematic from figure 2.7 is .

con nected to the P C . The timer channels are used as i n figure 2.6.
SYSCLK/ 1 6

'1 '

CLKO

GATEO

OUT !

OUTO

'1 '

CLK2

GATE2

D
CLK

SET

r--+-''\/\l\--o+5
Fig . 2 . 6 The timer channe ls connection
27

OUT2

The Timer Circuit

a . To what address i s the 18253 circuit connected?

b . Starti ng from the SYSCLK = 1 2M Hz frequency, generate a 1 Hz signal
on the OUT1 output.
c. Make the necessary connections and program the circuit to obtain an
externally commandeq pulse of 0 , 5 sec. at the OUT1 output.
d. Transpose the "DORE M l .ASM" program for the expansion board
loudspeaker.
17:0 ,.,
'1 .,,r
'\

15
14
13
12 .
11
10
9
7

t-=--U...

3
6

11

Al

E!1....
lll!B
RD

AOW
AOR

07
D6
D5
D4
D3
D2
01
00

\ ' \

O IJT'2
G2
CLK2
O UT1
G1
CLK1
O UTIJ
GO
CLl<D

SYS CLK/16

8253

Fig . 2 . 7 The e l ectrical schematic of the app l ication

28

The RTC and the CMOS Memory

3 . TH E REAL TI M E C LO C K AN D TH E C M O S M E M O RY
3.1

General i nformation

Starting with I B M PC/AT computers, a C MOS memory has been

introd uced , placed on the main board , with the purpose to store some
information concerning the system configuration even after it had been shut
down . The information is used for the system i nitialization , th us allowing a
flexible configuration , different from one computer to another (different RAM
memory, d ifferent floppy d isc units and hardware-disc types, etc.). CMOS
memory stores also time and alarm i nformation , refreshed by the RTC
(Real Time Clock) and a few bytes used to keep information concerning the
system d iagnosis d u ring booting.
The first type used the MC 1 468 1 8 circuit, mounted on the main
board , having a capacity of 64 bytes, supplied from a battery to store the
CMOS memory contents even after the computer had been shut down . MC
1468 1 8 incorporated also the Real Time Clock that has its own oscillator.
Different peripheral ci rcuits producers have realized their own constructive
forms for the CMOS memory, some of them allowing 1 28 bytes memory.
CMOS memory add ressing is the same for any C MOS memory type and
for most of the bytes the significance remains the same.

The three categories of i nformation stored in the CMOS memory are:

I nformation concerning the system configuration (ex: available RAM
memory, types of flexible disk u n its, type and specific featu res of the
fixed d isk unit).
I nformation provided by the Real Time Clock, concerning the time
(seconds, minutes, hours, month year) and the alarm (th e alarm is a
facility of the RTC which allows a hardware interrupt generation I RQ8
(type vector 70H ) each time the current time becomes the same as the
time the alarm is set).
System d iagnosis i nformation , provided during the booting phase .
The shutdown byte , used in the PC-AT restart mec anism, where it
remains after a CPU reset, to exit from the protected mode.

An important thing is that the real time clock is refreshed independently

by the central u n it, while the system clock used by B I OS is refreshed ( 1 8.2
times per second ) at the timer generated i nterrupts on the 0 timer channel
to I RQO.
29

The R TC and the CMOS Memory

3.2 MC 1 468 1 8 ci rcuit

3.2.1 Internal Block Diagram

MC146818 has 4 logical blocks :
The i nterface with the bus - contains:
-demultiplexers for address and data signals demultiplexing
-reset logic
-read-write selection logic
The Real Time Clock comprises: a quartz sq uare wave generator and
a programmable d ivider mounted with a prescaler register and a meter.
Th!3 clock is i ncremented by the programmable divider output and its
role is to refresh the registers : seconds, minutes, hours, weekday,
month day, month , year and to compare them with the alarm registers .
If the values are equivalent, the I RQ line will be activated . All the
registers a re in the CMOS memory and they a re available for
reading/writin g .
Power management block ensures the switching from the supplying
source to the battery when the sou rce is interrupting and signals this to
the system through the PS line.
CMOS memory is a low consumption memory, with a capacity of 64
bytes, accessible through the bus-interfacing block.
<

AD O - AD 7 .
AS

Bus

DS

InterfacE

R /WR
RST

.
.

- -

D O - D7

DO - D7

'"

A O - A7

'

/CS

RTC

onur

DO -D7
,. n _ ,. .,

CMOS
Memory

AO - A7

I RQ

CKF S
PS

P ower
management

I- -

Addre s s Data

Bus

Fig . 3 . 1

The

MC 1 4 6 8 1 8

30

Bus

block diagram

The R TC and the CMOS Memory

3.2.2

Circuit pin assignment

The circuit is encapsulated in a 24-pin package, whose significations

are:
OSCI
OSC2

ADO
ADI
AD2
AD3
AD4
ADS
AD6
AD7

RESET
IRQ
AS
OS
PS
CKFS

SQW

cs

CKOUT

RiW

23
21

Fig . 3 . 2 RTC pin as signment

AD0-7 - multiplexed address and data signals

/CS - Chip Select
R/W - Read/Write
AS
- Address Strobe
- Data Strobe
DS
PS
- Power Sense, u sed to control VRT (Valid RAM and Time) bit from
register D, who is 0 when PS is low
CKFS - Clock out Frequency Select, used for CKOUT frequency selection :
if CKFS is con nected to VDD, CKOUT = OSC 1 , if CKFS is connected to
GND, CKOUT = OSC 1 I 4
CKOUT - output signal of time base frequency d ivided by 1 or 4
/I RQ - Interrupt Request (IRQ8 in PC), active as long as the i nterrupt
generating bit is active and the interrupt validating bit is set
VCC - +SV
GND - ground
OSC 1 -2 - quartz inputs (4. 1 94304M Hz/1 .048576M Hz/32. 768KHz)
SOW - Square signal output, obtained by d ividing the OCS 1 signal; the
1 5 frequencies are obtained depending on the bits 83 BO from register A
RESET - does not affect the clock, the calendar or the RAM; at th e system
start it maintains low for a while, its effect being the P I E , AIE, U I E , UF,
I RQF, PF bits reset
-

31

The RTC and the CMOS Memory

3.3 The C M OS memory content and its accessi ng mode

The CMOS memory locations a re used to store the information
presented i n the table below, the rest of it being available to the user. I n
case of using this circuit in a PC, the locations have the destination
presented in the appendix 2.
Addr CMOS memory content used by the RTC
o oh
O lh
0 2h
03h
04h
O Sh
06h
07h
08h
0 9h
O ah
Obh
Och
O dh

Current s e cond for RTC *

Al arm s e cond f o r *
Current minut e *
A l a rm minut e *
Current hour*
Al arm hour*
Day f rom week ( l = Sunday ) *
Day f rom month*
Current month*
Curren t ye ar ( the last t wo di g i t s ( supe r i o r
d i g i t s ) are at addre s s 3 2 h ) *
S t atus reg i s t er A of RTC
S t atus reg i s t er B of RTC
S t atus reg i s t e r C of RTC
( Read i n t e r rupt s t a tus reg i s t e r )
S t atus reg i s t e r D of RTC ( D 7 = 1 supp l i e d
c i rcu i t , D=O b a t t e ry empty

* T h e content o f 00h-09h locations are read i n hex.

Exa m p l e : If the location 02h contains 1 2 h then cu rrent m i n ute i s 1 2 .

Table 3 . 1 CMOS memory addresses used by the RTC

Register A {R/W}
7

3-0

6-4

Upda t e in p r og re s s

DV2 - DVO

( UI P )

Rate s e l e c t o r f o r SQW :

RS 3 - RS O

U I P - (U pdate I n Progress) is a status bit (flag) that can be controlled by the

progra m . When this flag is " 1'' , it indicates an update cycle in progress or starting
soon .
DV2 - DVO
allow different conditions establish ment, th rough a progra m ,
according t o t h e quartz type that will b e used
RS3
RSO
bits for rate selection , allows selecting one of the 15 dividing
possibilities of the 22 level divider or the divider output disabling
-

Register B {R/W}
I
S ET

7
SET

6
PIE

5
AIE

4
UIE

3
SQWE

= O time update going on ordinary

32

DM

24 / 1 2

DSE

The RTC and the CMOS Memory

= 1 one can i n itial ize the time a n d calendar
PIE ( Period i c I nterrupt Enable} = 1 enables the period ic i nterru pt, th roug h flag PF
AI E (Ala rm I nterrupt Enable} = 1 ena bles i nterrupt through a l a rm flag AF
UIE ( U pdate-ended I n terrupt Enable) = 1 enables interrupt through flag U F
SQWE (Square Wave Enable) = 1 activates rectangular s i g n a l to SQW output, with
a freq uency selected through RS3 - RSO
OM ( Data Mode) = 1 i n d i cates ti me and calendar binary u pdati n g , else BCD
updati n g
24/1 2 = 1 activates 24h/day counting mode
DSE ( Dayl i g ht Savings Enable) = 1 activates automatic s u m mer/wi nter hour
passing

Register C (Read only) is used by the I NT70 h i nterrupt handler, to

determine i n what situation it was generated
-

IRQ F

6
PF

AF

UF

2
0

1
0

0
0

I RQ F - i nterru pt req u est flag is active ("1 ) if at least one of the followi n g cond itions
"

is tru e : PF = P I E = 1 ; UF = U I E = 1 ; when thi s bit is " 1 " , / I RQ pin is low . The reg i ster
bits reset at the reg i ster read i n g or when the signal /RESET i s active
PF - period ic interrupt flag is set on " 1 " when a certa i n front is detected at the
d ivider cha n n e l . Its periodicity is commanded by the RS3 - RSO b its .
AF - alarm i nterrupt flag activates if cu rrent ti me equals alarm ti me and generates
an i nterru pt if flag A I E = 1
U F - U pd ate - ended i nterru pt flag , is activated after every u pd ati ng cycle. If U I E =
1 , the U F activation sets bit I RQF and activates i nterru pt signal /I RQ .

Register D (Read only)

7
VRT

6
0

5
0

4
0

2
0

1
0

0
0

VRT - Val i d RAM a n d Time i n d i cates RAM content status depe n d i n g on the
tension level o n pin PS. VRT = O i n d i cates that the level on PS i s low, so the
battery is empty.

Reading and writing CMOS memory locations

To read the content of a CMOS memory location one must follow the
next steps:

Send to port ?Oh the address of the location that wil l be read

Read the location value from port 7 1 h

33

The R TC and the CMOS Memory

Example:
mov a l , addr e s s
out 7 0 h
al
in a l , 7 1h
,

To write a location of the CMOS memory one fol lows the next steps:
Send to port ?Oh the address of the location
Write the new value to port 7 1 h

Example:
mov a l , address
out ? O h

al

mov a l , new_value
out 7 l h
al
,

System services for CMOS - RTC data access

3.4

The operating system allows user access to the system clock (used
by B IOS) and to the real time clock (which updates independently) through
B I OS services I NT 1 Ah . For data reading from CMOS - RTC , the operating
system provides the fol lowing services ( I NT 1 Ah ) :
Reads the clock from CMOS -RTC
CH = hour in BCD (EX: CX= 1 1 49 H = 1 1 :49)
CL = minutes in BCD
D H = seconds in BCD
CY = 1 when RTC is locked
AH=03h
Time setting in CMOS-RTC
C H , CL = hours, min utes in BCD
Input:
D H = seconds i n BCD
D L = 1 sets automatic change winter/summer time
AH=04h
Reads date from CMOS
Output:
C H = century in BCD (Ex: CX= 1 987h= 1 987)
CL = year i n BCD
D H = month i n BCD (Ex: DX=03 1 2h=March)
D L = day in BCD
C F = CY = 1 if RTC is locked
AH=OSh
Sets date in CMOS
Input:
C H , CL = century, year in BCD
DH, DL = month , day i n BCD
AH=06h
Sets the RTC alarm . At the set time, the user i nterrupt routine is
called from the address corresponding to INT 4Ah . It may be only one
alarm activated .

AH=02H

Output:

34

The R TC and the CMOS Memory

Input:

C H , CL = hours, minutes in BCD

DH = seconds i n BCD
CF = CY = 1 RTC is locked or an alarm is active

Output:
AH=07h

Resets the RTC alarm

The system configuration can be read with INT 1 1 h . It returns to

the following bits configu ration.
01 5 - 014

Para l l e l Port

00
01

013

11

in s t a l l e d

- S e r i a l p r i n t e r i n s t a l l ed

1 - Game adap t o r ins t a l l ed

Dll -09

Port RS2 3 2

DB

07 - 0 6

F l oppy d i sk driver

D3 -D2

10

012

D S - 04

Not

AX

000

Not

001 . . 111

1. ..... 7 port s

i n s t a l l ed
instal led

- DMA p r e s ent

V i de o Mode

RAM memory s i z e

00

01

10

11

00

Re s e rved

01

4 0 c o l o r c o lumns

10

8 0 c o l o r c o l umns

11

Monochrome TTL

00

01

1 6k

10

32k

11

64k+

Dl

- Mathema t i c coproce s s or ins t a l l e d

DO

- D i s k un i t

ins t a l l e d

Table 3 . 2 System configuration provided by

INTllh

in

AX

This i nformation can also be found i n the system memory at the

address 0 : 04 1 0 h .
3 . 5 Application and exercise

a. Study and execute the following application, written in C language,

application that d isplays information about date and hour, read from the
CM O S memory.
35

The R TC and the CMOS Memory

#inc l ude < dos . h >
#in c l ude < S t diO . h >
# inc l ude < c on i o . h >
typede f uns i gned char byte ;
Ox7 0
# d e f ine Rt cAdr Port
Ox7 1
#def ine Rt cDa t a Po r t
0
# de f ine S e c onds
2
# de f i ne M inut e s
4
# d e f ine Hours
6
# de f ine Dayl
7
# de f ine D a y
8
# de f ine Month
9
# de f ine An
10
# d e f ine Reg A
11
#de f ine RegB
12
# de f ine RegC
13
# de f ine RegD
14
# de f ine Diagnose
15
# de f ine Century
/ / Func t i on that reads a l o c a t i on f rom CMOS
byt e CmosRead ( by t e Address )

byt e retur ;
asm {
mov a l ,Address
out Rt cA d rPort , a l
in a l ,Rt cDa t aPort
mov retur,Al

};

return

( retur ) ;

/ / Fun c t ion t h a t wr i t e s

to a l o c a t i on f rom

CMOS

vo id CmosWr i t e ( by t e Address,byte Content )

asm {
mov
out
mov
out

};

a l ,Address
Rt cAdrPort,a l
a l Conten t
Rt cDataPort,al
,

vo i d ma i n ( vo i d )

whil e ( b i oskey ( l ) = = O )

c l rscr ( ) ;
i f ( ! ( CmosRead ( D i agnose ) & l 2 8 ) )
36

/ / verifies bat t e ry status

The RTC and the CMOS Memory

/ / reads
p r i nt f ( " RTC

RTC

emp l oy mode

i s u s ed

/ / r e a d s hour
p r i n t f ( " The

t i me

in

f rom r eg i s t e r B

%d hour s mode \ n " , ( CmosRead ( RegB ) & O x 0 2 ) * 6 + 1 2 ) ;

i s : %x . % 0 2 x . % 0 2 x \ n " , Cmo sRead ( Hour ) , Cmo s R e a d ( M i nut e ) ,

Cmo s Re a d ( S e conds ) ) ;
/ / reads

da t e

p r i n t f ( " Da t e : % x . % 0 2 x . 2 %x % 0 2 x \ n \ n \ n " , Cmo sRead ( Day ) , Cmo s R e a d ( Month ) ,

Cmo s Re a d ( Century ) , Cmo s R e a d ( Ye a r ) ) ;

else
p r i nt f ( " At t ent i on !

};

RTC B a t t e ry emp t y \ n " ) ;

de l ay ( S O O ) ;

b . Modify this program s o a s to read from CMOS the type a n d n umber of

floppies and hard d isks of the system .
c . Modify th is program s o as to read from C M O S the type o f video card .
d . Rewrite the application using system services.

37

; .

The Programmable Interrupt Controller

4. TH E P ROG RAM MAB LE INTERRU PT CONTROLLER

4. 1 Interrupts i n data processing

Most of the computer components need to exchange i nformation with

the microprocessor and wait for its attention when they require a data
transfer. The microprocessor supervises the data transfer between different
components in order to prevent the data losses . The microprocessor can
supervise the data transfer in two different ways:

Poll i ng the microprocessor tests the devices one by one and serves
the one that requires a special attention . Polling can be used in the
case of some devices or in microprocessor systems but not in PCs,
because it is too slow. Many processing cycles can be lost, because
most of the times the devices response is negative. In add ition, the
devices need data transfer or attention with d ifferent freq uencies (e.g .
the mouse needs much less attention than a hard-d isk when i t is
activated for data transfer).

Interrupt- i s another way of approaching the d ata transfer and it

consists in letting the devices ask for attention when they need it, while
the 'microprocessor can take care of other d uties, wasting less time than
i n polling mode. When an interrupt is sensed , the microprocessor quits
the progra m run and properly serves the device that put it off.
The microprocessors generally have only one pin for the i nterrupt req uests,
but there can be more exterior interrupt sources . When the system needs
more interrupts , an i nterrupt controller carrying out certai n d uties is placed
between the interrupt sources and the microprocessor. Some of the duties
carried out by the i nterrupt controller are:

Multiplexi ng the interrupts from different sources to the microprocessor

pin
Solving the priority problems for simultaneous i nterrupts
The generation of an i nterrupt vector which indicates the address of the
program that handles the interrupt

The above tasks are solved differently for some microprocessors (e. g .
Z80). The i nterrupt system is distributed to each circuit from t h e Z80 family
and the i nterrupt priorities are solved depending on the circuit position on a
priority chai n called "daisy-chain". The circuits also provide the
corresponding i nterrupt vector. The PIO Z80 circuit from figure 4 . 1 has
39

The Programmable Interrupt Controller

maxi mum priority, being the first component on the priority chain con nected
through the I E I ( I nterru pt Enable I nput) and I EO ( I nterrupt Enable Output)
signals. The P I C (Programmable I nterrupt Controller) 1 8259A circuit is
used in PC.
'I'

IE I
PIO

CTC

Z80

INT

IEO

IEO 1---- IE I

IEO 1---- IE I

Z80

INT

INT
INT

(Z80)

Fig . 4 . 1 The priority chain ( ' Daisy- Chain ' )

4.2 The 8259A overview

The 1 8259A circuit is made in N MOS technology i n a 28 - pin capsule.
This circuit is compatible with the 1 8259 controller (used with 1 8080) and
due to its additional fu nctions it can be used i n the 1 80x86 microprocessor
systems. The circuit allows interru pt req uests active on the increasing edge
or on "high" level and it can be used in the system by itself, managing 8
interrupt levels, or more cascaded circu its can be used , to manage u p to 64
i nterrupt levels.
Based on an i nterrupt- handling rule that can be programmed , the controller
finds out if there is at least one interrupt request and sets the INT signal on
high leve l . If the microprocessor accepts the i nterru pt, it generates an
i nterru pt accepting sequence of more /I NTA run cycles (2 i n 18088/18086
mode and 3 in 1 8080 mode) to recognize the i nterrupt. During these cycles,
the controller puts on the data bus the information required by the
microprocessor for determining and executing the routine associated to the
accepted interrupt leve l .

4.2. 1 . T h e 18259A control ler architectu re

The P I C block d iagram has the fol lowi ng functional blocks :
I nterrupt Request Register {IRR) memorizes all the i nterrupt requests
coming from the outside .
I n Service Register {ISR) -memorizes i n service interrupt req uests at a
certai n time. After an i nterrupt has been served , the corresponding bit from
I S R is i nvalidated . The reset can be done automatically or programmed .
Priority Resolver {PR)
compares the I RR register content with ISR
register content and determines the i nterrupt request with g reater priority
tha n the i nterrupt being served , in which case it generates a new i nterrupt
request by setting the corresponding bit in I S R during /I NTA fi rst cycle .
-

40

The Programmable Interrupt Controller

Interrupt Mask Register (IMR) allows the invalidation of some interrupt

levels by settin g the corresponding bits in the register.
Data Bidirectional Amplifier - has 'three-state' bidirectional lines,
con necting the controller interface to the data bus. The control words,
status information and vector type are transferred through the amplifier.
Cascading Logic
The 1 8259A controllers can be cascaded to i ncrease the n umber of
interrupts; one controller is the master and the rest of them slave
(maximum 8 slave circuits). The slave controllers generate interrupt
requests on the IRi master input through the slave controller con nected to
that input. The CASO-CAS2 signals of the master controller are output
signals throug h which the slave controllers receive a code from the master
circuit. The slave circuit which recognizes the cod e (the prioritary one) wil l
transmit, during /INTA cycles , the data for the accepted interrupt request,
so that the routine can be determined and executed .
Read I Write Logic
The processor sees the controller as an input-output port set. Through AO ,
/WR, /CS and D O - D7 signals, the processor programs the controller using
command word s and through AO , /RD , /CS and DO - D7 signals it reads the
status registers .
-

/ I'NTA
Data

Control Logic

idi rec t i ona

bu f f er
/RD
/WR
AO
!CS
CASO
CASI
CAS2

/SP//EN

I'NT

I'NTERNAL
.-------. BUS
Read/Write
Logic

Cascading
Logic

IMR

Fig . 4 . 2 I 8 2 5 9A PIC internal block diagram

41

The Programmable Interrupt Controller

. 4.2.2 I nternal registers

The address for the 1 8259A i nterrupt controller programming is 20H

(for XT-PC) and the associated port addresses are listed bellow:
Port

I /O

2 0H
2 1H
2 0H
2 0H
2 0H
2 1H

I
I
0
0
0
0

S igni f icance
Re ad IRR , I'sR
Re ad I MR
Wr i t e OCW2 i f D4 ,
Wr i t e OCW3 if D4 =
Wr i t e I CWl , i f D4
Wr i t e OCWl , I CW2 ,

D3
00
1
= 1
I CW3 , I CW4
=

Table 4 . 1 Port addresses for PIC

The address for the slave PLC_.!s Q_OH (in AT-PC)

Interrupt Request Register (IRR) : {in al, 20H)
7

IRQ7

I RQi

=
=

IRQ6

IRQS

IRQ4

IRQ3

IRQ2

O there was no interru pt req u est on l i n e 'i'

IRQl

IRQO

Wl

WO

1 i n te rru pt req uest on l i ne 'i'

I n Service Register (ISR) : {in al, 20H)

6

W2

= 0 there is no i nterru pt
= 1 there is a n interru pt

W2 , W 1 , WO conta i n the binary code of the most pribritary level which

req uested i nterru pt

Interrupt Mask Register (IMR) : { i al, 2 H)

Mi

1Kl

=0
= 1

M6

MS

M4

M3

M2

Ml

MO

I R Q 1 interru pt l i n e is not masked

I RQ 1 l i n e is masked

W>oJY2\,.Q 'S

Priority Resolver {PR)

The user does not have access to this register. The register
compares the current i nterrupt priority level with the one from ISR.

42

The Programmable Interrupt Controller

4.2.3 18259A circuit pins assignment

Name
/CS
/WR

I /O

Pin

/RD

AO

27

I/O

4
11

I/O

12 14

D7
DO
CASO CAS2
-

/SP/ /EN

I/O

16

INT

17

IRO - IR7

18 25

/ INTA

26

Function
C i rcu i t s e l e c t i on
Ac t ive on ' 0 ' l eve l when c ommand words are
rece ived f rom the m i c ropro c e s s o r
Act ive on ' 0 ' l eve l when reading I 8 2 5 9A
c i rcu i t s t atus
AO together w i t h / CS , / RD , / WR de t e rmine
command/ s t at u s
t he
word
wh i c h
t he
m i c roproc e s sor wr i t e s / reads i n / f rom I 8 2 5 9A
c i rcu i t .
Norma l ly
is
conne c t e d
to
0
addr e s s l ine (Al f o r I 8 0 8 6 )
B i di re c t i onal
dat a
l in e s
for
cont ro l ,
s t atus inf orma t i on t r an s f e r and inte rrup t
ve c t o r t rans f e r .
For c a s cad ing
S l ave Program/ Enab l e Bu f f e r i s a doub l e
func t i ona l i ty p i n .
I n buf f e red mode
is
used a s a bus tran s f e r cont r o l s i gna l and
in unbu f f ered mode , S P = l f o r MASTER and
S P = O for SLAVE
output
INTe rrup t
c onne c t e d
to
INT
proc e s sor input ; t hrough i t , the interrupt
reque s t are t ransmi t t ed
a s ynchronous i nput s
( In t e rrup t Reque s t )
c onne c t e d to t he o f f - l ine c i rcu i t s wh i ch
t he
to
proc e s sor ,
inte rrup t s
gene rat e
u s i ng P I C I 8 2 5 9A
( INTe rrup t Acknow l e dge ) - u s e d f o r inte rrupt
acknowledge and int errup t ve c t o r reading
-

Table 4 . 2 Pins functions

IRO
IR1
IR2
IR3
I R4
IR5
IR6
IR7

CASO
CA51
CAS2

Fig . 4 . 3 Circui t pin assignment

43

The Programmable Interrupt Controller

4.3 PIC P rogramming

The circuit has only two ports for writing or reading program status, so
one must follow a certain order in sending the command words to t he P I C .
There are two types of words for working with 18259A:
- I n itialization words I CW 1 , ICW2 , I CW3, ICW4
- Operation words OCW1 , OCW2, and OCW3
The words sending order is presented in the d iagram from figure 4.4.
The I CW and OCW words structure is presented below:
ICW1 (OUT 20H, AL)
6

I LTIM I

SNGL

ICW4

The empty positions have significance in 8080 mode.

= O ICW4 is not necessary
I CW4
= 1 ICW4 is necessa ry
= O cascaded mode
SNGL
= 1 single mode (only one 8259A circuit)
= O I RQ7 interrupt active on edge
LTI M
= 1 interru pts active on level

ICW2 (OUT 2 1 H , AL)

T7

T6

TS

T4

T3

Ti are bits 3 to 7 from the code sent in the second /I NTA cycle. The
n u m ber (type) of the interrupt vector for single mode is 8 ( I RQO), 9
( I RQ 1 } , . . F ( I RQ7).
.

ICW3 (OUT 21 H , Al-) : for master

S7

S6

SS

S4

S3

S2

Sl

so

IDl

IDO

Si = 1 there is a slave connected t o l i n e ' i '

ICW3 (OUT A1 H , AL) : for slave

7

ID2

1 02 , 1 0 1 , 100: the identification code of the slave PIC (corresponds to

I RQ line n umber from the master where it is connected ). It is com pa red
with the code emitted on CAS0 . . . 2 by the master.

ICW4 (OUT 21 H, AL)

7

SFNM

BUF

PROC = O 8080 mode, = 1 8086 mode

AEOI = auto EOI , = 0 manual EOI
44

M/ S

AEOI

PROC

The Programmable Interrupt Controller

BUF M/S
0

SIGNIFICANCE

l
l

No externa l da t a buf f e r
Ext e rnal dat a buf fer ; s l ave P I C

Ext e rna l

da t a

buf f e r ; ma s t e r P I C

SNFM (Special Fully Nested Mode)

= 0 Priority working mode. Only the prioritary interrupts are accepted (the
interrupts with the same or less priority are ignored due to ISR)
= 1 S pecial mode for priorities (only for master). Other interrupts are
accepted, regardless their priority; an interrupt with the same priority as the
one being served will not be accepted

OCW1 (OUT 21 H, AL) : for the i nterrupt mask

M7

M6

MS

M4

M3

M2

EOI

Ml

MO

Mi = 0 u nmasked level
= 1 masked level

OCW2 (OUT 20H , AL)

7

SL

LO

Ll

L2

R (Rotate) = 1 : until the. next OCW2 . the. last served i nterru pt gets 8
lowest priority
SL (Specific Level ) = 1 : specific EOI is used . See the table below for
priority mode selection.
EOI (End of I nterrupt) = 1 : P I C is annou nced at the end of the served
interrupt procedu re
L2 , L 1 , LO: contain the binary code of the served priority level

SL

EOI

0
1

0
1

1
- 0
0

0
1

Significance
Rot a t e in AEOI mode - C l e a r
Non - spe c i f i c EOI
No e f f e c t
Spec i f i c EOI
Rot a t e in AEO I mode - S e t
Rot a t e t o non - spec i f i c EOI
Set s p r i o r i ty
Rot a t e t o spec i f i c AEO I

0
1

OCW3 (OUT 20H ,AL) : masked mode, register read selection

7

ESMM

SMM

PR

RI S

ESMM ( Enable Special Mask Mode) = 1 : special mask m ode validation

SMM (Special Mask Mode) = 1 : special mask mode
RP, RIS: select reg isters that will be read in the next instructio n
45

The Programmable Interrupt Controller

P = O polling mode {pseudo-interrupt mode: I NT is not validated to the

microprocessor. IRR register is swept through the program )
= 1 normal mode

ES MM S MM

Signi ficance

RR

RIS

Signi ficance

No e f f e c t

IMR s e l e c t i on

Spec i a l mask
reset
Spec i a l mas k
s e t t ing

I RR s e l e c t i on

I S R s e l e c t i on

ICWl

ICW2
NO

NO

ICW4
Ready for
interrupts

(OCW)

Fig . 4 . 4 The flow chart for PIC programm i ng

4.4

18259A controller modes

Full y Nested Mode

This mode is instal led after the initialization if another mode is not
programmed . The seventh interrupt level has the lowest priority and zero
level becomes the most important. During interrupt acknowledge cycle , the
most important priority request is determined and the vector associated to
the interrupt is placed on the data bus. Meanwhile the corresponding bit
from I S R is set. In EOI mode, this bit is set to 1 and it needs an explicit
46

The Programmable Interrupt Controller

command for erasing it before interrupt service routine ends. I n AEOI mode
the bit stays in 1 until the last i nterrupt acknowledge /I NTA cycle ends. As
long as the I S R bit is set, any other interrupt requests are ignored , except
the more prioritary ones that are served (if the microprocessor is set to
accept the interrupt requests).
EOI mode
The I S R bit corresponding to the served i nterru pt i s automatically
reset i n AEO I mode (without using a special command) or using a
command word activated before EOI mode interrupts serving routi ne ends.
In cascaded mode, the served interrupt corresponding bit has to be erased
from both master and slave .
AEOI mode
Automatic End of I nterrupt - is activated when AEOI bit from I CW4 is
1 and it is equ ivalent with a non-specific EOI command activated when the
interrupt recognizing cycle ends (the third for 1 8080 and the second for
18086 mode).
Automatic (non-specific) priority rotation
There are cases when an off-line device after being served becomes
the last one in the priority list and it wil l not be served u ntil the other seven
off-line devices from the priority list wil l be served properly.
Specific Priority Rotation
The user can dynamically change the priority order from the program.
A low priority level is defi ned and the other levels will be modified according
to this one.
I nterrupt masking
Each i nterrupt request i nput can be masked using I M R, which is
programmed with OCW.
Special mask mode
In this mode the interrupt req uests with the same priority, as the
served i nterrupt, are i nval idated but the more prioritary or less prioritary
than the served one a re accepted . This mode is programmed with ESMM =
1 and S M M = 1 i n OCW3 .
Polling mode
In this mode, the i nterrupt system is invalidated at the microprocessor
level. The i nterrupt requests are scanned using a polling command . Polling
mode is set with P = 1 in OCW3. The 18259A controller handles the fi rst
reading cycle (/RD and /CS) as the first cycle from the i nterru pt accepting
sequence . The most prioritary request bit is set i n ISR.
47

The Programmable Interrupt Controller

Specific F u l ly Nested Mode

This mode is necessary in the systems with several cascaded 18259A
controllers and it is programmed from the master. (Th rough S F N M = 1 in
ICW4 ). This mode is similar to Fully Nested Mode with some exceptions.
When a n interrupt request coming from a slave is served , the master circuit
does not i nvalidate this slave. In this way the most prioritary interrupt
requests coming form the same slave are properly served . I n the normal
mode ( F N M ) , when an i nterrupt request coming from a slave is served , the
corresponding master input is invalidated and even the more prioritary
i nterrupt requests than the one being served wi ll not be accepted .
Buffered mode
When the 1 8259A controller is cascaded in the unbuffered mode, the
/S P//EN signal is used as an i nput signal controlling the type (master or
slave). There are system configurations that need communication between
the 18259A controller and the bus, using a bidirectional amplifier (buffer) . I n
this case the /S P//EN signal i s used a s an output signal to establish the
bidirectional ampl ifier transfer direction :
/EN = 0 transfer from the controller to the microprocessor
/EN = 1 transfer from the microprocessor to the controller
Because of th i s , i n the buffered mode a prog ra m chooses the contro l l e r
type . The thi rd bit from ICW4 programs the buffered mode and the second
bit programs the master/slave type .
Cascaded Mode
One 1 8259A master controller can be i nterconnected with maxi mum 8
slave controllers to implement an i nterrupt system with 64 priority levels.
The master controls the slave controllers through CASO . . . CAS2
cascading lines. The slaves I NT outputs, in cascaded configuration, are
/EN

17

INT

CASO
C A S1
CAS2

CASO
CAS1
CAS2

I RO
IR1
IR2
IR3
IR4
IRS
IR6
IR7

17

IRO
IR1
I R2
IR3
I R4
IRS
I R6
IR7

INT

PIC SLAVE

P I C MASTER

Fig . 4 . 5 PIC cascading in PC -AT

48

/EN

The Programmable Interrupt Controller

con nected to the master I Ri in puts. If a slave i nterrupt request is active and
th is i nterrupt request is the most prioritary one, the master wil l validate the
corresponding slave through the cascading l ines, so that the slave put the
interrupt routine address or the interrupt type on the data bus.

4.5

The PIC employme nt i n PC

I n PC-XT computers only one 18259A controller is used , with 20h

reference address and having the 8 i nputs assigned to the off-line devices
listed below:
Interrupt Input

Off - l ine device

( mo s t p r i or i t ary )

Vec tor ( type )

CO T ime r

08h '

IRQl

Keyboard

09h

I RQ2

Not used

OAh

I RQ 3

COM2
COM l

O Sh

I RQ4
I RQ S

Hard Disk

O Dh

I RQ 6

F l oppy D i sk

O Eh

I RQ 7

LPT

O Fh

IRQO

O Ch

T ab l a 4 . 3 P C - XT interrup t s empl cx-ment

I n PC-AT computers there are two cascaded controllers (see figure

4 . 3 . ) , havin g 20h as master address and AOh for slave . The typical
util ization and other possible util ization are listed in table 4 . 2 .
Non-masked Interru pt ( N M I)

There is a separate pin for non-masked interrupt request, which is

active on edge. The " I " bit setting does not i nfluence the acceptance of
N M I . The non-masked i nterrupt is used i n PC when a parity error is
detected .
IRQ

Priori ty

Vec tor

0
1

0 8h
0 9h

2
-

OAh

11

O Bh

12

O Ch

13

O Dh

14

O Eh

Typical
Employment
T ime r
Keyboard
Ca s c ading
( I RQ S - 1 5 )

COM2 ( s e r i a l
port )
COMl
Sound B l a s t e r
( SB ) , HD
Fl oppy D i s k
Con t ro l l e r

49

O ther Ut i l i t i e s
-

Modem , EGA adap t e r ,

COM3 / 4
Modem , SB , COM4 ,
Network Cards ( NC )
COM3 , Modem , SB , NC
LPT2 / 3 , COM3 / 4 ,
Modem , NC
Tape a c c e l e ra t o r

The Programmable Interrupt Controller

LPTl ( Para l l e l
port )
Real t ime c l ock

15

O Fh

7 0h

71h

10

72h

11

73h

12

74h

- PS / 2 mou s e

13

75h

14

7 6 11

15

10

77h

LPT2 , COM3 / 4 , Modem ,

SB , NC
-

NC ,
PC!
NC ,
PCI
NC ,

Coproce s s o r
( F PU)
IDE - 1 channe l
( HD )
IDE - 2 channe l

SB , S C S I adap t e r ,
dev i c e
SB , IDE channe l ,
dev i c e
SB , S C S I adap t e r ,
VGA card
NC , SB , S C S I adap t e r ,
I D E channe l
-

SCS I adap t e r
SCSI adap t e r , NC

Table 4 . 4 PC-AT interrupts employment

4.6 Exercise
a . Study the architecture a n d programming mode for the 1 8259A controller
and the employment of the controller in the I B M-PC compatible
com puters.
b . Write a test program for P I G .
c. Where can we find the addresses of the interrupt handler routines i n
IVT, for the req uests from the slave PIG inputs?
d.

Write a program sequence which masks the i nterrupts coming from

d ifferent devices (timer, keyboard , floppy d isk) and notice the effect
after running the program.

e. What is the role of the following sequence?

mov
out

f.

al , 2 0h
2 0h , al

What is the I RET instruction run effect?

g . What i nvolves the two 18259A controllers cascading according to the

con nections, programming and priorities?

50

Applications on the Interrupt System

5. APPLI CAT I O N S ON TH E I NTERRU PT SYSTEM

5.1 The applications support

The application presented below is an example of how the interrupt
system can be used . This example shows the major aspects , such as the
interrupt redirect, its solving and the development of a handler routine.
On I RQ7 i nput (the less prioritary input destined for L PT parallel port)
of the 8259A controller (master) there are two possibilities to generate an
interrupt: with a switch or from the channel 2 of a timer circuit with the base
address 1 OOh (see fig . 5 . 1 ) . The interrupt source selection is done with a
jumper.
+ 5V

S
CLK

Q t-----.

'I'

SYSCLK/16

GATE2
:
2 -....;::,_ _
OUT2 i---=u1

CLI<2

IRQ7
(B21 -ISA)

Fig . 5 . 1 The applications electrical schematic

For the interrupt source 1 the application I NT? .ASM presented below
was developed . The application counts the interrupts arrived on the line ' 1 '
from the pushbutton (and cleaned with a RS Fl i p-Flop) and signals it on the
screen .
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - -

PAGE 6 0 , 1 3 2
T I TLE INT7
COMMENT * Gene rat e s i n t errup t s f rom a pus hbu t t on on I RQ 7 *
STACK SEGMENT PARA STACK ' STACK '
512
DUP ( ? )
DW
ENDS
STACK
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - -

DATA S EGMENT PARA PUB L I C ' DATA '

51

Applications on the Interrupt System

d w 2 DUP ( ? )
O l d i rq7 interrup t addre s s
db O dh , O ah , " Push the but t on connec t ed t o
I RQ 7 1 1 , O dh , O ah , " $"
me s out
db O dh , O ah , 11 Done 11 , Odh , O ah , 11 $ 11
charac t e r db 3 0 h
ENDS
DATA
;----------------CODE SEGMENT PARA PUBL I C ' CODE '
MAIN PROC FAR
AS SUME CS : CODE , DS : DATA , S S : STACK , E S : NOTH ING
push ds
xor ax , ax
; f or return
push ax
mov ax , dat a
mov ds , ax
; me s s age d i s p l ay
mov ah , 9
mov
; me s s age addre s s o f f s e t
dx , o f f s e t me s i n
2 lh
; DOS interrup t c a l l
int
cli
; - - Red i re c t i n t e rrupt IRQ7 t o u s e r ' s rout ine - - - - - - - mov ax_1;3 5 0 fh
; Read t ime r inte rrupt addre s s in ES : BX
-:, C o? l-.
.!I
int 2 l h
; DOS interrup t c a l l
mov i rq7_o l d , bx
Ct-Ti u &) s ave o l d interrupt o f f s e t addre s s
,,,ry mov i rq7 -o l d + 2 , e s
; and segment addre s s
.,(_ \:. '
push ds
{" mov dx , o f f s e t i rq7 int
; new rout ine o f f s e t addre s s
-<'
mov ax , seg i rq7 int
mov ds , ax
mov ax , 2 5 0 fh
; l oad addre s s f rom DS : DX i n TVI
int 2 l h
; DOS interrup t c a l l
pop ds
mov ax , 0 6 0 0h
; c l ear s c reen
mov cx , O
mov dx , 1 6 4 fh
mov bh , 7
int l,_Q]l;ui (()
mov a l , O O l l l O O Ob
; masks s e t t ings
out 2 lh , a l
s t i ( ,, 1 1,,,l,_
wa i t :
mov ah , . l
; wa i t f o r any key
int 1 6 h
j z wa i t
; - - O l d interrupt i rq7 - - cli
; s ave s DS
pus h ds
; re s tore s ve c t o r in TVI
mov ax , 2 5 0 fh
; l oads o l d addre s s in
DS : DX
lds dx , dword p t r i rq7_o l d
; DOS interrupt c a l l
int 2 l h
pop ds
; re s tore s DS
; re s t or e s mask
: mov a l , l O l l l O O Ob
out 2 l h , a l
sti
mov ah , 9
; - - me s s age end - - - - - - - - i rq7_o l d
me s i n

- -

t
(l 'I-

'V ,

- -

u VP}(
_

'-

52

Applications on the Interrupt System

mov dx , o f f s e t me s out
int 2 1h
mov ah , 0 2
mov dl , 0 7
int 2 1 h
mov ax , 4 C O O h
int 2 1 h
MAI N ENDP

; be ep at exi t
; end program t hrough
; ex i t DOS func t i on c a l l

PROC NEAR
IRQ7 INT
; - - new inte rrupt rou t ine - - pu sh ax
push ds
mov ax , data
mov ds , ax
mov ah , O eh
mov a l , cha rac t e r
int l Oh
; chara c t e r d i s p l ay
inc chara c t e r
mov a l , 7
gene ra t e s s ound
int l Oh
ov a l , 2 0 h
; EOI
out 2 0 h , a l
pop ds
pop ax
iret
; re turn
END
; = = End = = ===-== = = = = = = = = = = = = = = = = = = = = = = = = = = = =
code ends
; CODE segment end
end ma i n
; program end
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * ,

5.2 Exercise
a. Analyze the I NT7 .AS M application and run it.
b. Rewrite the application :
using the controller i n poll i ng mode
using software cleaning instead of the fli p-flop.
c. Adapt the application for the second interrupt source (channel2 - timer)
d . The thi rd i nterrupt source i s a phone dial disk (see fig u re 5.2). Write a n
application that takes the i mpulses from i t a n d d isplays the d ialed
n umber. Attention to cleaning!

53

Applications on the Interrupt System

PC
.

,-........................... -.....................................................................

! PARALLEL
+5

PORT

10
-ACK

Dial disk

4K7
18-25
GND

IR 7

! - IRQBN

l
11. '" 1

Fig . 5 . 2 Dial disk application schematic

'

lft>l"Ji
..
. ; ' . . .

54

...

The OMA Controller

6 . T H E DIRECT M E MORY ACCES CONTROLLER

6. 1

OMA

transfer pri nciple

The transfer of a data block between a peripheral device and the

memory can be made using a program, with I N/OUT commands or using
d irect memory access. I n the first case, the transfer is relatively slow
(- 1 00ko/s) due to the necessary operations; the data follows the path
(described in fig u re 6 . 1 ) : peripheral device - microprocessor - memory. To
i ncrease the speed of data transfer between faster periphera l equipment
(Hard/Floppy d isc) and memory, if the external equ ipment has direct
access to the memory, we have an advantage, i . e . avoiding the data
passing through the microprocessor. This leads to a transfer rate of
- 1 Mo/s. This accessing mode is possible using the specia lized DMAC
ci rcuit (Direct Memory Access Controller). The principle of the DMA transfer
is presented i n fig . 6 . 1 ) .
Memory

M
0
IQ
IQ
GI

:" ......................................
;

l . . . . ._
....... , , . , , . , , , , , . . , ....,............

tJ

0
M
Ill
0
M

- HOLD
::fl

HLDA

........

.. .

i DMA

. .. . . . . . .. .

(>
. .

.. . . . .

'
'

.. .

1 11

..

... ... .. ... .. .. .. .. .. .. .. .. ... .. .. .. .

I
I

......................

.......................................................

1 :
'

1 '-------..39
HLDA _

Addre s s Bus
Data Bus
-control Bus ..

'
'

, _

--

DMA
Con t ro l l e r

(;.',

'

'

DREQ

DAC K _

.-

'

'

1 111

P e r i phe r a l
D ev i c e

. . . . . .

Fig . 6 . 1 Direct memory access trans fer principle

If the peripheral equipment has to write d ata i n the memory, the

necessary steps for i mplementing a DMA cycle a re :
1. The peri pheral system performs a request through the DREQ signal to
the DMA controller, i nforming that it needs a data transfer;
55

The OMA Controller

2 . The controller requ i res the microprocessor (or anothe r dedicated

hardware that solves O MA req uests) to yield the BUS by activating the
H RQ line to the HOLD pin of the microprocessor;
3. At the end of the current BUS cycle (if possible), the microprocessor
accepts the HOLD req uest and switches the buses in high impedance
state , then it activates the HLDA;
4. The controller receives the H LDA from the microprocessor and from
now on the controller can take over the buses contro l . It wi ll answer to
the periphera l system through DACK; DACK operates as a selection
signal for the peripheral device .
The transfer wil l be made under the total control of the O MA controller
that generates addresses and selection signals for the memory. The
transfer takes place automatically, without the microprocessor intervention ,
therefore without I N/OUT instructions. The OMA cycle is able to continue
with other cycles if the request is still o n , or the yield ing of the bus is
possible if HOLD becomes inactive .
The DMAC 1 8237 A for PC has 4 independent channels for di rect
memory access , each of them havi ng own progra mmable registers . PC and
PC/XT computers have 4 OMA channels of 8 bits and since PC-AT
compuiers h ave 7 DMA c h a n n e l s of 8 a n d 1 6 bits , by ccica d i n !:l lwu
18237 A controllers.

6.2 OMA Controller overview

The O MA controller 1 8237 A is a programmable circuit designed to be
employed in microprocessor systems in association with an external 8:bit
register (e. g . 1 8282 ) . The circuit contains 4 independent channels and it can
be exp anded to any number of channels by cascading add itional 1 8237 A
circuits. There can be addressed maxi mum 64K words on each channel.
The circuit allows also merriQ.ry- rl'lmory transfers .
6.2 . 1 Pins assignment
The circuit has 40 pi ns that can be grouped in fou r categories,
considering the fun ctions of the signals.
Control and synchronization signals
RESET ( 1 3): i n put active on " 1 " that switches to "O" the status
registers , req uest, tem pora ry register and the mask. After reset,
is an i nactive cycle
CLK ( 1 2) : clock i nput for 5 MHz
EOP/ (25): (End of Process) bidirectional sig n a l , active on
indicates the ending of a OMA task; it can be internally or
activated

56

command
the circuit
"O" which
externally

The OMA Controller

CS/ ( 1 1 ) : (Chip Select) input active on "O" used to select the circuit as a
peripheral 1/0 device d u ring the inactive cycles
READY (6): i n put used to synchronize the circuit with the memories and the
slow peripheral devices by prolonging the M E M R or M E MW impulses
AEN (9): (Address Enable) c;> utput used for the command of a latch register.
When AEN= 1 , the bits A8 . . . A1 5 of the address provided by 18237A are
written to the address bus.
ADSTB (8): (Address Strobe) output that controls the loading of the
address byte A8 . . . A1 5 in a register
M EMW/ (4) : (Memory Write) TS (three state) output used when writing data
to the memory during a O MA transfer that is either a Write type or a
memory -memory type
MEMR/ (3): (Memory Read) TS output similar with M EMW/, but for reading
from the memory
IOR/ ( 1 ) : (1/0 READ) bidirectional TS signal, active on "O" used by CPU to
read the control reg isters i n the i nactive cycle; in the active cycle it is used
for taking data from a peri pheral device in a OMA writin g transfer
IOW/ (2) : ( 1/0 WRITE} bidirectional TS signal , active on "O"used by CPU to
program the circuit in the inactive cycle; in the active cycle it is used to
transfer d ata to a peri phera l device in a DMA read ing tra nsfer
Req uest/acknowledge signals for microprocessor bus control
DREQi ( 1 9- 1 6): i=0,f 1 ,2 , 3 (OMA Request) inputs on which the peripheral
devices con nectec fo the circuit send asynchronous signals of OMA
transfer request on the afferent channel . The active level of signals and the
channel priorities are programmable. DREQ line must be maintained active
until the corresponding DACK line becomes active .
DACKi (36/37/ 1 4/1 5): (OMA Acknowledge) used to signal the
execution of OMA req uest to the peri pheral devices that req uested the
O MA transfer. The active level is programmable, after using RESET they
are active on "O"
H RQ ( 1 0): ( Hold Request) output used by 18237A to request control over
the buses
H LDA (7): ( Hold Acknowledge) input activated by the microprocessor,
indicatin g that the bus is ready for the OMA transfer. The signal becomes
active ( H ) after at least a clock period after HRQ is activated

Address l i nes
AO . . . A3 (29-26): TS, bidirectional address lines; these are outputs in the
active cycle and contain the less significant 4 bits of the address and they
are i nputs in the i nactive cycle, used by the CPU to address the i nternal
reg isters as ports .

57

The OMA Controller

A4-A7 (24-2 1 ) : address lines, outputs that work only during D MA transfer,
providing A4-A7 bits of the address provided by DMAC .

Data l i nes
DO-D7 (3 1 -35, 38-40): bidirectional TS lines connected to the data bus of
the system . In the 'program state' , on these l ines the address, state ,
temporary or U C cou nting registers are written or read . I n the active cycle
they represent the address bits A8-A 1 5 , being strobed by the ADSTB signal
to be memorized in a n external latch .
6.2.2 The i nternal block diagram of DMAC 18237A
I n the block diagram (fig.6.2), the following modules can be noticed :

1 . Timing and control block: generates i nternal synchron ization signals

and external control signals ( I OR/, IOW/, M E M R/, M EMW/ etc . )
2 . Commands control block: decodes the commands tra nsmitted t o the
circuit by the C P U
/ EO P

DE CREMENT

TEMP .

I N C / DECR

WORDS

EMP .

COUNTER ( 16 )

T I M I NG

ADS T B
/ MEMR

16

&

CONTROL

/ MEMW

ADORES

EG I S TER ( 1 6 )

F o r e a c h channe l
READ BUFFER

16

R / W BUFFER

BAS E
BASE
ADDR .

CRT .
CRT .

WORDS

ADDR .

COUNT

( 16 )

(16)

(16)

COMMAND

WORDS

CONTROL

COUNT
(16)
AB . . Al S
DO - Dl

DREQ
0-3

8
4

COM ( S )
P R I OR I TY
ENCODER
AND

MAS K ( 4 )

LOG I C
4

8
DBO . . D B 7

PRIORITY
ROTAT I NG
DACK
0-3

R/W
REQUEST ( 4 )

MODE

-'----- _....'---

STATUS

(8)

TEMPORARY

(8)

( 4X6 )

Fig . 6 . 2 Internal block diagram for DMAC - I 8 2 3 7A

58

The OMA Controller

Priority control block: solves the orderi ng problem of the OMA transfer
req uests executing for multiple concurrent channels
4 . OMA transfer channels: the circuit has four programmable independent
channels. On every chan nel , there are five reg isters (register for the
main address, main words counter, current address, current words
counter, mode register).
The 1 8237A circuit has a memory capacity of 344 bits. The registers
significance is:
3.

REGISTER

REGISTER LENGTH

NUMBER OF REGI STERS

B a s e addre s s
B a s e words coun t e r
Current addre s s
Current words coun t e r
Temporary addre s s
Temporary words coun t e r
S t at u s
Command
Temporary
Mode
Mask
Reque s t

16
16
16
16
16
16
8
8
8
6
4
4

4
4
4
4
1
1
1
1
1
4
1
1

Base address register (1 6 bits): contains the first address the transfer is
made from. This register can be written using the progra m , but it cannot be
read .
Base counter register (1 6 bits) : contains the number of words to be
transferred . It can be written , but it cannot be read .
Current address registers (1 6 bits): contains the value of the transfer
address. This address is automatically increased or decreased after every
transfer. If the channel is programmed with auto i n itialization, the value of
the Base address is loaded in this register.
Current counter register (1 6 bits): determines the n umber of transfers left to
be executed . When it switches from OOOOh to FFFFh, a TC (Terminal
Count) signal i s generated .
Mode register (6 bits): g ives information about the transfer mode and it is
written d u ring the circuit programming
Temporary address register (1 6 bits): contains the temporary address on
16 bits i n the case of memory- memory transfer
Temporary words counter register ( 1 6 bits) : has the same function as the
current cou nter register, but it is used with the temporary address register
59

The OMA Controller

Temporary data register (8 bits): holds the current byte transferred i n case

of memory-memory tra nsfers

Status register (8 bits): contains information about the circuit status. It can
be read by the C U , therefore the channel that received a TC signal or a
OMA request can be determined .
Command register (8 bits): controls a l l the operations made b y 18237 A. It is

programmed in the 'program state' by the microprocessor and it can be

reinitialized with a RESET signal or an erase command .
Mask register (4 bits): contains the mask for validating O MA requests on

each channel . The mask bit is switched to " 1 " when the channel reaches
/EOP, if it was not programmed for auto i nitiaiization .
Request register (4 bits): one for every channel and it signals that a O MA

request arrived on the afferent channel . The priority control block manages
it. A TC or EOP determi nes the erasing of the corresponding req uest.

6.2.3 The 18237A Circuit programming

I n order to program the OMA circuit we use as a main address Oh,
reserved i n PC for this circuit. For PC-AT, that uses 2-cascaded circuits,
the addresses are 0-0F for the slave circuit and COh-OFh for t h e ma ster.
The operational mode and the reserved port addresses, associated to the
registers are determined by the following :

Channel Port ( * )
OOH
O OH
O lH
O lH
02H
02H
03H
03H
04H
04H
O SH
O SH
0 6H
0 6H
07H
07H

0
0
0
0

2
2
2
2
3
3
3
3
*
**

Port ( * * ) Type 1/W)

COh
COh
C2h
C2h
C4h
C4h
C6h
C6h
CBh
CBh
CAh
CAh
CCh
CCh
CEh
CEh

( w )
R

w
R

w
R

w
R

w
R

w
R

w
R

Slave circuit at P C - AT

Regi s ter
B a s e addre s s channel 0 D MA
Current addre s s channe l 0 DMA
B a s e c oun t e r channe l 0 DMA
Current counter channe l 0 DMA
B a s e addre s s channel 1 D MA
Current addre s s channe l 1 DMA
B a s e count e r channe l 1 DMA
Current coun t e r chann e l 1 DMA
B a s e addre s s channe l 2 DMA
Current addre s s chann e l 2 DMA
B a s e c oun t e r channe l 2 DMA
Current coun t e r chann e l 2 DMA
B a s e addre s s channe l 3 DMA
Current addre s s chann e l 3 DMA
B a s e coun t e r channe l 3 DMA
Current coun t e r chann e l 3 DMA

( the only DMAC at P C - XT)

Ma s t e r c i rcui t at P C - AT ( non - ex i s t ing at PC - XT )

60

The OMA Controller

Regi s ter or Soft command

S t atus

r eg i s t e r

(#)

Command re g i s t e r
S o f tware

r e que s t s

I n d i v i du a l
Mode

ma s k s

r eg i s t e r
reg i s t e r

r eg i s t e r

f l ip - f l op c l e a r

I n t e rna l

Temporary r eg i s t e r
Re s e t

I 8 2 3 7 A -ma s t e r

C l e a r ma s k r eg i s t e r
Wri t e b i t s
*

of

c l e ar

ma s k r eg i s t e r

Port*

Port**

O BH

DOh

0 8 Ho .

DOh

0 9H

D2h

OAR

D4h

O BH.<.

D6h

O CH

D8h

O DH

Dah

ODH

Dah

OEH

DCh

O FH

DEh

R I W Operation
R

w
w
w
w
w

w
w
w

( in al ,
( out
(

0 8h )

OBH,

out

0 9H ,

al)
al )

( out

OAR ,

al )

( ou t

OBH ,

al )

( out

O CH ,

al )

( in al ,

ODH )

( out

ODH ,

al )

( out

OEH ,

al )

( out

O FH ,

al )

S l ave c i rcu i t at P C - AT ( the on ly DMAC at PC - XT )

Mas t e r c i rcui t a t P C - AT ( non - exi s t ing a t PC - XT )
S o f tware commands

**

The controller registers have the structure presented below. When

programming the circuit its will be charged with adequate values. For the
software commands, the content is not relevant.
COM MAN D REGISTER

DACKH

D RQL

EWR

RPY

CTIM

D I SAB

COAHE

0
M-M

= 0 disables memory - inemory transfer

= 1 enables memory - memory transfer
= 0 disables channel 0 addreS storing
COAH E
= 1 enables channel 0 address storing
= x if M - M = O
D I SAB= 0 activates I 8237A
RPY = 0 fixed priorities
= 1 deactivates I 8237 A
= 1 rotate priorities
. EWR = 0 late write pulse
CTI M = 0 normal cycle
=1 extended write pu lse
= 1 compressed cycle
= x if CTI M = 1
= x if M - M = 1
DACKH = 0 DACK active on 1
DRQL= 0 DRQ active on 1
= 1 DACK active on 0
= 1 DRQ active on 0
M-M

REQUEST REGISTER

6
-

I -

SRQB = 0 cleat request bit

= 1 set req uest bit

SCl
0
0
1
1

sco

0
1
0
1

I - I

SRQB

SCl

Signi ficance
Select s
Selects
Selects
Selects

61

channel
chann e l
channe l
chann e l

0
1
2
3

0
sco

The OMA Controller

MASK REGISTER
7

S M KB

I SCl

SMKB

= 0 clear mask bit

= 1 set mask bit (blocks channel)
sco

SCl

0
0
1
1

0
sco

Signi f i cance
Select s
Select s
Selects
Selects

0
1
0
1

channe l
channe l
chann e l
channe l

O
1
2
3

mask
mas k
mask
ma sk

bit
bit
bit
bit

M O D E REGISTER

SMl

SMO

AUT0 1 =
=
DECR =
=

0
1
0
1

OECR

AUTOI

SOTl I SOTO

deactivates auto initialization

allows auto initialization
selects increasing the address
selects decreasing the address
sco

SCl

SOTl

Selects
Selects
Selects
Selects

SOTO

0
0
1
1

0
1
0
1

SMl

0
0
1
1

0
sco

Signi ficance

0
1
0
1

0
0
1
1

SCl

channe l
channe l
chann e l
channe l

0
1
2
3

Signi ficance
Te s t ing
Wr i t e i n memory
Read f rom memory
I l l egal
I f SMO = O and SMO = l

SMO

Signi ficance

0
1
0
1

Reque s t mode
Byt e mode
B l ock mode
Cas cade mode

MASK REGISTER (FOR ALL CHANNELS)

7

SMKl

SMK2

SM Ki = O clear mask bit for channel i

= 1 set mask bit for channel i , i=O, 1 , 2 , 3

62

' O

SMKl

I I SMKO

The OMA Controller

STATUS REGISTER

RQ3

TCi

RQ2

RQl

RQO I TC3

TC2

TCl

TCO

= 1 channel i is at a null counter

= 0 channel i is not at a null counter i=O, 1 , 2, 3
RQi = 1 OMA transfer request on channel i
= O no OMA transfer request on channel i , i=O, 1 , 2 , 3

6.3 Functional Descri ption of the OMA Controller

1 8237 operates i n two large cycles: the inactive cycle and the active
cycle . Each cycle is composed of a number of states . 1 8237 is able to
reserve 7 differDJ!<:ii s . each lasting for a clock period .
I n peripheral device to memory or memory to peri pheral device
transfers made using O MA, data does not pass through the controller. Data
are transferred directly from the 1/0 port into the memory (or from memory
to 1/0 port), the /IOR and /MEMW (or /MEMW and /IOR) signals being
activated d u ring the transfer. 1 8237 A also allows d i rect memory- memory
transfer. This transfer req uires a !ItfililQ l)' _Jaqi rig and memory_ writin_g , the
data passing through the OMA controller. Between 18237A and the
micro p roces sor, th e profo col presented above takes place.
6.3.1 Idle C y cle
When none of the channels requires a OMA service , 18237 A will enter
the inactive (idle) cycle or 'slave' mode. In this mode, the controller will
search the D REQ l ines on every clock cycle and the logical level of /CS p i n ,
to determine a microprocessor possible attempt o f reading or writing
i nternal registers . If /CS and H LDA are "O", 18327 A enters the programming
state, when the CPU is able to change or inspect i nternal registers . AO-A3
address lines are i nputs and allow internal registers selection . Due to the
size and n umber of i nternal registers, an i nternal fli p-flop is used to
generate an additional address bit that serves to select the high or low byte
of the 1 6 -_Q_it -dd ress registers or word counters. The flip-flop can be
i n itialize d qn reset using Master Clear or Clear fli p-flop software
commands , so that during writi ng/reading a new addresses the operation to
be made i n the correct order of the bytes.
6.3.2 Active Cycle
When 1 8237A is i n the inactive cycle and receives a OMA request
(DREQ) on one of the channels, the controller sends a H RQ req uest to the
microprocessor and enters the active cycle or the 'master' mode, during
which the circuit will control the buses and wil l execute OMA transfers,
working i n one of the 4 transfer modes.
63

The OMA Controller

6.3.3 Transfer Modes

Single Transfer Mode. I n this mode, the circuit is programmed to
execute only one transfer, the word counter will be decreased and the
current addres s wil l be i ncreased/ decreased after the execution of the
transfer. When the word counter is switched from Oh to FFFFh (TC
Terminal Count), on /EOP line an impulse is generated . If the channel was
programmed i n auto i n itialization mode, it will be auto i n itialized . OREO
must be kept active u ntil DACK becomes also active. If OREO is activated
only during a transfer period , then H RO becomes inactive and the circuit
wil l decontrol the buses .
Block Tra nsfer Mode. I n th is mode, when OREO signal appears,
repeated transfers will be executed until getting to TC or /EOP=O is
received from exterior. I n this transfer mode, OREO line must be kept
active only unti l the DACK signal appears . I n auto initialization mode, the
current address and the cu rrent counter of the channel are reloaded with
the initial parameters and the channel stays i nactive. The block maxi m u m
dimension is 6 4 KBytes.
Cascaded Transfer Mode. This mode is used to connect more than
one 1 82 3 7 A circuit i n the system . In fig . 6.3 the connection mode for two
such circuits is presented , connection used in PC-AT type computers.
Demand Tra nsfer Mode. The circuit is programmed to continue the
execution of the transfers until a TC or an external /EOP appears or until
OREO becomes i nactive; therefore the transfer is able to continpe until the
1/0 device wil l finish the sent data set. The auto initialization can be
determined by the end of the program (/EOP) generated external ly or by a
TC .
6.3.4 Types of Transfer
On each of the modes described above different types of transfer can
be used : read , write or test. On write transfers, the data is taken from 1/0
circuits and stored in the memory, activating simultaneously /ME MW and
/IO'fl. signals. On read transfers, data is sent from the memory to the 1/0
devices by activatin g the /M EMR and /IOW signals. Test transfers are
pseudo transfers . D MAC operates the same as a i n the other transfers, the
d ifference is that the control lines of the memory and of the 1/0 devices
remain inactive , only the addresses are generated .

64

The OMA Controller

Ch

D R QO
OAC l<D

Ch

ORQ1
OACK1

HRQ
H LOA

Ch

O R QO
D AC l<D

HRQ

C e nt r a l
Un i t
H LDA

Ch

DRQ1
DACK!

F loppy
Ch

Ch

Ch 2

D R Q2
O AC K2

Ch 3

O R Q2
OACK2

disk
i nt e r f ac e

O R Q3
OACK3

8237A Slave(Oh)

8237A Mester(COh)

Fig . 6 . 3 DMAC cascade connection

Memory to memory transfer
This transfer is valid for channels 0 and 1 . The data passes through
the 18237 A controller that has an 8-bit temporary data register, which keeps
the c u rre n t tra n sferred byte . The tra n sfer is i n itial ized by setting a job
request (OREQ) on channel 0. For this transfer there is the possibil ity to
i nscri be the source address (where the tra nsfer is made from), the
destination address and the n umber of bytes that need to be transferred .
The source address is inscribed in the current address register of channel
0, while the destination address is in the current address register of channel
1 . The number of bytes to be transferred will be written i n the word counter
register of channel 1 . Channel 0 may be programmed to use the same
address for a l l the transfers, allowing the initialization of a memory block
with the same word .
Autoinitial ize
When the channel involved in the OMA transfer was programmed
with auto initialization , after a /EOP appears, the Current Add ress and
Current Word Counter reg isters are reloaded with the values from Base
Address and Base Word Counter registers. The channel is ready to perform
a new OMA transfer without the i ntervention of the central u n it, when a
OREQ request is detected .
Priorities
18237 A may be programmed to work with two types of priorities: fixed
priorities and rotating priot... I n case of fixed priorities , simultaneous
OMA requests will be exec-uted in a fixed order: channel 3 - the less
65

The OMA Controller

prioritary, channel 0 - the most prioritary. For rotating priorities , the channel
whose req uest was executed most recently wil l become the less prioritary
one. This mode prevents the system monopolizing by one channel.

6.4 Connecti ng the 18237 A controller

In order to be packed in a 40-pin capsule, for the 1 8237A circuit the
h i g h byte of the address is multi plexed o n the data lines. For de
m u ltiplexi ng it, an external register is used , to memorize the high byte of the
address o n the descending front of ADSB signal . AEN signal validates the
reg ister outputs on the address bus. AO-A 7 wi l l be tied d i rectly to the
add ress bus (fig . 6 .4) .

6.5 The OMA controller i n I BM-PC

The OMA Controller operation is not very transparent for the user and
its prog ra m m i ng is q uite complicated . There are different OMA
architectures for PC-XT and PC-AT. The PC-:-XT has only cm _!:)MAC that
allows 8-bit tran sfers; while PC-AT has a second controller that allows
perform ing 1 6-bit transfers. T h e cascad ing mode of the two 1 82 3 7 A circuits
is presented in fig . 6 . 3 . The 'slave' circuit is connected to a channel of the
'master' circuit so that HRQ and H LDA signals are con nected to DREQO
and DAC KO of the ' master' circu it. Due to this cascade connection , the
channels of the 'slave' circuit wi l l have superior priorities than the ' m aster'
channels. This is the reason for the channel n u m bering in fig . 6 . 3 . Chan nels
ADDPE S S BUS AO-Al5

BUS EM

AO -A15

f--

EN

HLDA

'

A 0 -A3 A4 -A7 / C S
I 8 2 3 '1A

HI.DA
C LK

C LK

/IO
/ I O''
/MEHR
/IIEHN

DBO-DB7

HllQ

HOLD

CPU

"

Fi g . 6 . 4

'- / O E

AD S TB

DB O -DB

STE

Jl8 -A15
8282

( Sb i t l at c h )

;.

.
.

/ I O I\l I ON/MEMR /HEHN

DATA BUS

I n terfacing

66

I 8 2 3 ?J!. : i ':o

the

sys tem

./

The OMA Controller

4-7 can execute 1 6-bit transfers, while channels 0-3 can execute only 8-bit
rransfers , - for PC-XT. Since the controller, by its desi g n , can provide
only 8-bit transfers because of increasing I decreasing the internal address
by only one byte register, after every transfer it is necessary to establish the
mode of execution of the 1 6-bit transfers . The solution for i ncreasing I
decrea _by_-2 the address that the controller gives on the bus is as it
follows: the address l ines that come from OMAC wil l be postponed by 1
related to the l i nes of the address bus, being equivalent to a multiplication
by 2. On the programming level, the 1 6-bit transfer i nvolves certain
changes:
1 . The memory address is reduced by half, being automatically doubled by
the hard realized offset
2 . O MA 1 6-bit tra nsfer can begin only from even memory addresses
3 . The block length wil l b e calculated i n words, not bytes; maxi mum length
becomes 1 28 Kbytes
4. By choosing as an address for the beginning of the transfer the
beginning of a 64 Kbytes page, we make sure that the OMA segment
wi l l not be exceeded
O MAC is able to control only the address lines AO-A 1 5, for that the
maximum block length to be transferred has _64 Kb ytes. It is the PC
designer d uty to control the other address bits A 1 6-A 1 9 for PC-XT (A 1 6A23 for PC-AT) i n order to place the block to be transferred anywhere i n
the 1 Mo memory or the 1 6 Mo memory o f the PC. T h i s can be
accomplished as presented in fig .6.5, by add ing a page register of !!- or 8
bits. For this purpose , the 74LS 1 70 circuit is used for Felix PC
- - XT and
74LS6 1 2 for PC-AT.
Page registers corresponding to different cha nnels can be loaded
employing 1/0 instructions, using the fol lowing port addresses reserved for
this:
PC - XT :

PC-AT :

8 l h f o r channe l 2 DMA

( addre s s b i t s 1 6 - 1 9 )

( addre s s b i t s 1 6 - 1 9 )
8 2 h f o r channe l 3 DMA
8 3 h f o r channe l s O and 1 DMA ( addre s s b i t s 1 6 - 1 9 )

foI

8 9h

( addr e s s b i t s 1 6 -

6 DMA

8bh f o r chann e l 5 DMA

B ah f o r channe l 7 DMA
8 f h f o r DRAM r e f re sh

67

( addre s s b i t s 1 6 - 1 9 )
( addre s s b i t s 1 6 - 2 3 )
( addre s s b i t s 1 6 - 2 3 )
( addre s s b i t s 1 6 - 2 3 )
( addre s s b i t s 1 6 - 2 3 )

The OMA Controller

1 6MB

Page2 5 5 ( 64Ko )
D e te rm in e s of f s et

in t h e page

reg is ter Externa 1 latch

( 8 bit s )
regi ste r ( 8 )

DMA

15

Externa l page
registe r ( 8 )

Pages

( 64Ko )

DMA BUFFER

.................!i>.g1 . < 6. J<:?. >

16

. . . . . . . ..

P age3

Page reg i s t er
dete rmine s
merrory page

OMB

. ...

( 64Ko )

P age2

( 64Ko )

P agel

( 64Ko )

P ageO

( 64Ko )

Fig . 6 . 5 Memory address generation for DMA trans fer using I 8 2 3 7A

OMA transfer channels are dedicated as it follows:
PC -XT :

DMA channel

e/16

0
1
2
3

bits

Defaul t uti l i ty
DRAM re f re s h
Not u s e d
F l oppy D i sk
Hard D i sk

8
8
8
8

PC-AT :

Other uti l i ties

Default
uti l i ty

DMA
Channel

8/16
Bits

Not used

S ound cards
( l ow DMA )

SCS I adap t o r s , para l l e l ECP port ,

network cards , voc a l modems

F l oppy D i s k

Band a c c e l erator cards

Not u s e d

Para l l e l ECP port , SCS I adap t o r s ,

cards
( l ow DMA ) ,
s ound
network
cards , voc a l modems

16

C a s c ad ing

16

S ound cards
( hi gh DMA )

S C S I adap t o r s , network cards

16

Not u s e d

16

Not used

Sound
cards
Sound
cards

68

cards

( h igh

DMA )

network

cards

( high

DMA ) ,

network

The OMA Controller

6.5 Exercise
a.

Study the architecture and programming of the 18237 A circuit and its

use in PC.
b.

Write a program sequence that verifies the circuit registers (the ones
that can be verified).

c. Analyze the following sequence and determine the controller functioning

mode, the channel, initial transfer address and the length of the block to be
transferred.

d.

MOV AL, OOOlOOOOB

MOV AL,

OUT 08H,AL

OUT 8 7H I

MOV AL, OOOOOlOOB

MOV AL, OOH

"ii/

OUT 09H,AL

OUT OOH, AL

MOV AL, OOOOOOOOB

MOV AL, 80H

OUT OAH,AL

OUT OOH, A

MOV AL, 10010100B

MOV AL, 00

OUT OBH, AL

OUT OlH, AL

MOV AL, OOOOOOOOB

MOV AL, OAH

OUT OFH,AL

OUT OlH,A

Analyze the following sequence (from Felix-PCBIOS) that represents

the OMA 18237 A controller initialization.

MOV AL, OFFH

OUT OAH, AL

OUT OlH, AL

MOV AL,

PUSH AX

OUT

18

41H, AL

OUT OlH, AL

MOV AL,

MOV AL,

OUT OBH, AL

SSH

;start channel
;of

18253

41H

OUT OBH, AL

MOV AL,

MOV AL,O

OUT OBH, AL

42H

MOV CH, AL

MOV AL, 43H

OUT 08H, AL

OUT OBH,AL

PUSH AX

e.

Deactivate DMAC and check the access to floppy disk.

69

timer

OMA Data Transfer on PC-A T

7 . O MA DATA TRAN SFER ON PC-AT

7 . 1 The application descri ption

To illustrate how O MA transfer works, the fol lowing application
realizes a transfer from an 1/0 port to memory, in a PC-AT computer. For a
good understanding of the board , study its block schematic (fig . 7 . 1 ) and the
electrical one (fig.7.2). The application transfers i nto the video memory of
the computer a block of data (actually the same byte) from an i nput port,
through OMA; the transfer is initiated using a switch (see fig .7 . 1 ) . A three
state bi-directional bus amplifier, 1 8286 , makes the 1/0 port .
The direction of the transfer is established b y the input T: i f T = " 1 " the
transfer is from the inputs Ai to the outputs Bi; if T="O" the transfer is
backwards. The transfer takes place as long as /OE = "O" - see fig .7.2. The
ASC I I code of the byte transferred into the memory can be established
using the switches connected to the Ai in puts of the port 8286 . One of the
Flip-Flops in the electrical schematic cleans the switch contact that i nitiates
the OMA transfer, the other serves the req uest O MA-O RQO at /OACKO
activation . The time-charts from fig .7.3 help us observe the relationship
between the schematic signals. The board is i ntrod uced i n one of the
computer I SA slots. For the transfer, the channel 0 OMA wil l be used ,
because it is available at PC-AT.
COMMAND

BUS

ADDRESS B U S

HRQ

CPU

VIDEO
MEMORY

DRQO
DEMAND
LOGIC

DMAC

HLDA

I 8237A
INPUT
PORT

DATA BUS

Fig . 7 . 1

The block

di agram

71

of the

board

OMA Data Transfer on PC-A T

5V

5V

5V

1 0k
DMA
D

CLK

12

11

7474

----5-<

i n it i a l i z a ti on
s w it ch

CLK

5V

1 0k

DACK O

DO

5V
1 0k

------""""-" O E

GND

8286

62
63
64
65
66
67
T

16
15
14
13
12
11

!-'--

D7

( I SA B US )

5V

Fig . 7 . 2 The elec trical schematic of the app l ication

S TART
Ql ( CL K
Ql ( DRQ O )
HRQ

----

HLDA
AEN
AD S T B
DBO - S B 7
_
AO - A 7

oA8-Al5
--------f

____________,

_________

/ DACK

a l i d Add

Va l i d Addr

/ IOR . /MEMW
Fig . 7 . 3 Timing for the DMA transfer

72

)----

OMA Data Transfer on PC-A T

A program is presented below, which performs a data block transfer

from the i n put port to the video memory. The OMA controller programming
is done using its registers. 1 8237 A will accept programming (in the inactive
cycle) anytime HLDA is inactive , even if HRQ is active . The first step in the
circuit programming should be to deactivate the circuit (using the command
register) or to mask the channel whose registers we want to load. This wil l
avoid a OMA request apparition during t h e circuit programming . When the
programming is accomplished , the controller can be activated , or the
channels u nmasked .
The memory address where the data will be transferred is loaded into the
Base Add ress Register. The end of OMA service (/DACK deactivation)
takes place after a number of N+1 bytes had been transferred , N being the
n umber loaded i nto the Base Words Cou nter.

7.2 The program

I n order to programme the OMA controller we have to choose a
chan nel on which we requ i re the OMA service . I B M PC-AT has the
channels 0, 5, 6, 7 available, so we can choose one of the m . In the
progra m presented below, the channel 0 was chosen , whose registers were
initialized in the PROG RAM M I NG procedure. The first step in this
procedure was a Master Clear operation, a software command that has the
same effect as a hard reset. Its effect is the erasure of the command,
status, request and temporary registers; the "flip-flop" and the mask register
settin g s are also erased and 18237 A enters the i nactive cycle .
The address where the transfer is made is loaded as follows : the less
significant 1 6 bits (AO-A 1 5) into the Base Address Register and the most
significant byte (A 1 6-A23) i nto the Page Register (AT com puters use all 8
bits of the page register). I n this case , the destination of the transfer is the
video memory. We choose the graphic mode 2 fo r the terminal: text mode
80x 25. In this case, the base address of the video memory is B8000h. I n
order to transfer data into the memory starting with address B8320h, the
value OBh is loaded i nto the Page Register and the address 8320h into the
Base Add ress Register. The port associated to the Base Add ress Register
is an 8-bit port, so we wil l perform two OUT operations, first the low part,
then the high part of the address.
The n umber of bytes to be transferred is loaded i nto the Base Words
Counter Register using other two OUT instructions. The n umber of
transferred bytes is increased by 1 : for example if we write 1 00 i nto the
register, 1 0 1 bytes wil l be transferred , becau se of the TC condition which
appears at the tra nsition from 0 to FFFFh.
73

OMA Data Transfer on PC-A T

I n the video memory, in text mode, each character is represented on

two bytes: one for the ASC I I code of the displayed character and the other
one for the color attribute. The character codes are memorized at even
addresses, the color attributes at odd addresses. We suppose that the
base address is even. If an even n umber of bytes is transferred (the
n umber loaded in the Words Counter is odd ), on the screen appears a
n umber of cha racters equal to 1 /2 *(number i n WCR) + 1 , all of them having
the same color attribute. If the beginning address is odd , the bytes stored at
this address wil l represent the color attribute and it is possible that the first
character on the screen to be different from the transmitted one, but having
the same color attribute . If the number of bytes is even, the last byte will be
stored at an even address, so it represents the ASC I I value of the last
character. The color of this one wil l be given by the byte from the next
address, its content being indeterminate . The same thing happens if the
base address is even and an odd number of bytes is transferred .
PAGE 6 0 , 1 3 2
T I TLE DMABLOCK
; The program p e r f orms the DMA tran s f e r of a dat a b l ock
; From an i nput port into the video memory
STACK SEGMENT PARA STACK STACK '
; r e s e rve s 5 1 2 byt e s f o r the s t ack
dw 2 5 6 dup ( ? )
STACK ENDS
DATA SEGMENT PARA PUBL I C ' DATA '
me s s 1 db ' Con f igure an 8 - b i t AS CI I chara c t e r f rom the
swi t che s and when ready p re s s Ent e r '
db O dh , O ah ' $ '
me s s 2 db ' Pre s s Ent e r and when the s c re en i s c l e an ,
p re s s the s t art key ' db O dh , O ah , ' $ '
me s s 3
db ' The numbe r o f byt e s you w i s h t o b e t rans f e rred
( rep r e s ented on 4 dig i t s ; if the number is
<
1 0 0 0 put
O on the mos t s i gn i f i cant pos i t i ons ' db O dh , O a h , ' $ '
key
db
O dh
DATA ENDS
CODE SEGMENT PARA PUB L I C ' CODE '
MAIN PROC FAR
a s sume c s : code , ds : da t a , s s : s t ack , e s : nothing
; s ave P S P s egment addre s s and o f f s e t O
pus h ds
mov ds , ax
; c a l l PROGRAMM ING procedure
c a l l p rogramming
move ax , 2
; t ext mode , 8 0x2 5
; graph i c mode s e l e ct i on
int l O h
move cx , 2
; we d i s p l ay two me s s ages
; o f f s e t f o r me s s age 1
mov dx , of f s e t me s s l

74

OMA Data Transfer on PC-A T

aga i n :
mov ah , 9

; chara c t e r d i s p l ay func t i on

int 2 1 h
mov s i , o f f s e t key
ca l l wa i t

; t he addr .

of

the key we are wa i t ing f o r

; c a l l Ent er wa i t ing proc edure

dee ex
j z s t op
mov dx , o f f s e t me s s 2
j mp aga i n

; redo unt i l the me s s ag e s are d i sp l ayed

s t op : ca l l de l e t e
etO

: mov ah ,
int

; checks

for p r e s s e d key

16h

j z etO
cmp a l , ' q '

; compares the pre s se d key w i t h

jnz etO

; i f i t was not

'q' ,

'q'

redo t he l o op

ret
MAIN ENDP
PROGRAMM I NG PROC NEAR
mov a l , O fh
out

O dh , a l

mov a l , O O O O O l O Ob

; equival ent w i t h hard r e s e t

; mem . - mem .
; norma l

d i s ab l e ,

cyc l e ,

; a c t ive on 1 ,
out

0 8h , al

mov a l , O O O O O l O Ob

! 8 2 3 7 dea c t ivat i on ,

f ixed

priorit ies ,

DRQ

DACK a c t ive on O

; Command Reg i s t e r

out O bh , a l

; mem . WR , b l oc k mode ,
; Mode Reg i s t e r

aut o in i t . addr

mov a l , O fh

; mask f o r channe l s 0 , 1 , 2 , 3

out o fh , a l

; Mask Reg i s t e r

mov a l , Obh

; t he h i gh part o f the addre s s

incr .

( f or a l l c hanne l s )

out 8 7 h , a l

; Page Reg s t e r f o r channe l

mov a l , 2 0h

; t he l ow part of

mov dx , O Oh

; the addre s s o f t h e port a s soc i at e d w i t h

the addr e s s

; t he B a s e Addre s s Reg i s t e r f o r C O
out dx , a l

; l ow p a r t o f t he B a s e Addr .

Reg .

for CO

mov a l , 8 3 h
out dx , a l
cal l

; h i gh p a r t of t h e B a s e Addr .

Reg .

for CO

s e l e c t i on

push ax

; s ave a x

int

; wa i t s for a key

1 6h

( b l ock l ength )

pop ax
mov dx , O l h

; the addr e s s of

out

; t he Words Coun t e r Reg i s t e r

dx , a l

the port a s s o c i a t e d w i t h

mov a l , ah

; t he l ow byt e o f t h e Words Coun t e r Reg .

out

; high byt e of

dx , a l

mov a l , O
out

O fh , a l

mov a l , O
out

0 8h , al

the Words Coun t e r Reg .

; unma sk a l l channe l s

; a c t ivat e s DMA

ret
PROGRAMM I NG ENDP

75

OMA Data Transfer on PC-A T

WAIT PROC NEAR
etl :
; B IOS keyboard bu f f e r check s e rv i c e

mov ah , l
int 1 6 h

j z et l

; wa i t s unt i l a k e y i s pre s s e d

mov ah , O

; B IOS s e rvi ce ,

et2 :
pre s s e d k e y reading

int 1 6 h
; the pre s s e d key i s compa red to ENTER
; wa i t s f o r ENTER

cmp a l , [ s i ]
j nz e t 2
ret
WAI T END P
DELETE PROC NEAR
mov bh , l e h

; co l o r a t t r i b .

mov cx , O

; the l e f t - up c o rner

mov dh , 2 5

; l ine 2 5

mov d l , 8 0

; co l umn 8 0

mov a l , O

; c l e a r s c reen

mov ah , 6

; s crol l - up B I OS s e rv i c e

int

for s c reen ye l l ow on b l u e

l Oh

ret
DELETE ENDP
SELECT I ON PROC NEAR

mov dx o f f s e t

me s s 3

mov ah , 9

; DOS d i s p l ay f unc t i on

int 2 l h
mov ex , 1 0

; the number t he mu l t ip l i c a t i on i s made

mov s i , 4

; wi th the exp e c t e d numb e r of d i g i t s

e t 3 : mov ah , 1

jz et3

; wa i t i f t he bu f f e r i s empty

mov ah , O l h

; DOS e cho reading funct i on

mov b l , a l

; move al

and b l , O f Oh

; the mos t s ign i f i cant 4 b i t s

cmp b l , 3 0h

; checks

j ne e t 3

; repeat s i f

i t has b e e n p re s s ed wrong

and a l , O f h

; the u s e f u l

i n f orma t i on is

and bx , ax

; bx f-the pre s s e d d ig i t s

to b l
i f t h e d i g i t has been pre s s e d
re t a ined

cmp s i , l

; the l a s t d i g i t

j e et4

; f or the l a s t d i g i t j ump t o the end

mov ax , bx

; move

mov bx , ax

; ex ; / bx mu l t ip l i e d w i t h 1 0

in

ax

i s not mu l t ip l i e d w i t h 1 0

for

the

mu l t ip l i cat i on

w i th

i s done aga in

de e s i
cmp s i , O
et4 :

j ne e t 3

; redo f o r the next d i g i t

mov ax , bx

; ax i s l oaded w i t h t he numbe r o f byt e s

; t o b e t ran s f e rred

SELECT I ON ENDP
CODE ENDS
END MAIN

76

OMA Data Transfer on PC-A T

7.3 Exercise
a.
Analyze the
D MABLOCK.AS M .
b.

above

presented

charts

and

the

program

R u n the program to d o the OMA transfer.

c.
Change the above program so that the transfer is started through the
program (software request).
d.
Write a program that does a OMA transfer i n byte mode according to
the electrical schematic in figure 7.2, using the video memory as
destination .
e.
Propose a progra m that does a 1 6-bit OMA transfer, using the same
practical assembly, in which a change has been made so that the transfer
will be made on channel 5 .
Remark:

1 ) Use the addresses of the registers g iven i n the previous work

2) To load the destination add ress:
- bits 1 - 1 6 in the Base Address Register
- bits 1 7-23 in the Page Register
f.

Draw an electrical schematic for a 1 6-bit OMA transfer.

77

Designing The /SA-Bus Compliant Boards

8 . D ES I G N I N G T H E ISA-BUS C O M P LIANT BOARDS

8 . 1 Buses

in PC

The computer internal components communicate among each other

in d ifferent ways. Most of them (including the processor, the memory, the
extension cards, and the externa l memory devices) communicate through
one or more buses. A bus, i n computer language, represents a set of lines
(conductors) on which the i nfo rmation is passed between two or more
devices. A bus that connects only two devices is sometimes considered a
port. Considering that the processor is the fastest device i n a modern
computer, the buses can be classified using the distance between them
and the processor, the g reater the distance the slower the bus:

Processor bus - represents the bus with the higher level, used by the
chip-set to exchange i nfo rmation with the processor
Cache bus - appears i n recent architectures (used i n Pentiu m Pro and
Pentiu m I I ), being dedicated to system cache memory access. It is
sometimes cal led "backside bus". Main boards from the 5-th generation
used by conventional processors have the cache memory connected to
the standard memory bus
Memory bus - is a level 2 bus, which con nects the system memory to
the chip-set and processor. I n some systems, the memory bus and the
processor bus are one and the same
Local 1/0 bus - is a high speed 1/0 bus used to con nect to the memory,
to the processor and to the chip-set system the peri pheral devices
whose performances are critical . Video cards, d isks or speed network
i nterfaces are using this type of buses. The most used 1/0 buses of this
type are : VLBus (Video Local Bus or VESA) and PCI (Peripheral
Component I ntercon nect) bus.
Standard 1/0 bus - is the oldest 1/0 bus used by slow peripheral
devices (mouse, modem, sound cards, slow network cards). This is the
I SA bus (Industry Standard Architecture) or AT bus.

In recent computers, an additional bus especially designed fo r

graphical communications is used . It is in fact an AGP port (Accelerated
Graphics Port), because it connects only two devices.
Each bus has two distinct parts: the data bus which represents the lines on
which the data transfer are made and the address bus, which indicates the
place where the i nformation is transferred . There are a lso some control
79

Designing The /SA -Bus Compliant Boards

lines, controlling the bus functions, sometimes named control bus and
sometimes not mentioned .
A bus is characterized by:

Bus width : refers usually to the data part. If the bus is large, more
information can circulate on it, having a better performance . The original
ISA bus had 8 bits and ISA-AT, 1 6 bits . The other 1/0 buses (including
VLB and PC I ) have 32 bits. Memory and processor buses, beginning
with Penti u m , have 64 bits. The width of the address bus is separately
specified and it refers to the number of d ifferent locations in which , or
from which , data can be transferred .

Speed : indicates the binary flux on each bus line. Most of the buses are
transmitting 1 bit data /line /cycle, but the new buses like AGP can
transmit 2 bits data /line /cycle, thus doubling the performances. The old
buses l i ke I SA can transfer only 1 bit /line i n two clock cycles, halving
the performances.

Band (debit) of the bus indicates the quantity of the data that can be
transferred theoretically by the bus in a g iven unit of time . Making the
comparison with a highway, if the width is given by the n umber of road
bands and the speed represents how fast the cars are drive n , the band
will be g iven by the multiplication of these two and represents the traffic
value which the channel allows in 1 second . The next table indicates
the theoretical bands of the most used 1/0 buses, but practically these
val ues cannot be achieved from d ifferent reasons. For example, in the
case of ISA bus, the band should be of almost 8 M bytes/s, but in reality,
there are wait states introd uced on the 1/0 cycles, which are red ucing
th is value.

BUS
I SA- 8 ( XT )
I SA - 1 6 ( AT )
E I SA
VLB
PCI
PCI 2 . 1 - 6 4 b i t s
AGP

WIDTH
(BITS )

SPEED
( Mb / S )

BAND
( MB / S )

8
16
32
32
32
64
32

8.3
8.3
8.3
33
33
66
66

7.9
15 . 9
31 . 8
127 . 2
127 . 2
508 . 6
2 54 . 3

Table 8 . 1 The PC buses performances

80

Designing The /SA -Bus Compliant Boards

Cache
Memory

Sys t em
Memory

Video
Adap t e

( DRAM )

PCI MEMORY BUS

PCI
Chip - s e t

PCI S l o t s
I / O PCI BUS

EIDE
Con t ro l l er
I SA/ E I SA S l o t s

I SA/ E I SA
BUS

Fig . 8 . 1 Buses in PC

I n a system that has more buses, the connections g iven by the chip-set
must allow the connection of the devices to the buses and the transfer
between devices con nected to different buses. The device that allows
passi ng from one bus to another is named "bridge" . The best known is the
PCl-ISA Bridge, which is part of the system chip-set at Penti u m and
Penti umPro PC. PCI bus has also a bridge to the processor bus, which can
be fou nd i n Windows 95 at "Device Manager" >"System devices" .

8.2 The ISA bus

The I SA bus recommended by I B M is a synch ronous bus, which
means that all generated cycles are following a fixed clock of 8.33 M Hz.
Working i n this way, the bus is less flexible according to the transfer rate,
but allows the development of simple devices. The real band of the bus is
smaller than the one from the table 1 , reaching -5 M b/s for 8-bit bus and 1 0 M b/s for the 1 6-bit bus. Despite this reduced performance (enough for
some applications) the I SA bus is kept in the computer due to the simplicity
of the peripheral devices i mplementation and to the large boards supply on
the market.
In the table below there are presented the bus signals and the con nectors
are presented i n the appendix. The "low" active signals are followed by "-".
81

Designing The /SA-Bus Compliant Boards

Signals type is seen from the main PC board . A board connected to the bus
cannot get the control of the bus; this means that it cannot generate cycles
fo r reading and writing on its own , so it cannot be a master device . A slave
device can i nitiate a transfer cycle indirectly, by sending a OMA request to
the D MAC ( 1 8237A), but this one wil l manipulate the control signals. Bus
signals are TTL compatible.

SIGNAL

CONNECTOR
PIN

DESCRIPTION

TYPE

s igni f i cant
20
of
bits
Less
the
addre s s bus wh i c h d i r e c t t h e f i rs t
Mbyte o f memory and are va l i d on the
f a l l ing edge o f the s i gna l .
the
s igna l
DMAC
When
is
act ive ,
cont rol s the bus . The I / O addr e s s
decoders are u s i ng thi s s igna l t o
ignore the DMA t rans f e r cyc l e s .
Indi c a t e s that the addre s s s igna l s
are val i d and ready t o be decoded .
ALE i s forced t o " l " dur ing the DMA
cyc l e s .
sys t em
c l ock
MH z
The
with
8 . 33
f requency and 1 / 2
f i l l ing
factor .
syst ems
Some
can
have
d i f f e rent
f requency .

A1 9 -AO
{ addre s s )

A1 2 - A2 1

OUT

AEN
{ addre s s
enab l e )

Al l

OUT

ALE
{ addre s s
l at c h
enab l e )

B2 8

OUT

CLK
{ c l ock )

B2 0

OUT

A2 - A 9

I/O

The l e s s s ign i f i cant 8 b i t s o f dat a .

OUT

The s e s i gna l s indi c a t e t h a t DRQ i was

{ DACKi )
accepted
and
the
data
can
t ake
t ran s f e r
p l ac e
on
the
s e l e c t e d channe l .

D9 , B6 , B1 6
Bl8 ;
Dl l , D1 3 , D
15

IN

reque s t s
DMA
s ent
to
the
DMA
cont rol l e r a s k a channe l f o r da t a
t rans f e r . Channe l s 0 - 3 are for 8 - b i t
5-7
t ran s f e r s
channe l s
for
1 6 -bit
t rans f e r s . DRQ i s igna l mu s t b e kept
act ive unt i l DACKi become s a c t ive , or
e l s e the DMA reque s t i s i gnored .

Al

IN

Announces t he exi s t ence o f a n e rror ,

such a s par i t y e rror , and gene r a t e s a
NM I reque s t .

D7 - D O
{ dat a )
DACK0-3
DACK 5-7
{ DMAack )
DRQ 0 - 3
DRQ 5 - 7
{ DMA
reque s t )

I / O CHCK{ I/O
channe l
che ck )

D8 , B1 5 , Bl
7'
B2 6 ;
D1 0 , D12 , D
14

82

Designing The /SA-Bus Compliant Boards

I / OCH RDY
( I /O
channe l
ready )

Al O

IN

Used to int roduce wa i t s t a t e s in the

I/O
cyc l e s .
The
wa i t
states
are
inserted when the s i gna l i s inact ive
( mu s t b e kept on 0 at l e a s t 2 . 5 s ) .
The
s igna l wi l l not be a c t ivated
s imu l t aneou s l y
with
- o ws
for
not
c reat ing
probl ems
to
t he
bus
cont rol l e r .

D2

IN

Ind i c a t e s that the dev i c e support s

I / O cyc l e on 1 6 b i t s w i t h a wa i t
state .

Bl4

OUT

Bl3

OUT

I O CS 1 6 -

I / O 16 b i t

hip

elect )

!OR( I/O
read )
! OW ( I/O
wri t e )
I RQ 9 ,
I RQ3 - 7 ,
RQ 1 0 - 1 2 ,
IRQ 1 4 - 1 5
LA2 3 LA1 7
( l a t c hab l e
addre s s )

MASTER MEMCS 1 6 ( Memory 1 6

b i t chip
select )
MEMR ( Memory
read )
MEMW ( Memory
wr i t e )
ows -

(No wa i t
state s )
osc

(Oscilla
tor )
REFRESH RESET DRV
( Re s e t

4 , B2 1 - B 2 5 ,
D3 - D 7

IN

The s igna l i s a c t ive when a

want s t o read dat a f rom another
through the I / O space .
The s igna l i s a c t ive when a
want s to wr i t e da t a f rom another
through the I / O space .
Indicate
that
a
dev i c e
perf orm an I / O operat i on .

wan t s

un i t
un i t
un i t
un i t

to

The s e
s i gna l s
don ' t
pass
through
l a t ches and are va l i d when ALE pa s s e s
t o 1 . Us ing t hem t ogether w i th the
other addre s s l i n e s , one c an addre s s
16
Mbyt e s .
The s e
s i gna l s
c an
be
memori zed in l a t ches on ALE f a l l ing
edge .
The s ignal i s u s e d t oge ther with DRQ
for taking cont rol ove r the sys t em .

C2 - C 8

OUT

Dl7

IN

Dl

IN

C9

OUT

a c t ive
Is
cyc l e s .

in

all

memory

reading

ClO

OUT

act ive
Is
cyc l e s .

in

all

memory

wr i t i ng

BS

IN

B3 0

OUT

Bl9

OUT

B2

OUT

ext e rn a l
I nd i c a t e s
that
the
permi t s memory a c c e s s cyc l e s
b i t s w i t h a wa i t s t a t e .

board
on 1 6

Thi s s igna l can be u s e d t o i nva l ida t e

int roduced ,
imp l i c i t ly
states
wa i t
imp roving the sys t em p e r f o rmanc e s .
14 . 3 18
with
s i gna l
C l ock
f requency and 5 0 % f i l l ing f a c t o r .

MH z

I nd i c a t e s a r e f r e s h cyc l e exe cut ion .

the who l e
reset
of
the
Indi c a t e s
sys t em .

83

Designing The /SA-Bus Compliant Boards

drive r )
SBHE ( Sy s t em
bus h i gh
enab l e )

Cl

OUT

SD8 - SD 1 5
( Sy s t em
dat a )

Cl l - Cl 8

I /O

Bl2

OUT

Bll

OUT

TC -

B2 7

OUT

+ SV=

B3 , B2 9 , Dl
6

- 5V=

BS

B9

SMEMR ( s y s t em
mem . read )

SMEMW ( Sys t em
em . wr i t e )

+ 1 2V=
- 1 2V=
GND

B7
Bl , B3 1 , Dl 8

i t ind i c a t e s dat a
When i s a c t ive ,
t rans f e r on SDB - 1 5 and i f the addre s s
i s even , the t rans f e r i s made on 1 6
b i t s ; when the addre s s i s odd - on 8
bits .
Are the mos t s i gni f i c ant 8 b i t s o f
the da t a bus . On ly the dev i c e s that
a l l ow 1 6 - b i t t ran s f e r s u s e them .
I s act ive at the memo ry reading w i t h
f i rs t
p l aced
addre s s
in
the
the
memory Mbyt e .
I t i s act ive at the memory wr i t ing
with the addre s s p l aced i n the f i r s t
memory Mbyt e .
An impu l s e on t h i s p i n ind i c a t e s the
ending of t rans f e r s on one of the DMA
con t ro l l e r channe l s . The chann e l i s
by
t e s t i ng
the
DACK
de t e rmined
s igna l s .
In range 4 . 7 5V - 5 . 2 5 v a t a current
< 1 9 . 8A
In range - 5 . SV - - 4 . 5 v at a current
< 0 . 3A
In range l l . 4 V - 1 2 . 6 V at a current <
7 . 3A
In range - 1 3 . 2V - - 1 0 . 8 V at a current
< 0 . 3A

Table 8 . 2 The

I SA

bus signal s

8.3 General considerations for desi g n i n g a board on ISA-bus

I ntel processors from 80x86 family can address an 1/0 zone of
64Kports, using the less significant 1 6 address li nes AO-A 1 5; sti l l , a lot of
devices use only the fi rst 1 0 lines AO-A9, red ucing the 1/0 space to 0-3FFh.
I n the appendix the ports map is presented ; certain ports are reserved for
different PC devices. Figure 8.2 presents the time charts for 1/0 bus cycles.
The selection of an i nterface board ( circuit, port ) consists i n generating a
selection signal by decoding the address combination from the address
bus, signal that validates some circuits and allows the data transfer
between the board and the centra l unit. The address combination that
selects the board must be unique and not used on other combinations in
PC. Address signals from the bus are used for add ressing memory or 1/0
ports . The distiction between the memory addresses and the port ones is
made by M E M R , M E MW and IOR, I OW signals. The l i nes IOR and I OW
84

Designing The /SA-Bus Compliant Boards

are activated by the instructions I N or OUT (or by i nportb (address) and

outportb (address, data) in C language).
Usually, the signals used for decoding at simple ports {latches, buffers) are :

Addresses AO-A9

I O R or/and I OW

AE N
I n the case of the programmable interfaces, a part of the add ress lines
(AO . . . ) from the bus are connected directly on the correspond ing pins of the
interface, to address the available ports of the circuit and I O R , I OW signals.
U nconnected addresses and the signal AEN wil l be inputs fo r the decoding
circuit whose output wil l command the CS signal of the i nterface .
Decoding circuits can be designed using:
Logical gates

Decoders (74LS 1 38 , 74LS42, 74LS 1 54 . . . )

Logical comparators (74LS85, 74LS . . . )

E/PROM memories

AEN= O
ALE

ADDR .

___)--)
l O On s

/ I OW or / I OR
DATA ( / I OR )
DATA ( / I
>
_o
_w
_

\__

\
> 5 5 0n s

-------/
: < l l O n s ...

__
_
_

VAL I D DATA

VAL I D DATA

WRI TE TO OUT PORT

\._

_
_
_
_

\_

Fig . 8 . 2 I/O cycle for the I SA bus

An example of address decoder used for the selection of the

programmable i nterface 1 8253 , placed on a board con nected on the I SA
bus, with initial address 1 OOh , is the one from "The timer circuit " i n which
the above considerations are applied .
I n this paperwork (see figure 8.3) the selection of the ports realized
with register 74LS373 , at address 30Eh and 30Fh is made using the
EEPRO M 1 28 1 6 memory (2Kbytes) as a decoder. The connections used at
85

Designing The /SA-Bus Complian t Boards

the memory are: address lines AO-A1 0, signal AEN to /CE and I OW to /OE .
The data is loaded to the ports o n the negative edge g iven by the data bits
DO or 0 1 con nected to the G inputs of the register (on level " 1 " the outputs
follow the inputs), when one of the memory locations with address 30Eh or
30Fh was addressed . The locations' content is 01 h (00= 1 ), respectively
02h ( 0 1 = 1 ).

8.4 Appl ication

The schematic from figure 8.3 represents the electrical scheme of the
circuit implemented on a board (8 bits), connected on the I SA bus. The
scheme represents a circuit used to generate signals of variable form ,
amplitude and frequency.
On both latches A, B ( port 30Eh and 30Fh ) a digital analog converter DAC
08 is connected . The first converter has a reference of 1 0 V and it is used
in an u n i polar con nection to generate a variable reference for the second
DAC 08, allowing to obtain a variable amplitude for the generated signal .
The second converter is used to generate the signa l , being used in a
bipolar con nection , allowing to obtain a bipolar signal at the current-voltage
converter output realized with LF1 57.
For the presented scheme a program was written for generating a
sinusoidal signal with variable frequency and variable amplitude. The
application allows also to choose the accuracy of the signal syntesis by
selecting the number of samples /period . For setting the frequency with
which the samples will be generated , interru ptions generated by channel O
of the timer circuit 8253 are used .

8.5 Exercise
a. Analyze the electrical schematic from figure 8.3, the role of the signals
from the bus and compute the maximum amplitude (V-V) that can be
generated using the circuit.
b. Analyze and execute the program S I N U S . C and determine the
frequency l i mit of the signal that can be generated using this program.
Analyze the dependence of the frequency limit on the resol ution used i n
generating the signal (number of samples/period) .

86

Designing The /SA-Bus Compliant Boards

c. Write the following applications i n C or assembling, which wil l allow to

generate signals of variable amplitude and frequency with the next
wave forms:

Rectangular

Triangle

Random

Saw-tooth .
8 - bit
Digital
Ana l og
Converter

R6

+1 2V

2 ---.,._,
1 2,....,

11
5
10
6
9
9
,_..,
--__,,....,
12
8
1-7.;----;
1 5,__
7
1-7.
_--:-;
6
16
,_.,.,----:-1
19
5
1-'-'-

-;

4k

C3

- 1 2V

BpF

OAC08

B81 J O U T
87

BS

t-4----.....,

85 I OUT. D"----
B4
83
82 COMP I-'-''--
81
+ 1 2V

+ 1 2V

g g t-+--6-;
'-++-!-+-+-+---:-l
2

02
'-+--+-<-+--'-""' 0 3
'-++-f---i7-l 04
05

'-+----.;-;;,;

12

8 -bit Digital
Analog
A
Conve r t e r

02
9
9
03 >-=-____,_,
8
12
04 l--7i;----;
15
7
05
6
16
----.;,;
i-;;
5
1 9.--

gr g

----,-,u OC
G

4K7

R8

813

21<2

Vee

2816

Fig . 8 . 3 The electrical schematic of the application

87

Designing The /SA-Bus Compliant Boards

S inus Generator Program - SINUS . C

#pragma i n l ine
# inc lude < s t d i o . h >
# i nc lude < c on i o . h >
# i nc lude < do s . h >
# inc lude <math . h >
vo i d interrupt ( *v_int ) ( )
vo i d interrup t Gen_s in ( )
vo i d prg_t ime ( i nt ) ;
vo i d res_t ime ( vo i d ) ;
int t = O , s t ep s = 1 2 8 , f ;
char t ab l e [ 2 5 6 ) ;

/ / func t i on p o i n t e r
/ / s inus gene rator interrupt prototype

vo i d t ab l e_s i n ( vo i d )

int i ;
f o r ( i = O ; i < s t eps ; i + + )

t ab l e [ i ) = l 2 B * ( l + s in ( 2 * 3 . 1 4 1 5 9 / s t ep s * i ) ) ;
/ / end s inus values t ab l e

vo i d ma in ( vo i d )

f l oat v ;
uns igned int vv ;
char i = ' d ' ;
clrscr ( ) ;
v_int =getve c t ( B ) ;

/ / t ake type 8 i n t e rrupt f rom the t i mer

( I RQ O )
s e tve c t ( B , Gen_s i n ) ; / / put the new i n t e r rup t
wh i l e

( i== ' d ' l {

outport ( Ox2 1 , 1 ) ;
/ /ma sk I RQ O
p r i n t f ( " \ n \ t S i nus amp l i tude ( < 1 7 . 5V ) = " ) ;
s c anf ( " % f " , &v ) ;
v= 2 5 6 - ( 2 5 5 * v/ 1 7 . 5 ) ; / / c a l cu l a t e value f o r 0 - 2 5 5 s c a l e
vv=v ;
asm

/ / knowing Vvv= 1 7 . 5V and the i nput value v

mov dx , Ox3 0 e
mov ax , vv
out dx , a l

/ /vo l t age r e f erence adj us tment

p r i nt f ( " \ n \ tNumb e r of s amp l e s / p e r i o d

") ;
" , s t ep s ) ;
print f ( " %d , ( < =2 5 6 )
s canf ( 11 % d 1 1 , & s t ep s ) ;
t ab l e s in ( ) ;
/ / s amp l e s t ab l e generat ing func t i on
pr int f ( " \ n \ t S i gna l f requency=
") ;
s c anf ( 11 % d 11 , & f ) ;
p rg_t ime ( f ) ;
outport ( Ox2 1 , 0 ) ;
/ / unma sk IRQO

88

Designing The /SA-Bus Compliant Boards

p r int f ( " \ t Cont i nue ? d / n " ) ;
i =g e t che ( ) ;
/ / end whi l e
s e tve c t ( B , v_int ) ;
/ / re l oad o l d interrup t
r e s t ime ( ) ;
/ / end ma in
}
vo i d i n t e r rupt Gen s in ( vo i d )
-

etl :

a s rn {

mov
mov
mov
out
inc
rnov
dee
crnp
j le
mov

/ / s inus generat i on i n t e r rupt func t i on

dx , Ox3 0 f
bx , t
a l , t ab l e [bx)
dx , a l
bx
dx , s t ep s
dx
bx , dx
etl
bx , O

/ / port f o r s amp l e s
/ / t - t ime
/ / t ake s amp l e f rom t ab l e
/ / out t o port
//t=t+l
/ / l oad numb e r o f s t e p s f o r
/ / t ab l e end
t e s t ing

II

/ / t ime r e s e t

a s rn
mov t , bx
mov dx , O x2 0
rnov a l , Ox2 0
out dx , a l

vo i d prg_t ime

/ / redo t ime i n C
/ / i n t e r rupt d i s charge
EOI ( ou t 2 0H , 2 0 H )

II

/ / t imer programm i ng func t i on

(f)

int a , a l , a2 ;
a = ( l l 9 3 1 . 8 / s t ep s / f ) * l 0 0 ;
al=a%2 56 ;
a 2 = a/ 2 5 6 ;
_BL = a l ;
_BH= a 2 ;
asm
mov ax , Ox3 6
mov dx , Ox4 3

/ / l ow byt e
/ / high byt e

; / / t ime r mode word 0 0 1 1 0 1 1 0 = 3 6 h :

; / / 0 0 - channe l O ; l l - R / W l ow t hen

high
; / / oc t e t ; O l l - re c t angu l ar s i gna l ;
/ / 0 - b inary ; T imer - po r t 4 3 h

out dx , a l
mov
mov
out
mov
out

dx , Ox4 0
ax , bx
dx , a l
a l , ah
dx , a l

/ / Low
/ / H igh

/ / end prg_t ime

89

Designing The /SA-Bus Compliant Boards

vo id res t ime ( vo i d )

asm
mov ax , Ox3 6
mov dx , Ox4 3
out dx , a l
mov
mov
out
out

dx ,
ax ,
dx ,
dx ,

Ox4 0
OxO O
al
al

; / / t ime r cont rol word 0 0 1 1 0 1 1 0 = 3 6 h :

; / / 0 0 - channe l 0 ; 1 1 - R/W l ow/h igh byt e
; / / 0 1 1 - re c t angu l a r s i gna l
; / / 0 - b inary ; T ime r - port 4 3 h

/ / Low
/ / H i gh

/ / end r e s t ime

90

The Parallel Port in IBM-PC Computers

9 . TH E PARA L L E L PORT I N I B M -PC C O M P UTERS

9 . 1 General ities regard i ng the paral lel port

The PC parallel port has been used since the development of the first
one for the communication between the PC and the pri nter device. Initially,
the printers were connected to the PC through serial i nterfaces, but later,
due to the technology development, the pri nters got faster and faster and
the serial transmission were replaced by the parallel one.
As the number of PCs increased , the number of peripheral devices
using the parallel port increased also, and the parallel port evolved , getting
new facilities but still keeping the compatibility with the i n itial model . At first,
the connection between the PC and the pri nter did not need reverse data
transmission , from the printer to the PC, the parallel port having only one
way data signals. Along with the diversification of the peripherals, the need
of bidirectional data transmission appeared . This was first possible in I B M
PS2 computers, which allowed the setting of the transmission d i rection by
setting the 5-th bit in the control register, allowing the outputs of the data
output register to be in high impedance state , thus being able to read the
signals applied on the data l ines by the reaction register. Afterwards, new
types of parallel ports appeared , offeri ng, beside the possibility of
bidirectional 8-bit data transfer, other facilities increase the transfer rate and
even lead to the possibility of connecti ng several peripherals on the same
bus. Thus, beside the Standard Parallel Port (SPP), improved parallel ports
also appeared : EPP - Enhanced Parallel Port, used especially by
peripherals such as tape units, portable CD-ROM u nits or network
adapters, and ECP - Extended Capability Port, which allows connecting
several peripherals, being used mainly by the new generation peripherals:
scan ners, ultrafast pri nters etc.

9.2. The Standard Paral lel Port (SPP)

The standard connector of the parallel port is of DB 25S (mother) type with
25 contacts , and is placed on the backboard of the PC. The con nection to
the printer is done through a cable (L<2m), with a DB 25P(father) connector
toward the PC and a 36-pi n Centronics connector toward the printer. The
signals used can be grouped as follows:

91

The Parallel Port in IBM-PC Computers

8 d ata lines (DO - D7)

5 status lines (S3 - S7)
4 control l ines (CO - C3)

The correspondence between the signals and the pins (from both
kinds of con nectors) and the bits of the registers, as well as their
significance in the standard mode (SPP) are described in table 9 . 1 .
T_- !J?t,Jal be1_$_i!_cl.dresses of the parallel ports i n the PCs a re:
3bch - address used by the M DA adapters and the pri nter
378h - the pri nter interface address
278h - the printer interface address
DB 2 5
Pin

Centronics
Pin

SPP Pin
Signi ficance

Regis ter
bit

In/Out

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18-25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
36
1 9 - 3 0 , 33 , 17 , 16

- S t robe
Dat a O
Dat a l
Data2
Dat a3
Data4
Dat a5
Dat a 6
Da t a 7
- Ack
Busy
PaperFeed
S e l e c t Ou t
-Aut o f e e d
- Error
- Init
- Se l in
GND

co -

SS
S4
Cl S3
C2
C3 -

Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
Out
In
Out
Out

DO
Dl
D2
D3
D4
DS
D6
D7
S6
S7 -

Table 9 . 1 SPP pins and the ass igned signals

The convention s used in the physical description of the port are:
'-' in front of the signals means that the signal is active "low"
'-' following bits of the different registers means that the value of the bit
(from the registe r of the parallel port) corresponding to the signal has been
reversed .

The ROM-B I OS reserves four 1 6-bit words i n the RAM memory,

h
starting from the address 0:408h, wh e re it saves t e base addresses of the
parallel ports d etected afte r reset. The DOS operating system and the
B I OS functions use these addresses, assigning them to standard devices
92

The Parallel Port in IBM-PC Computers

for LPT1 , LPT2 and LPT3 printers respectively. The address of the fourth
device LPT4 is not a standard one. Thus, using the B I O S table described
above, one can reassign the addresses of the standard LPT logical
devices. The signals presented in table 9. 1 are assigned to the bits in the
registers (ports) that make up the hard/soft interface of the parallel port.
Their configuration will be presented shortly.
Data register (Base Address)
D7

D6

D4

DS

D3

D2

Dl

DO

Data 7 I Data6 I DataS I Data4 I Data3 I Data2 I Datal I DataO

This register keeps the data_to_be-1ransmitted . The outputs of the

parallel port corresponding to this register are
- eTIL_Je_veLoutputs. The port
e
also has a rea_c;tion register_ which allows th r ading of the data written . I n
case of P S 2 computers the data port is bidirectional; t h e direction of the
dataflow may be reversed through bit 5 of the control register, thus enabling
the reading of data introd uced from outside.
Status register (Base Address +1 )
S7

S6

S4

SS

Busy I -Ack I PaperEnd I SelOut

S3

- Error

S2 I Sl I S O

From this register the _peri pheral status signI a re read. For the Standard
Parallel Port, these signals have the following significance :

Busy - if it is "O" the printer is busy or the buffer is full

1 0 ms long negative ("O") impulse given by the printer which means that
the last character sent has been received
PaperEnd if it is " 1 " the printer is out of paper
SelOut - if it is " 1 " the printer is selected
-Error if it is "O" an error appeared while printing, the printer is not operational
or it has no paper
-Ack

Control Register (Base Address +2)

C7 I C6 I CS

C4

C2

C3

Dir I IrqEn I - Selin

93

Cl

- Init I - Autofeed

co

- Strobe

The Parallel Port in IBM-PC Computers

Irq 7
----1

IrqEn

'-----11<'--- -Ack
DE--- -Error
,..___
_
SeIOut
--
B A SE

A D D R+ l

PaperTud
,-- Busy

S7 =Busy
S6 = A c k

System
BUS

S5 = P ap e r E n d
S4 =Se l 0 ut
S3 = E r r o r

B A SE
A D D R+2
C O = - St r o be
C l = - A ut o feec
C2 = l n i t
C3 =-Selin

-Strobe
o--- -Auto
-Init
o--- -Selin

IrqEn*

C 4 = l rqEn
CS=Dir*

DIR
B A SE A D D R

1----
D 7 =D at a 7
D 6 = D at a6
D 5 =D a t a 5

Data7

Data6
1----4 Data5
1----4 Data4
--

,___

Data3

D 3 =D a t a 3

1----4 Data2

D 2=Data2

DataO

D 4 = D at a 4

Datal

D l = D at a l
D O = D at a O

Fig . 9 . 1 The block diagram of the SPP for IBM PC/PS2

D i r selects the d i rection of the data signals: "O " = output, " 1 " = input (only for
bidirectional ports - PS2)
l rqEn validates the apparition of the hardware interrupt on I RQ7, on the rising
edge of the Ack signal (" 1 " = validate l rq7; "O" = invalidate l rq7).
-Se l i n - if set to " 1 " it allows to activate/deactivate the printer by using
DC 1 /DC3 codes
-l n it - through a "O" impulse longer than 50 s, the printer is initialized
-Autofeed - if set to " 1 " , the printer moves to a new line after receiving a CR
-Strobe - through a " 1 " impulse at least 1 s long , the printer is announced that
there is a new valid data on the data l i nes.

94

The Parallel Port in IBM-PC Computers

The signal d iagram in the case of data transfer from the

presented i n fig .9.2:
1 The data register is written
2. The Bus y signal in the status register is checked
3. If Bus y is not active, the signal -Strobe in the
activated
4. If Busy is active, the -Strobe signal is deactivated .
becomes active, the receiving of the byte by the printer
PC.

PC to the printer is

DO-D7 [[X
I

Bl.SY

-S'IROBE
-ACK

i
i

When -Ack signal

is confirmed to the

3
I

VA L i

control register is

DAT A

I
I

i
i

Fig . 9 . 2 Data trans fer cycle toward the printer

9.3 Data transfer modes between standard ports

For data transfer between two systems using standard parallel ports
there are three connection modes:
Mode1 i n which the data is transferred on 4 bits, is done by con necting bits
00-04 (or 03-07) of the first port data register with bits S3-S7 of the
second port status register and vice-versa. Bits 00-03 con nected to S3-S6
transport the data , and 04/S? are used for synchronization.
Mode2 can be used only by bidirectional ports (PS/2), where 8-bit transfers
are possible. The receiving port must be passed into high i mpedance state
(by setting bit C5 to 1 ) thus enabling the reading of the byte received from
the sender, through the reaction register.
,

Mode3 uses for the i nput 4 bits from the .GQD.trol port and 4 .btts. otthe. state.
port, thus enabling bidirectional 8-bit .kcir.ifrs on any PP. I n this case, the
control outputs must be set to i'1'; ( C O=C 1 =C3=0 an d C2= 1 ) , because, as
they are open-collector outputs, they can be commanded to "O" by an
external device without destructive effects. The reaction register of the
control port, keeping in mind the fact that bits CO, C 1 and C3 have been
reversed , can read these outputs.
95

The Parallel Port in IBM-PC Computers

9.4 Parallel port-related BIOS services

Two interrupts have been reserved for the parallel port: hardware i nterrupt
07h , with i nterrupt vector 07h , and I NT 1 7h , wh ich allows the access to
several B I OS pri nter specific services:
Function OOh
character output, sends a character to one of the printers
connected to the PC
Inputs: AH = 00; AL = the code of the character for pri nting; DX= the
number of the pri nter
Outputs: Atl = the status of the printer
Remarks: The first printer connected to the PC has the n u mber 0 .
The content o f the registers BX, CX, DX, S I , D I , BP a n d of the segment
reg isters does not change.
The significance of the bits in the status byte is explained below:
-

B7

B6

-Busy Ack

B5

B4

PEnd Online

B3

Error

B2

Bl

BO

Timeout

Online = 1 printer selected

f:.rror = 1 transmission error
Tout = 1 Timeout error

-Busy = 0 busy pri nter

Ack = 1 character received
PEnd = 1 no paper

Beg i n n i n g with the address 0 :478h, on the next three bytes there a re
stored the Time-Out counters for the parallel interfaces that keep track of
the fai led transmission attempts.
Function 01 h

PC.

i n it printer, initializes one of the pri nters connected to the

Inputs: AH = 0 1 ; DX = the number of the pri nter;

Outputs: H = the status of the pri nter;

Remarks: same as for the previous function .

Function 02h

testi ng the status of the pri nter. The PC reads the status of

the printer.
Inputs: AH = 02; DX = the number of the printer
Outputs: AH = the status of the printer
Remarks: same as for function Oh .

96

The Parallel Port in IBM-PC Computers

9.5 Extensions of the paral lel port

The communication modes on the parallel port have been
standard ized in the I E E E 1 284/1 994 standard , called " Standard Signaling
Method for a Bidirectional Parallel Peripheral Interface for PC" . The
standard defi nes _5 transfer modes that ensure the creation of a direct
transmission channel (from the PC to the peripheral), a reverse one (from
the peripheral to the PC), or a bidirectional one (b_alf-:cl LJJ>le x ).
The transmission modes defined by the standard are the fol lowing:

The Centronics or compatibility mode, used by the standard parallel

port

The ' N i bble' 4-bit transfer mode, which uses the status lines as a
reverse communication channel

The 'Byte' or 8-bit transfer mode, used for bidirectional 8 - bit

transmission , which was used in the first bidirectional ports

The E P P mode, used by EPP ports

The ECP mode, used by ECP ports

The first two of these communication modes use the classic parallel port,
wh ile the thi rd uses the parallel port specific to I B M PS/2 . The last two
modes use parallel ports implemented using chips that respect the i E E E
1 284 standard . Beside the standard port, the improved ports have a
number of extra registers. For fu rther detail, consult the references.

9.6 Application
The suggested application presents how to command of a LCD using
the parallel port of the PC. The connection schematic is presented in
fig . 9 . 3 . To command the LCD data lines the parallel port data register was
used (DO-D7) , the R/W line is connected to the ground because only write
operations are done, RS is con nected to Selectin ( 1 7 ) and Enable From
LCD to Strobe (1 ). The supply source is of 9V, its voltage being stabilized at
+5V using a LM7805 circuit. The LCD contrast is adjusted through a 5Kn
potentiometer con nected to V0 (3).

97

The Parallel Port in IBM-PC Computers

LM7805

U1
1

9V

De

VIN

P1

-c;'
0

"'

0
-

DO
DI
Dl
-ilHUlD.
D3
D4

0
0

C3

1 00n

"'

,.4EL

1
- 2
- 3
4
- 5
- 6

I
I

no

21
9
72

0-

'
10

l___<;

"'

1
1
T
C2

5k

1 -Strobe
14
15
J
16
4
17
5
18
6
19
7
20

R1

"

47uF

0
z

C1

VOUT

II

8
9
10
- 11
12
13
14

D7

LCD

24

*4< GND

Fig . 9 . 3 The appl ication electrical schematic

The program lcd 1 6.asm that commands the LCD displays the text
"*Test Message! *".

T I TLE LCD D I S PLAY CONNECTED O N THE PARRALEL PORT

; -------------------------- -----------------------ST IVA
SEGMENT PARA STACK ' STACK '
dup ( )
256
dw
ST IVA
ENDS
------------------------ -- ------; - -------- DATA
SEGMENT PARA PUBL I C ' DATA '
PORT l
0 3 7 Bh
; used para l l e l port b a s e addr e s s
dw
PORT2
0 3 7Ah ;
para l l e l port cont rol r eg i s t er addre s s
dw
va l
3 B h , O f h , O lh ; commands
dw
, * , , ,T,
e, , ,81 , ,t1 , , , , ,M, , ,e,
prim
dw
' ! ' , '*'
' s' , 's' , 1a' , 'g' , 'e' , '
sec
dw
' " *T e s t me s s age ! * " wi l l be d i s p l ayed on the LCD ' , ' $ '
t ext l
db
DATA
ENDS
-

- -

; ---------

---

- -

- -

---------------

98

----

- - - - -

-------

The Parallel Port in IBM-PC Computers

CODE
MAIN

MAI N
;

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

c l rscr

c l rs c r

'

SEGMENT - PARA PUBL I C ' CODE '

PROC FAR
ASSUME S S : STIVA , DS : DATA , CS : CODE , ES : NOTH I NG
push ds
xor
ax , ax
push ax
ax , DATA
mov
mov
ds , ax
cal l
c l rscr
; c l e ar s c reen
cal l displ
; di sp l ay program comment
ca l l i n i t
; in i t i a l i z e LCD
c a l l wr i t e
; wr i t e a t ext on the LCD
int 1 6 h
; wa i t for a key
mov dx , [ PORT2 ]
; c l e a r s c reen procedure
mov ax , 2 5 4
; s e l e c t s ins t ruc t i on regi s t e r
out dx , ax
; and STROBE = l , LCD a c t iva t e d
c a l l de l ay
mov dx , [ PORT l ]
mov ax , l
; c l ea r s c reen
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , l
out dx , ax
mov ah , 4 ch
; ex i t to Dos :
xor a l , a l
int
2 lh
RET
ENDP
p r o c near
pus ha
mov ah , 0 6 h
mov a l , 2 6
mov bh , 0 7 h
mov
mov
int
pop a
ret
endp

; c l e a r s c reen procedure

; co l or a t t r ibute
; ( wh i t e l e t t e r s , b l ack background )

cx , O O O O h
dx , 0 1 8 4 fh
l Oh

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

wr i t e

p roc near
mov dx , [ PORT2 ]
mov ax , 2 5 4
out dx , ax
c a l l de l ay
mov dx , [ PORT l ]
mov ax , B O h

; LCD wr i t ing procedure

; in s t ruc t i on reg i s t e r is s e l e c t e d

; s et DDRAM addre s s f rom whe re

; the f i r s t 8 char a c t e r s

99

The Parallel Port in IBM-PC Computers

etl :

out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , 1
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , O
out dx , ax
c a l l de l a y
mov s i , O
mov dx , [ PORT l ]
mov ax , p r im [ s i ]
out dx , ax
mov dx , [ PORT2 ]
mov ax , 1
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , O
out dx , ax
c a l l de l ay
add s i , 2
,...., ....... ,......
'- " '.t-'

et2 :

Cl ..;

-- ,

; w i l l be read

; da t a reg i s t e r is s e l e c t e d

; wr i t e , o n e b y one ,
; t he chara c t e r s f rom
; t he f i r s t s t r ing of l eng th B
; s e t STROBE act iva t e d

; re s e t STROBE act iva t e d

, c.
- '-'

j ne e t l
mov dx , [ PORT2 ]
mov ax , 2 5 4
out dx , ax
c a l l de l ay
mov dx , [ PORT l ]
mov ax , O C O h
o u t dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , l
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , O
out dx , ax
c a l l de l ay
mov s i , O
mov dx , [ PORT l ]
mov ax , s e c [ s i ]
out dx , ax
mov dx , [ PORT2 ]
mov ax , 1
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]

; s e l e c t s the i n s t ruc t i on reg i s t e r

; s e t DDRAM addre s s for d i s p l aying

; the next 8 charac t e r s

; s e t da t a regi s t e r

; wr i t e t h e next 8 chara c t e r s
; o f t h e s t r ing

1 00

The Parallel Port in IBM-PC Computers

mov ax , O
out dx , ax
c a l l de l ay
add s i , 2
cmp s i , 1 6
j ne e t 2
RET
endp

wr i t e
; ----------------- -------------- ------------- --d i sp l
p roc near
; t ext l d i s p l ay procedure
pus ha
mov
ah , 0 2 h
mov
bh , O Oh
mov
dh , 1
mov
dl , 1
int
l Oh
mov
ah , 0 9 h
lea
dx , t ext l
int
2 1h
pop a
RET
displ
endp
-

; - -

- - -

in i t

- -

- - - - - - - - - - - - - - - - - -

proc near
!!1 0 V

et :

s i , fJ

- - - - -

- -

- - -

- - -

- - - - - -

- -

- - - - - - - - - - - -

; s e l e c t ins t ruct i on reg i s t e r

; in i t i a l i z a t ion i s t o t ransm i t t o t h e LCD

; some informat i on s : no . o f b i t s
; o f the dat a bus ( 3 8 h ) ,
; LCD on s e t w i t h i n t e rmi t t ent cursor
; d i s p l ay ( O f h ) and c l ears creen ( O l h )

si , 2
add
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , 1
out dx , ax
c a l l de l ay
cmp s i , 6
j ne e t
RET
endp

; d i s p l ay in i t i a l i z a t i on procedure

mov dx , [ PORT2 ]
mov ax , 2 5 4
out dx , ax
'
c a l l de l a y
mov dx , [ PORT l )
mov ax , va l [ s i )
out dx , ax

ini t
,
- - - De l ay Proc Near
mov dx , O
mov bx , 1
mov a l , 1
xor ah , ah
int
l aH
add bx , dx

- -

- - -

- -

- -

- - - - - -

- - -

- -

- - -

- -

; de l ay procedure to l ed the LCD

; proce s s the rece ived i n f orma t ions

1 01

The Parallel Port in IBM-PC Computers

D l yLp :
xor
ah , ah
lAH
int
crnp dx , bx
j ne D l yLp
RET
D e l ay Endp

'

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

code

ENDS
END

MAI N

9. 7 Exercise
a . Analyze and execute the appl ication lcd 1 6.asm. To u nderstand the
progra m , the appendix about the 1 6-character LCD is recommended .
b . Modify the appl ication to display characters introd uced from the PC
keyboard .
c. Develop a n application that rotates a text, introduced from the PC
keyboa rd , on the LCD .
d . Rewrite the applications in C language.

1 02

The Parallel Port in the IEEE 1 284194 Standard

1 0 . T H E PARALLEL PORT I N TH E I E E E 1 284/94

STAN DARD

1 0. 1 IEEE 1 284/94 standard

The I EEE 1 284/94 Standard, "Signaling Methods for Parallel
Bidirectional Peripheral for PC , forecasts 5 data transfer modes. The last
"

two ( E P P , ECP) are evolved modes for high speed bid irectional
communications between a PC and an external peri pheral of 50 .. 1 00 times
faster than the standard parallel port. EPP and ECP modes keep the
compatibility with the existing peripherals that are using the old
comunications modes.
EPP and ECP modes are implemented in the newest 1/0 controllers
by most of the peripheral chips producers. These chi ps generate the
protocol signals needed for the data transfer between the PC and the
periphera l . For instance, in EPP mode, a byte can be transferred to the
peripheral using a simple OUT instruction. Also it is to be noticed for this
mode the possibility to address more peripherals by a separate address
transfer cyle. In ECP mode, the hardware is more evolved . In this mode the
presence of a F I FO memory makes O MA transfer efficient, also it allows to
send commands to all the peripherals using a special transfer cycle. The
1 284/94 standard , beside the 5 operating modes, uses a negotiation
method for the data transfer between the peripheral and the PC, defining
the physical interface (cables, connectors) and the electrical interface
(drivers , terminals, i mpedances).
The parallel port based upon the 1 284 standard represents a high
performance i nterface, easy to use for a great variety of peri pherals, from
pri nters to mobile peripherals, scanners, HDDs, etc.

1 0 .2 Enhanced Paral lel Port ( EPP)

The first specification for EPP mode appeared in the EPP 1 .7 version ,
i ncluded later i n I EE E 1 284 standard . The EPP port has two
implementations: EPE> tZ and EPP 1 .9, with differences that can affect the
port operation. EPP has a typical transfer rate between SOOKBps and
2MBps, ach ieved thanks to hardware implementation of the co mm u n fcation
proto col . The handshake signals are generated by hardware instead of
software, as i n the S P P .
1 03

The Parallel Port in the IEEE 1 284194 Standard

EPP mode is more often used than ECP. The difference between
EPP and ECP is that E P P gene.r_ptJ_nc:j_ C()l"ltroles all transfrn.to and_from
the peripheral, while EC P negoci a tes with the periphera l a reverse_channel
and the handshake c;ontrQI, things harder to achieve with an usual logic, so
a de d i cate cf contro ller or an ECP peripheral chip is necessary.
EPP protocol defi nes A_types of transfer cycles:
1 -2 : Data Read I Write cycles
3-4 : Add resses Read I Write cycles
In EPP mode, the pins and the signals have different names than in the
standard mode (see tab. 1 0 . 1 )
Pin

SPP Signal EPP Signal

In/Out

- S t robe

- Wr i t e

Out

2-9

DO -D7

AD 0 - AD 7

10

-Ack

- In t r

In/
Out
In

11

Busy

- Wa i t

In

Function
" Low11 i nd i c a t e s wr i t ing and
" hi gh"
indi c a t e s reading
Addre s s / Da t a b i d i rec t i onal
bus
The p e r iphe r a l gene r a t e s
inte rrup t i on when s e t s the
l ine to " 0 "
" Low" ind i c a t e s the
pos s i b i l i ty of s t a rt ing a
cyc l e ,

12

P ap e r End

13

Select
out
- Auto
Linefeed
- Error

14
15
16
17
1825

- !nit
- Select
in
Ground

User
Def ined
User
Def ined
-Data
S t robe
User
D e f ined
- Re s e t
- Addre s s
S t robe
Ground

In
In
Out
In
Out
Out

'' h i g h "

Lht: elid uf

cyc l e
C a n b e de f ined by every
p e r iphe ral
Can be de f ined by every
p e r iphe r a l
" l ow" i nd i c a t e s that a dat a
t rans f e r i s in progre s s
Can be de f ined by every
p e r iphe r a l
" l ow" r e s e t s t h e p e r iphe ral
" l ow11 ind i c a t e s a n adre s s
t rans f e r in p rogre s s

GND

Table 10 . 1 Pins signi ficance i n EPP mode

Paper End , Selectout and Error are not defined in EPP mode, these
lines b eing used in different ways, depending on the peri phera l . These
lines' status can be determined from the standard parallel port registers.

1 04

The Parallel Port in the IEEE 1 284194 Standard

E P P port registers
EPP port is, compared to SPP, a new set of ports (registers), th ree of
them being inherited from SPP mode. The next table presents these
registers .

Address

Port Name D/WR

Data Port
Wr i t e
( SPP/EPP )
S t atus Port
Bas eAddr+ l
Read
( SPP/EPP )
Con t r o l Port
Write
B a s eAddr + 2
( SPP/EPP )

Bas eAddr+ O

B a s eAddr+ 3
B a s eAddr + 4
Bas eAddr + 5
Bas eAddr + 6
E e. s e_ddr -!- ?

Addr e s s Port Read/

Wr i t e
( EP P )
Data Port
( E PP )
Unde f ined
( EPP)
Unde f i ned
( E PP )
Unde f i ned
( E PP )

Read/
Write
-

Description
S t andard dat a port
S t andard s t atus port
S t andard command p o r t
The port wr i t ing/ reading genera t e s
an
EPP
cyc l e
to
wr i t e / read
an
a ctd:t:e5s
The port wr i t i ng / reading gene r a t e s
a n EPP cyc l e t o wr i t e / read a dat a
I n s ome EPP imp l ement a t i on s i s u s e d
for 1 6 / 3 2 - b i t t rans f e r s
In s ome EPP imp l emen t a t i ons i s used
for 3 2 - b i t t rans f e r s
In s ome EPP imp l ement a t i on s i s used
for 3 2 - b i t t rans f e r s

Table 1 0 . 2 EPP mode regi sters

It is to be noticed that the first registers are the same as for the
standard mode, keeping the compati bility with the SPP mode.
If data communication to EPP compatible devices is needed , all that is to
be done is to send the data to be transmitted into the E P P data register, at
base address+4, and the EPP port hardware wil l generate all the needed
handshake signals. The same operations are to be done when address
transmission is needed , using the EPP port; the d ifference being in the use
of the E P P address register at base address+3. Both data and address
registers, in E P P mode, are read/write, so to read/write data from/ to the
device , the same registers can be used . The registers from base address +
5 . 7_ can be used for 1 6/32-bit
- data transfers, if the port accepts this. The
parallel port can tran Sfe r on ly- i:r bits at a time, so that any 1 6/32-bit word
sent to the parallel port is i ntercepted by the ISA controller that will
generate 2 or 4 8-bit rapid cycles without the user i ntervention .
.

The hardware protocol (handshake)

The d ata_Jrnn_$fers i_n _J;_pp mode follow the handshake procedure
from the next figures. EPP mode is d ifferent from S P P because this
1 05

The Parallel Port in the IEEE 1 284194 Standard

procedu re is done only by hard components . To i nitialize an EPP cycle, the

program needs to do only an 1/0 operation to a data or address EPP
register.
Data read cy cle.
A data read cycle takes place in a si11_gl__l / Q cycle and it is done fol lowing
the next steps:
1 . The program reads the EPP data register (from base address+4)
2. -DataStrobe is activated by the EPP port if - Wait is "low" and indicates
a data transfer
3 . The PC waits u ntil the peripheral confirms that the data byte is on the
lines ADO-AD? setting -Wait on "high"
4. EPP port copies the data into the data register
5. EPP port deactivates -DataStrobe
6 . E P P data read ing cycle i s ended
DC!t.a write cycle
T he program writes into the EPP data register (at baseaddress+4)
-Write is set on "low" , ind icating a write operation
The data is sent to the bus, ADO-AD?
-DataStrobe is activated because -Wait is "low" (active)
5. The PC waits u ntil - Wait becomes "high", ind icating acknowledge from
the peripheral
6. -DataStrobe and - Write are deactivated , the cycle is ended
7 . -Wait i s activated for an eventual new cycle

1.
2.
3.
4.

/Write

/Data
S t robe
/Wait
Data

\
I
x

/Write
/Data

S t robe

\_

/Wait

x==

Da ta

Fig . 10 . 1 EPP data read cycle

\__

Fig . 10 . 2 EPP data write cycle

If the handshake is implemented according to 1 .7 EPP standard (that

appeared before I E E E 1 284), -DataStrobe and -AddressStrobe can be
activated to start a cycle, no matter what the status of -Wait is. In EPP 1 .9,
an EPP cycle starts only after -Wait becomes "low" . Both EPP 1 .7 and EPP
1 .9 need Wait to be "high" to end a cycle. Its deactivation can be done
1 06

The Parallel Port in the IEEE 1 284194 Standard

through the progra m by read ing the status register or by writing it

(depending on the port type ) .

1 0.3 Extended Capabil ities Port (ECP)

ECP protocol uses _ ba_rg9mpQo.ents_ to generate the d ialog signals
(handshake) between devices , the same as i n EPP mod e , working
approximately at the same speed . Using this mode, highr p_erformance
can be obtained , using PMA transfer from/to the transmission/reception
_ElE.0-buffer that this port has. Another function of ECP is to compress in
real-ti me the data . Using RLE (Run Length Encoding), a compression rate
until 64 : 1 can be obtai ned , usually 4 : 1 . This is good for scanners and
performant pri nters , where most of the information (for example at an
i mage processing) represents long repeating data stri ngs. ECP supports
channel addressing modes, facility needed in the case of complex
peripherals consisti ng of more d ifferent devices, each one havi ng its own
add ress. For example, a m ultifunctional scan ner, fax/ modem and printer
device can be con nected to a PC through the parallel port, each fu nction of
the peri pheral being considered as a logical device that can be separately
accessed .
The ECP port is compatible with SPP and EPP. The operating mode of the
port can be selected i n a command register. When the port is used i n ECP
mode, the pins have the next fu nctions:

Pin

SPP

ECP

{Ju")/,..

- S t robe

2-9

D O - D7

IN/OUT

: ""

Ho s t C l k

Da t a ( 8 : 1 ]

Out

I n / Out

10

- Ack

P e r iphCl k

In

11

Busy

P e r i phAck

In

- AckRev e r s e

In

1 2 Paper End
13

Select

XF l ag

In

14

- Aut oFeed

Hos tAck

Out

15

- E rror

- Pe r iph
Reque s t

In

16

- In i t

- Reve r s e
Reque s t

Out

Function
I f i t i s '' l ow" ,
there are va l i c
data
on
port .
When
it
is
deact ivat e d ,
a s c ending
the
edge
wi l l be u s e d t o t ran s f e r da t a t c
t h e p e r iphe ral
B i d i re c t i onal dat a bus
Used t ogether w i t h Hos tAck for the
reve r s e data t r an s f e r
Used together w i t h Hos t C l k for the
direct dat a I addre s s t rans f e r
When i t i s " l ow" , the p e r iphe r a l
acknowl edge s - Rever s eReque s t .
Ext ens ib i l i ty f l ag
Gives s t atus i n f o rma t i on f o r d i re c t
dat a / commands
When i t i s " l ow" i nd i c a t e s that a
reve r s e da t a t rans f e r i s p o s s ib l e
When i t i s " l ow" indi c a t e s that the
data tran s f e r i s made in reve r s e
way

1 07

The Parallel Port in the IEEE 1 284194 Standard

17
18-

25

- S e l e c t in
Ground

1284

Ac t ive
Ground

Out

On " h igh" ind i c a t e s that the

i n one
of
the
i s work ing
t ran s f e r mode s

GND

Ground s ignal

port
1284

Table 1 0 . 3 Pins assignment for the ECP port connector

HostA<;k and PeriPohAck l ines indicate if the signals from t_b _gr:ita l ine.s
r,present data or command signals. If these l i nes are "high" then data is
sent to the data l ines, if these l ines are "low" then a command cycle takes
place. If the PC sends commands, then HostAck is "low" , and if the
peri pheral sends the commands then PeriphAck will be "low" .
I n a command cycle , the sent byte can be a RLE cou nter or a channel
address . This i s determi ned by the I'."_th_ blt (_MSl from the data lines. If this
bit is "O" , the other bits (0 6) are a value used i n the compressing
algorith m . If thi s bit i s " 1 " the data from li nes 0 6 represent the channel
address that can be from 0 to 1 27.
..

..

ECP registers
In the table below the ECP port registers are presented . The fi rst
three of them a re the same as for the standard para l lel p o rt A speci a l
attention must be accorded to the bid i rectional port activation bit (bit 5 from
the control port) . This bit shows the d i rection of data through the ECP port
and affects the bit that shows if the F I FO stack is fu l l or empty, bit from the
ECR register.
.

OFFSET
0

Port Name
D a t a Port

S t a t u s Port

Con t r o l Port

400

401
402

Read/Wr i t e

( ECP mode 0 0 0 0 0 1 )

F I FO Addre s s - ECP

F I FO
F I FO ;

Read/Write

( ECP mode 0 1 1 )

Read/Wr i t e

(Al l Mode s )

Read/Wr i t e

( Al l Mode s )

Data
( Para l l e l
ECP mode 0 1 0 )

Read/Wr i t e
Port

data

ECP Data F I FO ( ECP mode 0 1 1 )

F I FO t e s t

Read/Wr i t e

( ECP t e s t mode 1 1 0 )

C f gA ( Conf i gura t i on Reg i s t e r A

Con f igura t i on mode 1 1 1 )
C f gB ( Conf igura t i on Reg i s t e r B
Con f i gurat i on mode 1 1 1 )
ECR ( Ext ended Con t r o l Reg i s t e r
Al l Mode s )

Read/Wr i t e

Read/Wr i t e
-

Read
Read/Wr i t e
Read/Wr i t e

Table 10 . 4 ECP regi sters description

1 08

The Parallel Port in the IEEE 1 284194 Standard

Extended cq11JrnLre_gisterECR: this register establ ishes the operating

mode oTfhe-ECP- port and shows the status of the F I FO stack.

Bit

Function

7:5

S e l e c t s the opera t i ng mode

000

S t andard Mode

001

Byte Mode

010

Fa s t Centron i c s Mode

Oll

ECP Mode

100

E P P Mode

101

Re s e rved

llO

Te s t Mode

lll

Conf igura t i on Mode

ECP Interrupt B i t

DMA Enab l e B i t

ECP S e rv i c e B i t

F I FO Fu l l

F I FO Empty

-1 0
oo

Table 10 . S . Extended control regi s ter -(...+--

Operating Modes
Standard Mode
SPP
Byte Mode/
PS/2 Mode

In t h i s mode , the para l l e l port operat e s a s a

s t anda rd para l l e l port , wi thout the b i d i re c t i onal
t ransmi s s i on pos s ib i l i ty
I n t h i s mode , the para l l e l port ope r a t e s a s a
b i d i rect i onal s t andard para l l e l port
In t h i s mode , any dat a !il:it.t..en i n t o t he F I FO
s t ack wi l l b e --!!:- _t9 tbe pe riphe r a l us i ng the
S P P commun i c a t i on procedure ( hands hake ) . The hard
component wi l l generate the de s i re d commun i c at ion
procedure . Thi s mode i s u s e f u l when work i ng w i t h
can
We
have
ECP
spec i f i c
devi c e s .
non - ECP
a
bu f f e r ,
F I FO
l ike
hard
p o s s ib i l i t i e s ,
but the commun i c a t i on procedure s
acce l e ra t i on ,
( handshake ) w i t h the per iphera l a r e S P P spec i f i c
one s , not ECP .
St andard opera t i ng mode for E C P . Th i s mode u s e s
with
the
procedure
d i a l og
ECP
spe c i f i c
per iphe ra l s
I n: s ome c a s e s act iva t e s EPP mode , i n other c a s e s
t h i s mode i s r e s e rved .
Re s e rved
_

__ _

Parallel Port
FIFO Mode ( Fast
Centronics Mode )

ECP FIFO Mode

EPP
Mode/Reserved
Reserved

1 09

The Parallel Port in the IEEE 1 284194 Standard

FIFO Test Mode

In t h i s mode , any da t a wr i t t en into the F I FO t e s t

reg i s t e r wi l l be wr i t t en i n t o F I FO and any dat a
read f rom the F I FO t e s t regi s t e r wi l l be read
f rom the F I FO buf f e r . The F I FO Ful l / Empty s t atus
b i t re f l e c t s the buf f e r s t atus .

Configuration
Mode

I n t h i s mode the two conf igura t i on

cnfgA and cnfgB are acce s s ib l e

reg i s t e r s

Table 10 . 6 ECP operating modes

When the port is operating i n 1ndQn:t mode , it will be as a usual
standard parallel port without bidirectional tra nsfer. If bidirectional mode is
desired , we must choose the Byte mode. The F I FO parallel port mode and
F I FO ECP use hard components to generate the handshake signals. The
d ifference between the two modes is that the fi rst one uses SPP specific
handshake signals, so that it can be used together with the SPP printer,
while the second one uses ECP specific handshake signals.
The F I FO test mode can be used to test the capacity of the F I FO buffers
and to verify if they a re fu nctioning properly. I n the F I FO , test mode, any
byte written i nto the TEST F I FO register (base address + 400 h) is placed
i nto the F I FO buffer and any byte read from th is register is ta ken from the
F I FO buffer. Using this register, together with the F I FO Full and F I FO
Empty bits from the extended control register, we can determine the
capacity of the F I FO buffer. l_h_is sl]_oul9 be of 1 6 bytes.
The other b its from the ECR register have an i mportant role i n the ECP
operation . The i nterru pt bit (bit 4) activates the i nterru pts ; bit 3 activates the
d i rect memory access (QMA). Bit 2 shows if the req uested interru pt was
i n itiated ; if so, the bit w ill be set to 1 . To reset th is bit the procedure is
different, depending on the controller type; some controllers need to write
"O" at that address wh ile others reset this bit automatically after it was read .
The F I FO F u l l ( 1 ) and F I FO Empty (0) bits show the F I FO buffer status.
Thes e bits a re dependent on_l:>i!__ from the control reg ister. If bit O ( F I FO
Empty) is active , the buffer is completely empty; if bit 1 ( F I FO Full) is active,
the buffer is completely fu l l . If none of the bits is active , it means that the
buffer conta i n s some data , but it is not fu l l . These b its can be used in F I FO
test mode to d etermine the capacity of the buffer.
..

The configu ration register A - CnfgA

The configuration register A is one of the two configuration reg isters of the
ECP port. These reg isters can be accessed only when the ECP port is i n
the configuration mode (see extended control register). CnfgA reg ister can
1 10

The Parallel Port in the IEEE 1 284194 Standard

be addressed at base address + 400 and the b its have the sign ificance
presented i n table 1 0.7.
The configuration register A gives extnqg. i nformation about the
ECP port. The most signifi cant bit shows if the interru pts are generated on
leyel pr on edge. It depends on the l?C_ Lnternal bus type. B its 4 and 6 show
the width of the bus used by the ECP controller. Some controllers have only
8-bi t bus, other 1 6 or 32-bit bus. To be able to use at maxim u m the bus
width , the progra m can read the status of these bits to determine the
maxi mum size of the word for communicating with the controller.
The Ta st th ree bits (less sign ificant bits) are used for transrri[s!<:>.r1_L()\lry.
To recover data i n case of error, the program must know exactly how many
bytes were transmitted , determining if there are bytes left i n F I FO . Some
implementations can include bytes into the transmitter registers , that wait to
be transmitted as a part of F I FO (Full Status), other implementations do not
allow th is. bit 2 determines if the i mplementation allows it or not.

Bit
7

6:4

Function
1
0

I n t e rrup t s act ive o n l eve l

I n t e rrup t s act ive o n edge

O Oh

Ac c ep t s max imum 1 6 - b i t words

O lh

Ac cep t s max imum 8 - b i t words

02h

Ac c ep t s maximum 3 2 - b i t words

03h : 07h

Re s e rved

Re s e rved

The b i t s f rom the bus are inc luded or not i n F I FO

For d i r e c t commun i c a t i on , a byt e f rom the
0
t ransmi t t e r bus doe s not a f f e c t F I FO Fu l l
For d i r e c t commun i cat i on , a byt e f rom the
1
t ransmi t t e r bus is i n c l uded i n F I FO Fu l l
Unt ransmi t t e d byt e s in F I FO
00

1:0

01
10
11

Who l e word
One byt e f rom the word transmi t t ed on the port l e f t
in F I FO
Two byt e s f rom the word t ransm i t t e d o n the port l e f t
i n F I FO
Three byt e s f rom the word t ransmi t t ed on the port
l e f t i n F I FO

Table 1 0 . 7 Configuration regis ter A

Another problem is that the parallel port has 8-bit outputs , and the
user might want to transmit on 1 6 or 32 bits . In this case , only a part of the
111

The Parallel Port in the IEEE 1 284194 Standard

word is transmitted , equal to the maximum size that can be transmitted on

that port, the rest of it biog toied in FIFO. Bits 0 and 1 ind icate if the
bytes left in F I FO a re valid and can be transmitted .

Configuration register B - CnfgB

T h e configuration reg ister B , l i ke CnfgA, is ava i lable o n l y when t h e ECP
port is i n con_fig_u1UQ.r1 ffi.Qde . When this mode is selected , cnfg B is at base
add res.:!" 40l h . I n the table below the structure of cnfg B is presented .
The configuration register B can be a B.e.adLWrite access combinatio n .
Some ports c a n b e configured through software; O M A and I RQ resou rces
can be selected from the register. Others can be configured in B I OS or
using jumpers from the card . Bit 7 from cnfg B selects if the transmitted data
wi l l be CQJDJ?_rg witt1 C RE or noJ. When it is active , the transmitter will
compress d ata before transmission ; otherwise, data wi l l be transmitted
u ncompressed .

Bit
7
6
5:3

2:0

Function
1

Comp re s s output dat a w i t h RLE a l gor i t hm

Doe s not compre s s output data

I n t e rrup t s s t atus

ind i c a t e s I RQ p i n s t atus

S e l e c t s o r i nd i c a t e s IRQ l ine s t atus

000

Jumper s e l e c t e d inte rrupt

001

IRQ 7

010

I RQ 9

Oll

IRQ 1 0

100

I RQ l l

101

I RQ 1 4

llO

I RQ 1 5

lll

I RQ 5

S e l e c t s or i nd i c a t e s t h e s t atus o f t h e u s e d D MA c hanne l
000
Jumper s e l e c t ed 8 - b i t DMA channe l
001

Channel 1 DMA

010

Channe l 2 DMA

Oll

Channe l 3 DMA

100

Jumper s e l ec t e d 1 6 - b i t D MA channe l

101

Channe l 5 DMA

llO

Chann e l 6 DMA

lll

Chann e l 7 DMA

Table 1 0 . 8 Configuration regi s ter B

1 12

The Parallel Port in the IEEE 1 284194 Standard

BiL6 returns the status of the interrupt line. It can be used to diag nose
confl icts, because it does not reflect the interru pts from the parallel port and
from the other devices that use I RQ .
Bits 5 a n d 3 show the status of the interrupts generated b y the port, and
bits 2 . . 0 show the status of the OMA channels. This field can be
read/written .
E C P mode comm u n i cati o n
The communication with the peripherals in ECP mode is d ifferent from the
communication in SPP mode. The most significant d ifference is that in ECP
mode data can be transmitted in both ways anytime, using add itional
control signals. Below, the ECP d ialog modes (handshake) for both
communication ways (di rect and reverse) are presented .
D i rect data tra nsfer

1 . Data is sent on the data lines of ECP port to the PC

2. ECP port indicates the beginning of a data cycle

by

val idating

HostA ck= 1

3 . E C P port v a l i d ates data setting HostC/k o n "low"

4 . The peri pheral transmits the acceptance message by va l id a ti n g
PeriphA ck= 1

5. ECP port puts HostC!k on "high"; on the rising edge data is written to
the peripheral
6 . T h e peri pheral signals the data receiving b y deactivating PeriphA ck=O
/ Host

Clk

/ P eriph

Ac k

Ac k

Data

Fig . 1 0 . 3 Direc t data trans fer

Reverse d ata transfer

1 . ECP sets -Re verseRequest on "low" to request a reverse channel

2 . The peri phera l confirms the channel by setting -A ckRe verse on "low"
3. Data is sent by the peri pheral on the data lines
1 13

The Parallel Port in the IEEE 1 284194 Standard

A data cycle is activated by the peri pheral by setti ng PeriphAck on

"high"
5 . Data is validated b y the peripheral b y setting PeriphC/k on "low"
6 . ECP port responds by setting HostAck on "high"
7 . The peri pheral sets PeriphC/k on "high"; on the rising edge data is
written i n the ECP port
8 . E C P port confi rms the receiving b y setti ng HostAck o n "low"
4.

/ Rever s e "'\
Reques t
\. _____..J.

/Ac k
Rev erse

/ P e riph
Clk
/ Ho s t
Ack

/ Pe riph
Ack
Dat a

Fig . 10 . 4 Reverse data trans fer

RLE com p ress i o n ( R u n Length Encod i n g )

The RLE protocol incl udes a simple compression algorithm , Run Length
Algorithm. The compression is obtained by counting the identical bytes and
send ing them to destination as follows: fi rst, a byte that represents the RLE
counter is sent, then a byte that represents the repeati ng value is sent. This
algorithm al lows a maxi mum compression rate of 64 : 1 . For example if a
nu mber of 40 "C" characters wi ll be sent, a byte containing the va lue "40"
and a byte conta i n i n g the character "C" wil l allow the peripheral to recover
the i nformation . If i n the data string, we have two bytes of d ifferent values
(characters), a byte containing the value "O" will be the transmitted cou nter,
followed by the va lue of the first byte, then the two bytes for the second
character will be also transmitted .
The i nformation bytes compressed with RLE must be d istingu ished from
the other bytes sent on the data l i nes. I n order to achieve this, a command
to the F I FO port of ECP is sent. The bytes sent to this reg ister can be
address bytes or bytes compressed with RLE . The d ifference is made due
to bit 7 ( M S B ) . If it is 1, the other 7 bits ( 0 . . . 6 ) represent a channel address ;
if it is 0 , the other 7 bits represent the RLE counter. Using MSB for this
purpose, the n u mber of channels is l i mited to 1 2 7 .
1 14

The Parallel Port in the IEEE 1 284194 Standard

1 0.4 Appl ication

Analyze and execute the fol lowing progra m ; it detects the type of the
installed parallel port and its address .
# in c l ude < s t d i o . h >
# inc lude < do s . h >
# i nc lude < c on i o . h>

//******************************************************************
//******************************************************************

Main program

int ma in ( vo i d )

uns igned int f a r * p t raddr ;

uns igned int port , addre s s ;
int a ;
uns igned char r e s u l t , re z , va l = O x c c ;
/ / p o i n t e r to the sys t em memory s t art ing w i t h 4 0 8 h whe r e the
sys t em wr i t e s the de t e c t e d para l l e l port s
p t raddr = ( uns igned int f a r * ) O x 0 4 0 8 ;
"' C. 9r ft, /
- If' 1A"""
c l rs c r ( )
c l e a r s c reen
read the i ns t a l l ed para l l e l port s addre s s e s

//

; /I

II

a o cvv;

for ( a= O ; a< 3 ; a+ + )

port = * p t raddr ;
i f ( port = = O )

II
II

i f the addre s s content i s O

the port i s not ins t a l l ed

p r i n t f ( " LPT %d i s not ava i l ab l e \ n " , a + l ) ;

II

else

i n i t i a l i z e port addre s s e s

p r i nt f ( " The addre s s f o r LPT%d i s %xh\n 11 , a + l , po rt ) ;

i f ( ( i nportb ( port + Ox4 0 2 ) & 0 x 0 3 ) ! =

( inportb ( port + 2 ) & 0 x 0 3 ) ) ;

//
//

conf igure ECP mode and wr i t e

F I FO f u l l = O , F I FO empty= O 1 1 0 1 0 0b = O x 3 4
outportb ( port + Ox4 0 2 , 0 x 7 4 ) ;
r e su l t = inportb ( port + Ox4 0 2 ) ;
mus t be di f f erent and keep the i n i t i a l
/ / c on f i gura t i on
c annot be wr i t t en , they are Read On ly

/I
/I

i f ( re s u l t = = Ox7 5 )
el se

{ p r i nt f ( " The

II

port i s ECP typ e \ n \ n " )

;}

outportb (port + 4 , va l ) ;
wr i t e EPP da t a reg i s t e r
i f t h e S P P dat a reg i s t e r content i s di f f e rent

//

1 15

The Parallel Port in the IEEE 1 284194 Standard

II
II

f rom what we wro t e in the E P P da t a reg i s t e r

t h e port i s S P P type
re z = i nportb ( por t ) ;
i f ( re z ! = val )
print f ( " The port i s S P P t yp e \ n " ) ;
print f ( " The port i s E P P typ e \ n " ) ;
else

};

*pt raddr + + ;

};

ge t ch ( ) ;

1 0.5 Exercise
Write a n appl ication that determi nes the F I FO stack
port.

1 16

size of

the

ECP

On The Memory in PC Systems

1 1 . O N TH E M E M O RY I N PC SYST E M S

1 1 . 1 T h e memory organ ization

The 8086 microprocessor considers the memory as a 1 M byte string.
Because all its i nternal registers are on 1 6 bits, it can not work i nternally
with addresses longer then 1 6 bits, so it leads to the 1 Mbyte continuous
space divided i nto 64Kbytes segments . The microprocessor can work at
any time with four such segments, their start addresses being i n the
segment registers. The segments are memory blocks that can be
overlapped , the only condition to be respected being that the start
addresses must be a multiple of 1 6 . This segmentation i nto 64KBytes
blocks has some advantages:

Modular programming is facilitated ; each module (may occupy one or

more segments) may be developed i ndependently.

The programs can be written i ndependently by the position they wi ll

have i n memory or can be dynamically relocated ; in order to do this, the
programs must not affect the segment registers content and must not
access locations outside the current segment; using instructions to
mod ify the segment registers content, the program can be placed
anywhere in memory
The memory organ ization into segments has disadvantages also:

The segments length limits the length of the programs

The physical add ress is obtained using two logical add resses (the
mechanism is presented in fig . 1 1 . 1 ) that a re not unique, it means that a
physical address can be achieved from d ifferent combinations of logical
addresses, and this can create confusions.
15

0
OFFSET

15

0
S EGMENT REG I STER

19
PHYS I CAL ADDRESS

Fig . 1 1 . l The physical address calculation mechanism

117

On The Memory in PC Systems

The two logical addresses are the content of a segment register and of an
offset from another i nternal register or a result from the addressing modes.
To obtain the p hysical address , 1 6 mu lti ply the segment reg isters content,
the empty positions are padded with "O" , and then the offset is added ,
obtaining a 20-bit address .
The memory space that can be directly addressed by the 8086 processor is
of 1 Mbyte , with addresses between OOOOOH and FFFFFH . The addressing
can be done at byte level and at word level (two successive bytes) without
restrictions for the start addresses of the word operands.
Physically, the memory can be divided i nto two blocks of maxim u m 5 1 2
Kbytes: the even block and the odd block. The even block contains only
even address locations and the odd block, only odd address locations. The
even block is con nected to the inferior half of the data bus, 07-00, and the
odd one to the superior half of the data bus, 0 1 5-08 . The address l ines
A 1 9-A 1 are used to select a memory location simultaneously from both
blocks . The transfer between the selected locations and the data bus is
done only under the control of two more l i nes, AO and /B H E , l i ke in the
table below:
/ BHE

AO

0
0
1
1

0
1
0
1

Tran s f e r
Word
Odd byt e
Even byt e
-

Table 11 . 1 The commands for byte/word trans fer

Figure 1 1 . 2 presents the memory d ivision i nto the two blocks :
Ad dre s s b u s

Even

O dd

/ BH E

cs

AO

( HI GH )

cs

( lOW)
D O - D7

D 8 - Dl 5
D O - Dl S

Fig . 11 . 2 The memory blocks

118

On The Memory in PC Systems

I n order to access an operand from an even address, the l i ne AO wil l select

the even block and the line /BHE wil l i nvalidate the odd block. I n this way,
the transfer between the addressed location and the i nferior half of the data
bus wi ll take place . If the access to an operand from a n odd address is
needed , the line AO will i nvalidate the even block whi l e the line /BH E="O"
will select the odd block and the transfer between the addressed location
and the superior half of the data bus wil l take place .
I n the case of word transfer, from an even address, both blocks will be
selected simultaneously by the lines AO=/BH E="O". The transfer between
the two addressed locations and the whole data bus wi l l take place in one
bus cycle. In the case of access to a word operand from an odd address,
two bus cycles are necessary. I n the first cycle /BH E="O" and A0=" 1 " , so
that the byte from the odd address wil l be transferred to the su perior half of
the d ata bus, th is byte bei n g the less significant one of the opera n d . For the
second cycle the address is i ncremented , so that AO="O" and /B HE=" 1 " and
the byte from the even address wi l l be transferred to the i nferior half of the
data bus, this byte being the most sign ificant one of the opera n d .
These operations are executed automatically b y t h e microprocessor,
includ ing the correct steeri ng of the bytes to the correspond i n g halves of
the i nternal reg isters and the whole process is transparent for the user, but
it is 4 states longer.
The comm u n i cation mode between the processor and the memory is
similar to the 1/0 ports commun ication mode. The d ifference i s that for a
memory addressing a l l the memory l i nes are necessary and if the
processor i s ru n n i n g i n maxi mum mode, the read ing/writi n g from/to memory
is done under the control of /MRDC, /MWTC and /AMWC l i nes.
The 8086 systems i nterfacing with the memory i n the minimum mode is
presented i n fig u re 1 1 . 3 .

8 0 8 6 MIN

A l 6 - Al 9
..
AD O - AD 1 5
....
..
AL E
..
,
/ BHE ..
,
/.QD ..
,
/WR ..
,
M I / O ..
,
DT / R ..
DEN ,..
,

Memory
sys t em

Fig . 11 . 3 The memory interfacing in the minimum mode

119

(MN/MX= " l" )

On The Memory in PC Systems

From fig . 1 1 .3 can be seen that beside the multiplexed address and data
lines ADO-AD 1 5 and the high address l ines A 1 6-A1 9 there is the su perior
block val idation signal, /BH E . It must be noticed that in this mode, the
microprocessor generates the memory control signals ALE, /RD , /WR,
M/1 0 , DT/R and D E N . If the microprocessor is con nected i n maxi mum
mode, the specialized circuit 18288- bus controller generates the memory
control signals.
The memory system consists of two blocks: the memory itself and the
address decode r that selects the memory. I n fig . 1 1 .4 , a practical modality
of con necting a memory in an 8086 system is presented .
Addre s s bu s

Fig . 11 . 4 The decoder circui t for the memory selec tion

1 1 .2 The PC memory map

Figure 1 1 . 5 presents the memory map for a PC-AT, obtained with the
program C H ECKIT (for the first Mbyte):
Base l1e1111rtJ Map -------==;i
Mapped?
Usa11e :
KE'r'
P
A
p
u
R
R

.----- <COl'tUEltTI OllA L>

<RESERUED>

IJPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPAAAAA P UWvV.AA!RR-------RRRR
0K
Su.....ru Uiew
0
0 O:nO
004011 to B4F4h
84F4h to 9Ell0h
9E80h to A000h
A099h to C000h
C088h to Cll00h
ceeeh to F8BBh
F990h to 080Elh

640K
531)(
102)(
6K
128)(
3ZJ(
16811
MK

PJ'O!lrams
Ava i lab l e
Pr011ra111S
Ul deo RAM
Uideo ROM
<noth i ll!I >
SljsteM llOl1

Use the cursor keqs to se lect an Item .

Press Eln'ER to d i sp l alJ 1111re deta i l about the h i11 h l l11hted Item .
H , P!!Up , P11Dn - Ulew Wi ndow 1 FZ - Copt1 to LO!I 1 ESC - Cance l

Fig . 11 . 5 The PC memory map

1 20

lM

On The Memory in PC Systems

Fol lowi ng the design decision made by I B M , at the first PCs the memory
was d ivided i n 4 parts:

1 1 .2 . 1 The base memory (conventional) represents the fi rst 640

Kbytes of the memory map and it is used by the DOS programs, resident
programs and d rivers . It has the addresses between 00000 and 9FFFFh .
Here , in the fi rst Kbyte the ta ble of interrupt vectors is kept.
1 1 .2.2 U pper Memory Area (U MA) is the next memory area (384
Kbytes), above the conventional memory and it has the addresses between
AOOOOh and FFFFFh. It is destined to be used for video memory,
ROM B I OS or video RO M , depending on the computer (see fig . 1 1 .5). The
next concepts refer to this memory area:

A problem with the ROM used by B I O S or video is

that it is relatively slow ( 1 20-200ns) compared to the system RAM (5070ns). In addition, the RAM can be accessed on 32 bits wh ile usually
the ROM can be accessed only on 1 6 bits . The concl usion is that the
access to the code from ROM B I OS is slower than the access to the
code from the system memory that is why most of the systems allow the
ROM contents copyi ng i nto the RAM , lead ing to higher performances of
the system . This copy is the "ROM shadowi ng" and it is control led by
certa i n parameters from B I OS that al low the assignment of some RAM
blocks for the ROM copies. When booti ng, the ROM parts that a re
enabled to be "mi rrored" are copied by the B I OS i nto the assig ned
D RAM memory that wi l l be protected against afterwards writi ng , wh ile
the ROM is i nvalidated . Usual ly, the area "mi rrored" i nto RAM is the
a rea of the system B I OS and of the video BIOS.
RO M S h adowi n g .

EMS (Expanded Memory S pecification) was

created to outru n the addressing limits imposed at 1 Mo by the first
generation of processors, being standard L I M E M S . To use the
expanded memory, a special adapter containing add itional memory and
switching circuits was used . The memory from the board was d ivided
i nto 1 6 Kbytes logical blocks called pages . The switching circu its allow
1 6 Kbytes memory blocks i n U MA area, cal led EMS page . This window
is usually located in the DOOOOh-DFFFFh address area and allows
access to fou r EMS pages. When the program (supporti ng L I M Lotus
I ntel-Microsoft standard ) needs a certai n expanded memory area, this is
shifted i nto the 64 Kbytes window by the switching circu its , so it can be
accessed . This concept, cal led "switched memory banks" is not very
Expanded

Memory.

1 21

On The Memory in PC Systems

different from the virtual

hard d isk but to another
i nefficient. Workin g with
offered by I NT 67h . The
the 1 Mo space.

memory, the switching being made not to the

memory area , more ofte n , thing that makes it
expanded memory is easier due to services
new processors allow extended memory over

ROM Sca n . Duri n g "cold-boot" , after POST (Power On Self Test) and
after the default handlers instal lation , B I OS verifies the external ROMs
found on the boards i n the slots of the PC. This testing is called ROM
Sca n .
Remark. R O M Scan was not implemented i n t h e fi rst ROM-B I OS and
the fi rst PCs do not have this facil ity.
The external ROM modu les can be usually between C800 : 0 and EOOO : O
addresses . Each 2Kbytes module from this area is verified i f i t h a s a
signature having the form below. If the B I OS fi nd the ROM signature, it
wi l l i nitiate the checksum calcu lation for the mod ule. Each byte is added
mod ulo 1 OOh and the sum should be 0. If the module is found to be
val i d , B I OS executes a FAR CALL at offset 03h and the ROM must
eventually return through a FAR RET. Usually the program from the
ROM mod ule wi l l i nitial ize the dedicated hard and will i nsert certai n
addresses into TIV.

Off set
+O
+l
+2
+3

Length

Content

Remark

1
1
1
?

55h
aah
Length
?

S i gnature of a ROM modu l e that can

be acc e s s ed f rom B I OS
Modu l e l ength , i n 5 1 2 byt e s inc rement
Code

Modu l o l O O h checksum

. ....

.... ........ ..

. ..

...... ...

1 1 .2.3 H i g her Memory Area ( H MA) is the fi rst 65.520 bytes

(64Kbytes - 1 6 bytes) from the extended memory (above 1 Mo) and
represents the physical add resses between 1 00000h and 1 0 F F E F h , due to
segmented address ing , and it corresponds to addresses F F F F : 1 0h FFFFh . It is a s pecial area because it represents the only area from the
extended memory that can be addressed by the PC in real mode. Normal ly,
the access to the extended memory is done i n protected mode or using
special drivers . There is a problem with the " 1 " from the line A20 which
does not exist at 8086 and 8088 , and it addresses again the start area O
OFFEFh . Starting with 80286 that su pport both modes, real and protected ,
the su pposition that i n real mode 80286 is perfectly compatible with 8086 ,
but havin g 24 address l i nes, is made. I n real mod e , we are placed i n the
first 64 Kbytes of the extended memory. To keep the compati bil ity of 80286

1 22

On The Memory in PC Systems

i n real mode, the original PC-AT I B M used the free l i n es of the keyboa rd
controller to command the line A20 . The keyboard controller i nvalidates the
line A20 when the processor is ru n n i ng in real mod e , to keep the
compati bil ity with the precedent PCs and validates it when passi ng to
protected mode. Microsoft developed a special d river, H I M E M . SYS , which
allows the line A20 to be manipulated u nder soft contro l , allowing access to
H MA in rea l mode. By practical reasons, H MA is normally used by the DOS
system to keep a part of its code, emptying approxi mately 45Kbytes of
RAM from the conventional memory. This can be done by specifying i n
CON F I G . SYS "DOS= H I G H " .

1 1 .2.4 Exten ded Memory (XMS) represents t h e memory above

1 M B , that is the addressabil ity l i mit for the original 8088 PCs processor.
Except the H MA area, the extended memory is not accessible to a PC
run n i n g in rea l mode. There are two ways to use the extended memory: the
system may operate in fully protected mode l i ke Windows N T and it can
access d i rectly the extended memory, or the other way, used by other
operati ng systems or applications ru nning in real mode (including DOS
programs that need access to the extended memory). Windows 3.x and
Windows 95 must coordinate thei r access using an extended memory
manager. The most popu lar manager is H I M E M . SYS , i n agreement with
the extended memory (XMS) user specifications.

1 1 .3 Applications
The presented application is con necti ng a 4Kbytes EPROM memory
and a 1 6Kbytes S RAM memory i n a PC system , i n the e mpty places of the
extension slots . The start address of the EPROM memory i s considered to
be CCOOOh and for the S RAM memory - DOOOOh (see fig . 1 1 .5)

1 1 .3 . 1 C o n necti ng E P RO M memories t o t h e system

Two ci rcuits 127 1 6 , EPROM memories of 2 Kbytes were u sed . Figure
1 1 .6 presents the circuit and its pins assignment. The m a i n p roblem i n
con nectin g a memory o r a port to the system is the decoder circuit, which
allows addressi n g in the desired or authorized address area . The memory
address decoder m ust be conceived depend ing on the memory start
address and the memory d imensions. I n this case, a 4Kbytes memory is
con nected starting from the address CCOOOh .
The n u mber of address l ines necessary to decode the memory block
wi l l be computed . For 1 Kbytes=2 1 0 we need 1 0 add ress l i nes. For
2Kbytes=2* 1 Kbytes we need 1 1 l i nes, and for 4Kbytes - 1 2 l i nes.
1 23

On The Memory in PC Systems

00
01
02
03
04
05
06
07

AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10

.c..E

OE
VPP
27 1 6

rig . l l . 6

E P ROM

memory pins assignment ( 2 Kbytes )

AO-A 1 0 = address lines

00-07 = data lines
/CE = memory selection signal, active on "O " ("chip enable")
/OE = memory read validation signal, active on "O " ("output enable")
Vpp = voltage that allows data writing to memory if 25V is applied

.-----.
7408

Fig . ll . 7 The address decoder for the

E P ROM

memories

In ta ble 1 1 .2 the address li nes used by the decoder and for

addressing the memory are presented .

Al9

Al8

Al7

Al6

Al4

AlS

Al3

Al2

All

AlO

A9

AS

A7

A6

AS

A4

A3

A2

Al

AO

AO

Table 11 . 2

EPROM

decoder address l ines

1 24

On The Memory in PC Systems

The address l i nes A 1 9-A 1 2 are used i n both memory banks, and l ines
A1 1 -A1 will be used for addressing. AO is used in selecti ng the low (even)
ban k if AO="O" or the high (odd) one if A0=" 1 " and /BH E="O" . Figure 1 1 . 7
presents the d ecoder made accord i ng to the table 1 1 . 2 .

1 1 .3.2 C o n necti ng SRAM memories to the system

Two 6264 circuits were used , 8Kbytes SRAM memories. Figure 1 1 . 1 O
presents the circuit. J ust l i ke for the EPROM circuit, to read/write from/to
the memory, we need an address decoder. The sta rt address is DOOOOh
and the address l i nes to generate CS2 and the lines for addressing are
determined i n the same way as before .
AO
A1
A2
A3
A4
A5
A6
A7
AS
A9
A10
A1 1
A1 2

DO
01
02
03
04
05
06
07

CS1

OE

6 2 64

Fig . 11 . 8

SRAM

memory pins assignment ( 8 Kbytes )

AO-A 1 2 = address li nes

DO -07 = data l i nes
/CS 1 = memory selection signal, active on "O" ("Chip select" )
CS2 = memory selection signal, active on " 1 " ("Chip select")
/WE = memory write command signal, active on "O"("Write enable")
/OE = memory read validation signal, active on " 1 " ("output enable")

The ta ble 1 1 . 3 is used for designing the address d ecoder.

Al9

Al8

Al7

Al 6

Al4

AlS

Al3

Al2

All

AlO

A9

AS

A7

A6

AS

A4

A3

A2

Al

AO

AO

Table 11 . 3

SRAM

decoder address l ines

1 25

On The Memory in PC Systems

The l ines A1 9-A1 4 will be used to generate the signal CS2 and A1 3-A1 wil l
be used t o address the memory. AO is used t o select the low (eve n )
memory ba n k , because it is con nected t o /CS 1 from a memory circuit and
/BH E is con nected to /CS 1 from the other memory, to select the high (od d )
memory ba n k .
I

A
B
c

YO
Y1
Y2
Y3
Y4
fil._Y5
Y6
G2 BY7

2
3

6
4
5

2
74 LS04

74 LS 1 38

Fig . 11 . 9

The

addr e s s

decoder

for

the

SRAM memo r i e s

1 1 .4 Exercise
a.

Using C H ECKIT, analyze the memory map on the workstation .

b.

Using S D E B U G , identify the video R O M signature a n d write a

progra m seq uence to verify the checksum.

c.

Analyze the con nection of the memories to the I SA bus, presented i n

the appendix. What i s the role of M E MCS 1 6? Suggest a schematic
that uses only one decoder circuit for E PROM and RAM .

d.

Using C H ECKIT detect the memories con nected to the system o n the
I SA bus and analyze the EPROMs contents.

e.

Write an appl ication for detecti ng the ROM blocks from the memory
map.

f.

Write a prog ra m i n assembling language that makes a self-copy i n

U MA ( S RA M ) and lau nches itself.

1 26

On The Memory in PC Systems

8
7
6
s
4
3
2
1
23
22
19

AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10

8
7
6
s
4
3
2
1
23
22
19

00
01
02
03
04
OS
06
07

18
20
21

.Q.E.

OE
VPP

MR

AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10

00
01
02
03
04
OS
06
07

9
10
11
13
14
1S
16
17

.Q.E.

OE
VPP
27 1 6

2716

12
13

Fi g . 1 1 . 1 0

E le c t r i c a l

s chema t i c f o r the E PROM memo r i e s b l o c k

1 27

On The Memory in PC Systems

10
9
B
7
6
5
4
3
25
24
21
23
2

10
9
B
7
6
5
4
3
25
24
21
23
2

DO
D1
D2
D3
D4
D5
D6
D7

AO
A1
A2
A3
A4
A5
A6
A7
AB
A9
A10
A1 1
A12
CS 1

DO
D1
D2
D3
D4
D5
D6
D7

CS1

CS2
'M.

.GS2
'M.

OE

OE

6264

Fig . 1 1 . 1 1

AO
A1
A2
A3
A4
A5
A6
A7
AB
A9
A10
A1 1
A12

E l ectrical

6264

s chema t i c

128

for

the

SRAM memo r i e s b l o c k

The Cache Memory

1 2 . TH E CAC H E M E M O RY
1 2.1

An

overview of cache memory

I n t h e e x i st i n g syste m s , t h e t i m e t h a t i s nece s s a ry to a ccess t h e

syste m m e m o ry i s l o n g e r t h a n t h e i n struct i o n s execution t i m e . F o r exa m p l e ,
t h e t i m e to a ccess D RAM m e m o ry i s 50-6 0 n s wh i l e a 1 O O M H z proce s s o r
executes m ost o f the i n struct i o n s i n a 1 O n s cycl e . F o r t h i s rea s o n a
co n g es t i o n m a y a p p e a r i n t h e d ata proces s i n g d u e to t h e p rocess of
b ri n g i n g t h e i n struct i o n s to t h e processor. The cache is a l ow capa city but
h i g h-speed Stat i c RAM ( S RA M ) m e m o ry that conta i n s t h e p ro g ra m parts
t h at we re re ce n t l y accessed fro m t h e m a i n m e m o ry . T h e c a c h e m e m o ry i s
u s e d to red u ce the t i m e n e ce s s a ry to b ri n g the i n fo rm a t i o n to t h e
proce s s o r . T h e t y p i c a l access t i m e fo r S RAM i s - 1 S n s , s o the c a c h e
m e m o ry a l l ows s m a l l p a rts o f t h e m a i n m e m o ry to be accessed 3 to 4 t i m e s
faste r t h e n i n D RAM , so t h at t h e p roce s s o r can process m o re d ata , waiti n g
less time.
T h e i d e a be h i n d t h e i n c re a s i n g o f t h e system perfo r m a n ce u s i n g t h e
c a c h e m e m o ry i s t h at t h e proce s s o r wi l l a lways access t h e m e m o ry i n a
s m a l l- l oc a l ized a re a . T h i s a rea is l o a d e d i nto t h e cache m e m o ry , a l lowi n g
t h e proce s s o r to access t h e m e m o ry fa ster. F o r exa m p l e , i n com m o n
a p p l i ca t i o n s , a 1 6 Kbytes i nte rn a l cache m e m o ry o f a P e nt i u m proce s s o r
conta i n s ove r 90% o f the a d d resses a ccessed by t h e process o r . I t m e a n s
t h a t o v e r 9 0 % o f t h e m e m o ry acce s s e s occur i n t h e cache m e m o ry a n d
o n l y 1 0 % o u ts i d e i t . Why t h e D RA M m e m o ry i s n ot re p l a ced w i t h S RA M ?
T h e m a i n re a s o n s a re costs a n d co n s u m pt i o n s . S RAM i s m o re expe n s i ve
t h a n D RAM a n d m o re powe r co n s u m pt i ve , a l s o be i n g l e s s d e n s e t h a n
D RA M m e m o ry . F i g . 1 2 . 1 s h ows a s i m p l ified m od e l o f a syste m with cache
m e m o ry .
C PU

S y s tem I n te r face
Fig . 1 2 . 1

Ba s i c mode l

129

of

the

cache

The Cache Memory

I n this system , each time the processor reads or writes the cache i ntercepts
the transfer to the bus, al lowing the reduction of the system response time .
Notions about cache

Before d iscussing the basic model and the architecture of the cache
memory, some common terms wil l be defi ned .
C ache h it designates a transaction whereby the cache memory contains
the i nformation req uested by the processor.
Cache m iss designates a transaction whereby the cache memory does not
conta i n the i nformation requested by the processor.
Cache consistency. Because the cache is a copy of a small memory area ,
it is i mportant that it reflects always the content of the main memory. To
maintai n the cache consistency, the terms below are used to descri be
certai n operations. The su pervision of the address l i nes done by the cache
for a transfer represents a snooping operatio n . It allows the cache to see if
itself contains the d ata that are the object of the transfer. When the cache
takes over the i nformation from the data lines, the actual ization operation is
cal led "snarf" . The "snoop" -"s narf" processes allow the cache to keep
its consistency.
To descri be the data i nconsistency, the next terms are used : d i rty data
which means that data are mod ified i n the cache but not i n the main
memory and stale data when the data are mod ified i n the main memory
but not i n the cache.

1 2.2 Architectu res of cache memory

The cache has two characteristics: a read architectu re and a write
pol icy (techn i q u e ) . The read arch itectu re may be "look aside" or "look
th rough" and the write policy may be "write back" or "write th roug h". Both
read architectures may use any write method , depend ing on the desi g n .
" Look aside" a rc h itect u re

Figure 1 2 .2 p resents a block diagram of the "look- aside" arch itecture .

T h e main characteristic o f t h i s architectu re type is that t h e cache and the
main memory are accessed at the same ti me. It is to be noticed that the
main memory (DRAM) and the cache memory see a bus cycle at the same
time.
When the p rocessor starts a reading cycle , the cache memory verifies
if the address from the bus is "cache hit", in wh ich case the cache memory
wil l respond to the reading cycle and wil l end the bus cycle. If it is a "cache
miss", the m a i n memory will respond to the processor and will end th e bus
1 30

The Cache Memory

cycle. The cache memory will do a "snarf' operation , so that the next time
the processor will find the data i n the cache. The "look aside" cache is
easier, which makes it cheaper. This architectu re provides a better
response time i n case of "cache miss" because the D RAM memory and the
cache memory see the bus cycle at the same ti me.
,- - - - - - - - - - - - - - - - - - - - -

CPU

I
I
I
I

SRAM
(Cache )

I
I

Cache
Controller

Tag RAM
- - - - - - - - - - - - - - - - - - - - - _I

System Interface
Fig . 12 . 2 "Look aside" cache archi tecture
" Look t h ro u g h " read arch itectu re

Figure 1 2 . 3 presents a block diagram of the "look th rough" read

architectu re for the cache memory.

C PU-

SRAM
( Cache )

Cache
Controller

Tag

RAM

System Interface
Fig . 12 . 3 "Look through" cache architecture
The main characteristic of this architectu re is that the cache memory
is placed between the processor and the main memory. I n this case, the
cache memory sees the processor bus cycle before allowi ng the passing to
the system bus. When the processor starts a memory access, the cache
1 31

The Cache Memory

verifies if it contains the requested data . If it is a "cache h it" , the cache

respond s to the p rocessor req uest without accessing the main memory. If it
has not found the data , we have a "cache miss" and the cache tra nsfers the
bus cycle to the system bus so that the main memory answers to the
processor req uest. The cache memory loads the d ata ("snarf') so that next
time the processor will access the data from the cache .
T h i s architecture allows the processor to access the cache memory when
a nother master device is controlling the bus and accesses the main
memory, because the processor is isolated from the rest of the system.
This architectu re of the cache memory is more complex because it has to
be able to command access to the rest of the system , lead ing to cost
i ncreasi n g . Another d i sadvantage is that the access to the system memory
is slower, because the main memory is accessed only after the cache.
Write tec h n i q ues

The write tech niq ues determine the way the cache memory solves a
writing cycle . The two used methods a re "write back" and "write
t h rou g h " . In "write back" method , the cache memory works l i ke a buffer.
When the processor i n itiates a writi ng cycle , the cache memory receives
the data and fi nal izes the cycle, and then when the system bus is available,
the cache memory writes the data into the main memory. This method
provides maxi m u m performance, allowi ng the processor to conti nue
workin g , while the main memory is updated later. The control of the writi ng
i nto the main memory i ncreases the cache memory complexity and costs .
I n the second method , "write throu g h " , the processor writes i nto the main
memory through the cache memory . The cache updated its content, but the
writi ng cycle conti n ues u ntil data is stored i nto the main memory. This
method is less com plex, so it is cheaper. Its performance is lower beca use
the processor must wait u ntil the main memory stores the data .

1 2 .3 Cache memory components

The cache subsystem can be d ivided i nto th ree fu nctional blocks :
SRAM , Tag RAM and the cache control ler. These blocks can be
implemented in more ch i ps or i n only one ch i p . The SRAM memory is the
static RAM memory block that keeps the data . Its d i me nsion d etermines the
d i mension of the cache memory. Tag RAM (TRAM ) is a small part of SRAM
that stores the addresses of the data from S RAM . The cache controller
manages the access to the cache memory. One of its tasks is to su pervise
the data flow requested by the processor, to refresh SRAM and TRAM , to
i mplement the writin g method . The cache controller has also the role to
1 32

The Cache Memory

determine if the memory access request is a cache h it or a cache miss. It is

not desirable for the whole PC memory to be loaded i nto the cache
memory. For example, the video memory cannot be loaded i nto the cache
memory; it is not "cacheable" .

1 2.4 Cache memory organization

In ord e r to u nderstand how the cache is organized and how it works ,
two notions a re defi ned : cache page and cache line.
Cache page

The main memory is d ivided i nto equal areas called cache pages .
The size of a page depends on the size of the cache memory and of its
organ ization .
Cache l i ne

A cache page is d ivided i nto smaller parts cal led cache lines. The
size of a cache line is determined by the processor and by the cache
memory arch itectu re .
I n fig u re 1 2 .4, w e see how the m a i n memory ca n be d ivided i nto
cache pages and l i nes.
D RAM

Memory

Cache Page

Cache Memory

Line m
-

Cache Page
Cache Page
Cache P age

Line

L i ne

Line

Fig . 12 . 4 Cache pages

F u l ly-Associative Cache

The organizing scheme allows each line from the main memory to be
stored at any location from the cache memory (fig . 1 2 . 5 ) . The fully
associative cache d oes not use cache pages , only cache lines. The main
memory and the cache memory are d ivided i nto equal size lines. For
1 33

The Cache Memory

example fig . 1 2 . 5 shows how line 1 from the main memory is stored i n line 0
from cache, but this is not the only possibility, l i n e 1 can be stored
anywhere in the cache memory, that is why it is ca lled "fu l ly-associative" . A
"ful ly-associative" scheme assures the best performance beca use any
memory location can be stored at any location of the cache memory. A
disadvantage is the complexity of th is system . The complexity appea rs
because we have to determine if the req uested data is i n the cache
memory in order to accomplish the time req u i rements . The cu rrent address
must be compared to all the addresses in the RAM , need ing a large
nu mber of com parisons, increasing the complexity and the i mplementation
costs for a large cache. That is the reason why th is type of cache is
commonly used only for caches smaller than 4Kbytes.
D RAM

Memory

Line m

Cache Memory

Line

L i ne

L i ne

....

\'

1\

Line m
-

'Ill

L i ne
Line
L i ne

1
O

Fig . 12 . 5 "Fully-Associative" Cache

D i rect mapped cache

The d i rect mapped cache is known as the fi rst type of associative

cache. Figure 1 2 . 6 presents a direct mapped cache scheme. In this
scheme , the main memory is d ivided i n cache pages. The size of each
page is equal to the size of the cache memory. The d i rect mapped cache
can store a certai n l i n e from the memory in a line from the cache memory.
For example: line 0 from any memory page will be stored i n line 0 from the
cache memory. If line 0 from page 0 is stored into the cache memory and
line 0 from page 1 is requested , line 0 from page 0 wil l be replaced with l i ne
0 from page 1 . This scheme maps directly a l i n e from memory to an
equivalent cache line; that leads to the name of "direct mapped cache".
1 34

The Cache Memory

For the d i rect mapped cache , the requested addresses wi l l be

compared with only one cache add ress , making the i mplementation less
complex and cheaper. The d isadvantage is the lack of flexi bil ity, i nvolving
poorer performances especially when changing cache pages.

DRAM Memory
I
Line n I II
I
I

/."" I

- I
I

Line 0

Cache memory

ine 0

Page 0

P if;g'e m
, -

Line nI ,'

Line n

Line n

Line 0

Fig . 12 . 6 Direct mapped cache

Set-Associative cache memory

A set-associative cache memory scheme is a combination between

the "fu l ly-associative" cache and the d i rect mapped cache. It d ivides the
cache i nto eq ual sections cal led cache ways (usually 2-4 sections). The
size of the cache page is equal to the size of the cache way. Each cache
way is treated as a smaller d i rect mapped cache. Figure 1 2 . 7 i s an example
that describes a two-way associative cache memory that allows stori ng two
memory pages anyti me.
This scheme is less complex than the fully-associative one because the
n umber of comparators is equal to the nu mber of cache ways . A two-way
associative cache needs only two comparators, which makes it cheaper.

1 35

The Cache Memory

Memory

DRAM

/I

'

Line n I
- I
I

L i ne

._

I
I
I

---------- ---------

L i ne n

Cache
Memory

I
I -

ine

Page

'

Page m

L i ne

I
I
I
I
I
I
I
I

I
I
I
I

Way

Way

L i ne n

L ine n

..._
.,,

L i ne

L i ne

: - - - - - - - - - - - - - - - - - -

Fig . 12 . 7 Two -way set- associative cache memory

1 2.5 The Penti um processors cache memory

The Penti um processors cache memory is implemented d ifferently
from the princi ples presented above. The fi rst d ifference is that the cache
memory is on the same chi p with the processor, so no external hardware is
necessary for using this cache, red ucing the costs of the system . An
advantage of th is i mplementation is the i ncreased response speed . For
example, a 1 O O M H z Penti um processor has the speed of the external bus
of 66MHz. Any externa l cache would work at a maximum speed of 6 6 M H z ,
but the i nternal cache works at 1 O O M Hz. An external interface can be
designed on 6 4 bits wh ile the internal interface and the processor buffer
work on 256 bits. The i ntegration of the cache memory into the central unit
i ncreases the system performances.
The thi rd d ifference is that the cache is d ivided into two separate
components to increase performances: data cache and code cache, each
havi ng 8Kbytes. This allows us to use the data and code cache pages
without overwriting them.
A Pentiu m processor system commonly has a n external cache. The
external cache is the second cache memory of the system and it is called
level-2 cache (L2). The processor internal cache is called level-1 cache
(L 1 ) . The name does not depend on the physical location of the memories
but on the way, the processor addresses them . Level L 1 is a lways
1 36

The Cache Memory

addressed before level L2. F ig . 1 2 . 8 shows how the L 1 and L2 cache work
in a Penti u m processor.
CPU

Ll Cache
Memory
L2 Cache
Memory
DRAM

System Interface
Fig . 12 . 8

Level - 2 cache at the Pentium processor

Cache memory organ ization and operat i n g modes

Both caches have the structu re of a two-way set-associative cache

memory. The cache l i ne size is of 32 bytes or 256 bits . A cache line is
loaded by a burst of four read operations from the processor 64-bit data
bus. Each cache way contains 1 28 cache lines. The cache page size is of
4Kbytes or 1 28 l i nes .
The write method for the Pentiu m processor allows software to control the
cache memory operati ng mode. The bits that control the cache memory,
from the processor control register CRO, are CD (Cache Disable) and NW
(Not Write through). The CD bit al lows the user to disable the processor
i nternal cache . When C D= 1 , the cache is disabled and when CD=O the
cache is enabled . The NW Bit allows the cache to use the Write Through
tech nique (NW=O) or the Write Back method (NW= 1 ).
Cache consistency

The Pentiu m processor maintains the cache consistency using the

M E S I protocol ( Mod ified Excl usive Shared I nvalid). The cache to decide if
i nformation must be refreshed uses the protocol or not. The Pentium
processor i mplements two fu nctions to allow the i nternal cache to be
consistent: snoop cycles and fl ush ing cycles. The Penti u m processor
snoops the system bus d uri ng memory transfers : when another bus master
device performs a writing operation , the Penti um processor su pervises the
address . If the processor has the data , it wil l i n itial ize a Write Back
operation . The cache flushing is the mechanism used by the Pentium
processor to clear the cache . A cache evacuation may occur due to
1 37

The Cache Memory

hardware or software causes. During an evacuation , the Pentium processor

rewrites all the d i rty (modified ) data , and then invalidates the cache (makes
the l ines unavailable). After doing this, it wil l generate a special bus cycle
cal led "Flush Acknowledge" . This signal allows the secondary level cache
(L2) to evacuate its content.

1 2.6 Cache memory characteristics identification

The C PU I D instruction may return information about the size and
characteristics of the internal cache memory. When register EAX is
initialized with value 2 , CPU I D instruction loads i nto registers EAX, EBX,
ECX, EDX values indicating characteristics of the processor cache . The 8
"lower" bits from EAX (AL) contain a value that identifies how many times
CPU I D must be executed to obtain a complete image of the processor
cache . For example, Pentium Pro processor returns 1 in AL, indicating that
CPU I D must be executed just once (with parameter EAX=2) to obtain a
complete i mage of the processor configuration .
EAX, EBX, ECX and EDX contain 8 valid descriptor bits . Table 1 2 .6 shows
that when bit 3 1 =0 ; the register contains 8-bit valid descri ptors. Table 1 2 .7
shows thei r val ues and the corresponding characteristics.
Bit3 1 Descriptor type
Reserved
1
S -bit
de s c r ip t o r s

Description
Re s e rved
De s c r iptors ind i c a t e a tab l e con t a ining
the
to
pa rame t e r s
ident i fy
the
charac t e r i s t i c s o f the cache memory

Table 12 . 6 . Descriptors
Descriptor
value
o oh
O lh
02h
03h
04h
06h
OSh
OAh
O Ch
4 0h

Cache description
Nu l l
I n s t ru c t i ons TLB , 4 K page s , 4 - way a s s o c i a t ive , 3 2
i npu t s
I n s t ru c t ions TLB , 4M page s , f u l l y a s s o c i a t ive , 3 2
i nput s
D a t a TLB , 4 K page s , 4 - way a s s co c i a t ive , 6 4 input s
D a t a TLB , 4M page s , 4 - way a s s c oc i a t ive , s inpu t s
I ns t ru c t i ons cache , S K , 4 - way a s s co c i a t ive , 3 2 - byt e
l ine s
I n s t ru c t i ons cache , 1 6 K , 4 - way a s s coc i at ive , 3 2 - byte
l in e s
D a t a cache , S K , 2 - way a s s o c i a t ive , 3 2 - byte l in e s
D a t a cache , 1 6 K , 4 - way a s s co c i a t ive , 3 2 - byte l in e s
Does not have l evel L2 cache ( P 6 f ami ly ) or L 3 ( P4 )

1 38

The Cache Memory

4 lh
42h
43h
44h
4 5h
5 0h
S lh
52h
S bh
S ch
S dh
6 6h
7 0h
7 9h
7 ah
7bh
7ch
82h
8 3h
84h
8 5h

Un i f i ed c ache , 3 2 - byte l ines , 4 - way a s s co c i a t i ve , 1 2 8 K

Un i f i e d cache , 3 2 - byte l ine s , 4 - way a s s co c i at ive , 2 5 6 K
Un i f i ed cache , 3 2 - byte l ines , 4 - way a s s c o c i a t ive , 5 1 2 K
Uni f i ed cache , 3 2 - byte l ines , 4 - way a s s c o c i a t ive , lM
Un i f i e d cache , 3 2 - byte l ines , 4 - way a s s co c i a t ive , 2 K
I n s t ruc t i ons TLB , 4 K&2MB 4MB page s , 6 4 i npu t s
I n s t ruct i on s TLB , 4 K&2MB 4MB page s , 1 2 8 input s
I n s t ruct i ons TLB , 4 K&2MB 4MB page s , 2 5 6 i nput s
D a t a TLB , 4 K&4MB page s , 6 4 input s
D a t a TLB , 4 K&4MB page s , 1 2 8 inpu t s
D a t a TLB , 4 K&4MB page s , 2 5 6 input s
D a t a cache , B k , 4 - way a s s co c i a t ive , 6 4 - by t e l ines
I ns t ruct i ons t race cache , 1 2 K Op s , 4 - way a s s oc i a t ive
L 2 cache , 1 2 8 K , 8 - way a s s co c i a t ive , 6 4 - byte l ine s
L2 c ache , 2 5 6 K , 8 - way a s s co c i a t ive , 6 4 - by t e l ines
L2 cache , 5 1 2 K , 8 - way a s s coc i at ive , 6 4 - by t e l ines
L2 c ache , lM , 8 - way a s s co c i a t ive , 6 4 - by t e l in e s
Uni f i e d cache , 3 2 - byte l ine s , 8 - way a s s coc i a t ive , 2 5 6 K
Un i f i ed cache , 3 2 - byte l ines , 8 - way a s s co c i a t ive , 5 1 2 K
Un i f i e d cache , 3 2 - byte l i nes , 8 - way a s s co c i a t ive , lM
Un i f ied cache , 3 2 - byte l ines , 8 - way a s s c o c i a t ive , 2 M

/
/
/

Table 12 . 7 Decoded descriptors value

TLB (Translation Lookaside Buffer)

A program typically accesses only a few of its pages at time and
accesses them repetitively.
TLB contains a mapping of virtual page number (the TAG) to a
physical page number. TLB typically contains 98% or more of the pages
accessed . Typical size is 64-1 28 entries. Small TLB can be made fully
associative.
Remark.

1 2 .7 Exercise
a.

Using the Turbo Debugger - TD32 a n d the CPU I D instruction , identify

the cache memory characteristics on the workstation.

b.

Write an application t o identify the cache memory characteristics for

non lntel processors, according to the appendix.

1 39

Appendix 1 - X86 processors identification

Appendix 1
EFLAGS register can be modified using several instructions and it is used
for branching programs (arithmetic flags) and to control the processor.

FLAGS/EFLAGS regi s ter ( 1 6 / 3 2 b i t )

3
1

... 2 2 2 1 1
... 2 1 0 9 8

1
7

1 1 1
6 5 4

1
2

1
1

N
T

I OPL

I
N
A v R
0
I I
T
D
c M F
p F

IOPL

v v

1
3

1
9 8 7 6
0

4 3 2 1 0

D I T s z
p
A
c
0
0
1
F F F F F F
F
F
F
D I T s z
p
A
c
0
0
1
F F F F F F
F
F
F

Bi t

Label

Description

0
2
4
6
7
8
9
10
11
12 - 13
14
16
17
18
19
20
21

CF
PF
AF
ZF
SF
TF
IF
DF
OF
IOPL
NT
RF

Ca rry f l ag
P a r i t y f l ag
Aux i l iary carry f l ag
Z e r o f l ag
S ign f l ag
Trap f l ag
I n t e rrupt enab l e f l ag
D i re c t i on f l ag
Ove r f l ow f l ag
I / O Privi l ege l eve l
Ne s t e d t a s k f l ag
Re sume f l ag
Vi rtual 8 0 8 6 mode f l ag
Al ignment check f l ag 4 8 6 + )
Vi rtual inte rrup t f l ag
Virtual inte rrup t pending f l ag
I D f l ag

VM

AC
VIF
VIP
ID

141

Appendix 1 - X86 processors identification

Type Fam .

Model

0100
0100
0100
0100
0100

0000/1
0010
0011
0011
0011

xxxx

00
00
00

0100
0100
0100

0100
0101
0111

xxxx

00
00
01
00
00

0100
0100

1000
1000

xxxx

0101
0101

0001
0010

xxxx

01

0101

0001

xxxx

01

0101

0010

xxxx

01

0101

0011

xxxx

00

0101

0100

xxxx

01

0101

0100

xxxx

00
00
00

0110
0110
0110

0001
0011
0101

xxxx

00
00

0110
0110

0110
0111

xxxx

xxxx

01

0110

0011

xxxx

00

0110

1000

xxxx

00

0110

1010

xxxx

00

0110

1011

xxxx

00

1111

O O Ox

xxxx

Table

Al . l

Notes :

Description

Version

00
00
00
00
00

xxxx
xxxx
xxxx

xxxx

xxxx
xxxx

xxxx

xxxx

xxxx
xxxx

,,,
(l)
\i)
\lI
\ii
,,,
\11
,,,

,,,
\>J

""
(2)

I' I

(l)

(2)

I' I
(l)

(l)
"'
\l I

(2)
('!

(l)
"'

"'

\;)
l'J

Int e l
Intel
Int e l
I nt e l
Int e l

486
486
487
DX2
DX2

Int e l 4 8 6
Int e l 4 8 6
Int e l DX2
support
Int e l DX4
Int e l DX4

DX proce s s or
SX proc e s s o r
p roc e s sor
proc e s sor
Ove rdr ive proc e s sor
S L proce s s or
SX2 proce s s or
proc e s sor with Wr i t e Back
proce s s or
Ove rdrive proce s s or

Pent ium proce s s or ( 6 0 6 6 )

Pent ium proc e s s or ( 7 5 , 9 0 , 1 0 0 ,
12 0 , 13 3 , 1 5 0 , 1 6 6 , 2 0 0 )
Pent ium Ove rdr ive proc e s s o r ( 6 0 , 6 6 )
/

Pent ium Ove rdr ive proc e s sor

( 75 , 90 , 1 0 0 , 12 0 , 133 )
Pent ium Ove rdr ive proce s s or f o r
Int e l 4 8 6
Pent ium MMX proce s s or ( 1 6 6 , 2 0 0 )
Pent ium Ove rdrive proce s s or
( 75 , 90 , 1 0 0 , 12 0 , 13 3 )
Pent ium Pro proce s s or
Pent ium I I proc e s sor , mode l 3
Pent ium I I , mode l 5 , Pent ium I I
Xeon and Int e l Ce l e ron , mode l 5
proce s s ors
Int e l Ce l e ron proc e s sor , mode l 6
Pent ium I I I and Pent ium I I I Xeon ,
mode l 7 proc e s s ors
Pro c e s o r Pent ium I I Ove rdr ive
Pen t i um I I I / Xeon/ C e l e ron , mode l 8
proce s s o r s
Pent ium I I I Xeon proc e s s o r , mode l A
Pent ium I I I proc e s s o r , mode l B
Pent ium IV proc e s sor ,

I nt e l Xeon

The Intel processors signature beginning with Intel 4 8 6

l . Th i s proc e s s o r doe s not have the CPUID imp l ement ed .

2 . Re f e r t o eve ry proc e s sor documentat i on f o r the l a s t l i s t
of " s t epp ing numbers "
3 . The s t epp ing 3 does imp l ement CPUI D

1 42

Appendix 1 - X86 processors identification

Fig .

Al . 1

Pentium 4 processor resources extracted wi th

AMD ' s CPU - Z application .

1 43

Appendix 2- The real time clock and the CMOS memory

Appendix 2
The CMOS memory content
Address

Signi ficance

O O h - O dh Locat i on s u s e d
reg i s t e r s
POST ( Power
Oeh
On S e l f T e s t )
s t at u s b i t s

Ofh

Shut down
s t atus byt e
( the shut down
caus e )

by the real t ime c l ock and the s t atus

D7
D6
DS
D4

1 - ba t t e ry supp ly mi s s i ng
1 - inva l i d checksum
1 - wrong reg i s t ered conf igura t i on
1 - wrong RAM s i z e

D3
D2
Dl
DO
DO

1 - HDD out o f orde r

1 - summe r t ime t ab l e
0
0
s o f t r e s e t ( CTR+DEL+RESET ) or unexp e c t e d
re s e t
Shut down a f t e r memory s i z e de t e rmining
Shut down a f t e r memory t e s t
Shut down a f t e r memo ry p a r i t y e rror
Shutdown a f t e r a l oader boot s t rap
reque s t
Shut down a f t e r a FAR JMP
Shut down a f t e r s a f e mode exi t
Shut down a f t e r movi ng memory b l ocks
( s ee INT 1 5 h )
F i r s t driver typ e

D1
D2
D3
D4
DS
D6
D7

l Oh

l lh
12h

13h

F l oppy d i s k
driver type

( Re s e rved )
HDD type

D7 D4
D3 DO
D7 D4
D3 DO

F i r s t HDD
Se cond HDD

( Re s erve d )
D7 D6
DS D4

1 5 - 1 6h
1 7 - 18h

Second driver type

F l oppy d i s k driver
00-1
10-3 , 11-4
01-2
D i sp l ay driver
0 0 - not ins t a l l ed
0 1 - 4 0 c lm - CGA , EGA , VGA
1 0 - 8 0 c lm - CGA , EGA , VGA
1 1 - Monochrome TTL
D3
0
D2
0
D1
! - Coproce s s o r i ns t a l l e d
DO
1 - F l oppy d i s k driver i ns t a l l ed
B a s e memory s i z e
1 0 0 h = 2 5 6 k , 2 0 0 h= 5 1 2 k , 2 8 0h = 6 4 0 k
Ext ended memory addr e s s ( over lM ) - 0 - 3 c 0 0 h in M
I

1 44

'

Appendix 2- The real time clock and the CMOS memory

1 9h
C hard d i s k type ( i s > 1 5 )
c D hard d i s k typ e ( i s > 1 5 )
l ah
lbh - 2 0h ( Re s e rved )
2 1h - 2 dh ( Re s e rved )
2 eh - 2 fh Locat i on s used f o r the checksum o f l ocat ions f rom addre s s
l O H - 2 0H f rom CMOS memory
3 0h - 3 1 h Ext ended memory addre s s ( over l M ) , in Kbyt e s
32h
Current century i n BCD forma t ( year high dig i t s )
3 3h
B 7 ind i c a t e s 1 2 8 k ext ended memory pres ence ; B 6 i s u s e d by
S ETUP , e t c .
3 4 h - 3 fh Used di f f e rent l y , depending o n the sys t em typ e . Some sys t ems
use 3 8 h - 7 fh l o c a t i on s f o r p a s sword con t r o l and boot type .
Other s y s t ems u s e f o r thi s purpose the l o c a t i on s 7 8 h - 7 fh .
For AM I B I O S
3 4 h p a s sword cont r o l
B7 - B6
0 0 d i s connec t p a s sword
10
1 1 s e t p a s sword
1 1 s e t up p a s sword
3 8 - 3 dh ( AM I ) or 4 8 - 3 fh ( I BM P S / 2 ) encryp t e d p a s s word
3 Ch - boot typ e ( AM I )
B 7 - v i ru s check
BO
Boot A , then C I Boot C , then A
Other sys t ems u s e l ocat ions for :
- S e cond HDD type s aving , 4 8 type chara c t e r i s t i c s ( PHOEN I X )
- S c reen c o l o r s f o r s e tup ( AWARD )
-

The memory locations with addresses between 1 Oh and 20h are protected by
a checksum mechanism. At reset, if the checksum does not equal the data
stored at addresses 2eh - 2fh , the CMOS memory setup routine from B I OS is
cal led .
Addr .

Extended content of the CMOS memory

( AWARD )
B7 Motherboard c h i p s e t ( S i s 8 5 C 5 0 1 / 8 5 C 5 0 2 )
B O Aut omat i c conf i gurat i on not used ( l unu s e d )
( AM I )
4 1h
B 7 - B 6 awa i t ing t ime f o r I OR/ I OW cyc l e
B 5 - B4 awa i t ing t ime f o r D MA cyc l e f o r 1 6 b i t channe l s
B 3 - B 2 awa i t ing t ime f o r D MA cyc l e for 8 bit channe l s
B l EMR
undocument e d
BO
4 2 h - 4 4 h - ( AWARD ) Mothe rboard chip s e t s e t t i ngs
( AM I )
44h
B4 NM ! Announc e supp l y int e r rupt
B 3 NMI Local bu s exp i red

4 0h

1 45

Appendix 2- The real time clock and the CMOS memory

4 5h

4 6h

4 7h
5 0h
5 lh

52h
53h

( AWARD )
B 7 - B 6 AT Bus de l ay at b i t 3 8
B 5 - B4 AT Bus de l ay at b i t 1 6
B 3 - B2 AT Bus de l ay at b i t 8
B l - B O AT I / O bus de l ay
( AM I )
( Error : l = unu s e d )
B 7 B I OS Sys t em Cacheab l e
( Error : l = unu s e d )
B 6 V i de o B I OS Cacheab l e
B 6 - B O not used
- ( AM I )
B 7 - B 6 AT Bus de l ay at b i t 3 8
B 5 - B4 AT Bus de l ay at b i t 1 6
B 3 - B 2 AT Bus de l ay at b i t 8
B l - B O AT I / O bus de l ay
- ( AWARD ) Motherboard chip s e t s e t t i ngs
- ( AWARD ) P C I s l ot l , l a t ency 0 - 2 5 5 ( e rror : 0 )
( AM I )
B7 B ank 0 / 1 pre l oad RAS
B 6 B ank 0 / 1 acce s s w i t h Wa i t S t a t e s
B 3 - 2 Bank 0 / 1 Wa i t S t a t e s
( AWARD ) P C I s l ot l s e t t ings
B7 P I RQ O # t r i ggered inte rrup t s
0 = o n edge
l = on l eve l
B 6 - B 2 not in use
B 0 - 1 S l o t 1 IRQ s e t t ings
O O = A- P I RQO ( Erro r )
O l = B - P I RQ l
l O = C - P I RQ2
l l = D - P I RQ3
- ( AWARD ) P C I s l ot 2 , l a t ency 0 - 2 5 5 ( e rror : 0 )
( AWARD ) P C I s l o t 2 s e t t ings
( AM I )

B7
Bank 2 / 3 p re l oad RAS
B6
Bank 2 / 3 acce s s w i t h Wa i t S t a t e s
B 3 - B2
Bank 2 / 3 Wa i t s t a t e s
5 4 h ( AWARD ) P C I s l ot 3 ' l a t ency 0 - 2 5 5 ( e rror : O )
5 5 h - ( AWARD ) P C I s l ot 3 s e t t ings
5 6h - ( AWARD ) P C I s l o t 4 , l a t ency 0 - 2 5 5 ( e rror : O )
5 7 h - ( AWARD ) P C I s l o t 4 s e t t ings
5 8 h - ( AWARD ) r e s e rved for PCI bus s l ot 5
B3 on board CMD IDE Mode 3
5 9h - ( AWARD ) P C I s l o t 5 s e t t ings
5Ah - ( AWARD ) I RQ s e t t ings f o r PCI bus
B4 - B 7 P I RQ 3 # Interrupted l ine ( O =noth ing , Bh= I RQ l l , e t c )
B O - B 3 P I RQ O # Inte rrup t e d l ine
5Bh- ( AWARD ) I RQ s e t t ings for PCI bus
B4 - B 7 P I RQ3 # Inte rrup t ed l ine ( O =nothing , Bh= I RQ l l , e t c )
B O - B 3 P I RQ 2 # Inte rrrupted l ine
5 Ch - 5 Fh - ( AWARD ) not used
60h - ( AWARD ) Power management
B7
not used

1 46

Appendix 2- The real time clock and the CMOS memory

B6 V i de o o f f me thod
l =V/ H SYNC + B l ank ( erro r )
0 = empty s c reen
B4 - B 5 Video o f f op t i ons
O O =Al ways On
O l = Suspended - > o f f
l O = Su s pended , S t and by - >O f f
l l =Al l mode s - > O f f
P M c ont ro l l e d by APM ( l =DA )
B3
B2
not used
B O - B l Power management s e t t ings
O O =D e f ined u s e r
O l = D i s connec t e d
l O =M i n imum s aving o n powe r down ( 4 0 m i n f o r any event )
l l =Maximum s aving on power down ( 2 0 s e c f o r any event )
6 1h - ( AWARD ) Powe r management
B 7 PM on HDD port act ivi t i e s ( 1 = inva l i d )
B 6 P M o n LTP port act ivi t i e s ( l = inva l i d )
B 5 P M o n COM port act iv i t i e s ( l = inva l i d )
B 4 Power down suspend
B O - B 3 HDD Power down t ime 0 - D i s conne c t e d ,
1 - 1 5min T i me ( in minut e s )
6 2 h - ( AWARD ) Powe r management
B 7 - B4 S t andby mode s e t t i ngs ( f or def ined u s e r s )
D i s conne c t e d
o
2 0 sec
1
1 min
2
3
5 min
1 0 min
4
1 5 min
5
2 0 min
6
7
3 0 min
B
4 0 min
B O - B 3 mode s e t t ings ( f or de f ined u s e r s )
6 3 h - ( AWARD ) Power management
B 7 PM event d i s c onne c t e d for I RQ3 a c t i v i t y ( COM2 )
( l = d i s conne c t e d )
B 6 P M event f o r VGA a c t ivity ( l = d i s conne c t e d )
B5 not used
B4 P M event o n PCI / I SA
B O - B 3 Suspends mode s e t t ings ( f or de f ined u s e r s )
6 4 h - ( AWARD ) Powe r management ( PM )
B 7 P M event d i s connec t e d o n I RQ l l act ivi ty ( l =di s conne c t e d )
B 6 P M event d i s c onne c t e d o n IRQ l O a c t i v i t y ( l =d i s c onnec t ed )
B 5 P M event d i s conne c t ed o n IRQ9 act ivity ( l = d i s conne c t e d )
B4 PM event d i s connec t ed o n I RQB act ivity ( l = d i s conne c t e d )
B 3 P M event d i s conne c t e d o n I RQ7 act ivity ( l =di s conne c t e d )
B 2 P M event d i s conne c t e d o n I RQ 6 act iv i t y ( l =di s conne c t ed )
B l P M event d i s conne c t e d o n IRQ5 ( l = d i s c onne c t e d )
B O PM event di s c onne c t e d o n I RQ4 act ivity ( l =di s c onne c t e d )
6 5h - ( AWARD ) Power management
B 7 - B4 not u s e d

1 47

Appendix 2- The real time clock and the CMOS memory

B3 PM event di s conne cted on IRQ 1 5 a c t i v i t y ( l = d i s conne c t e d )
B 2 PM event d i s conne c t e d on IRQ 1 4 a c t i v i t y ( l = d i s conne c t e d )
B l PM event di s conne c t e d on I RQ 1 3 act ivity ( l = d i s conne c t e d )
B O PM event d i s c onne c t e d on IRQ 1 2 a c t i v i t y ( l = d i s c onne c t e d )
6 6 h - 7 9h - ( AWARD ) not used
6 8 h - 6 Fh - ( AWARD ) IDE HDD parame t e r s f o r f i r s t drive on
s e c ondary IDE port
7 0 h - 7 7h - ( AWARD ) IDE HDD parame t e r s for the s e cond drive on
s e c ondary IDE port
7Ah - ( AWARD ) CMOS ext ended checksum , h i gh byt e
7Bh - ( AWARD ) CMOS ext ended checksum , l ow byt e ( The ext ended
checksum i s the a r i t hme t i c sum o f a l l byt e s )

1 48

Appendix 3

Designing /SA-Bus Compliant Boards

Appendix
PC

1/0

map - reserved port addresses

Port address

Reserved for

0 0 0 - 0 l Fh

DMA Con t ro l l er - s l ave ( 8 2 3 7 -A5 )

0 2 0 - 0 2 lh

P I C - mas t e r ( 8 2 5 9A )

0 4 0 - 0 S Fh ( 4 0 - 4 3 h )

T ime r 8 2 5 4

0 6 0 - 0 6 Fh ( 6 0 - 6 3 h )

Keyboard Con t ro l l e r 8 0 4 2

0 7 0 - 0 7 Fh

Rea l T ime C l ock

0 8 0 - 0 9 Fh ( 8 0 - 8 3 h )

Page Reg i s t e r 7 4 LS 6 1 2

( ! 8 2 5 3 - 5 PC - XT )
( I 8 2 5 5A - P C - XT )

OAO - O B Fh

P I C - s l ave

O C O - ODFh

DMA Con t ro l l e r - ma s t e r ( 8 2 3 7 - A5 )

( 8 2 5 9A)

O FOh

C l ear FPU act ive

OFlh

Re s e t FPU

O F 8 - 0 FFh

FPU

1 7 0 - 177h

IDE s e condary ( HD )

1F0 - 1F7h

I D E pr imary ( HD )

2 0 0 - 2 0 7h

Game Adap tor / Joys t i ck

2 7 8 - 2 7 Fh

LPT2

2 B 0 - 2 DFh

EGA Card

2Elh

G P I B Adaptor

2E2 - 2E3h

Data acqu i s i t i on ( 0 )

2 E 8 - 2 E fh

COM4

2 F 8 - 2 FFh

COM2

(O)

3 0 0 - 3 1 Fh

Ext e rnal cards

3 3 0 - 3 3 lh

Audi o board

3 6 0 - 3 63h

Network c a rd ( addre s s l o w )

3 6 4 - 3 67h

Re s e rved

3 6 8 - 3 6 Bh

Net work card ( addre s s h igh )

3 6 C - 3 6 Fh

Re s e rved

3 7 8 - 3 7 Fh

LPTl

3 8 0 - 3 8 Fh

SDLC

3A0 - 3AFh

Bi synchronous 1

3 BC - 3 B Fh

MDA+LPT

3 C 0 - 3 CFh

EGA card

3 D 0 - 3 DFh

CGA card

3 E 8 - 3 E Fh

COM3

3 F 0 - 3 F7h

FD Cont ro l l er

3 F 8 - 3 FFh

COM l

1 49

Appendix 3

Designing /SA-Bus Compliant Boards

The ISA-Bus pin assigning

Cwum:tor Pin Alloatlon=

SokltrSidt
CND
Rf5!ff
+5V
lll02/9
sv
OllQ2
-IW
OWSt12V
(;ND.
MEMWMl!'Mll
IOW
!OROJ\CP-

!lRQJ
DACK!

l.IRQJ

IUWIU!SHS'l'S(;U:

1llQ7
UIQ6
IRQ5
IR()4
lllQJ
l)ACX2
TIC
A.I.I!
+SV
osc
GND

ConnIOf Pin Al
SoturSid

81
82
BJ
64
w;
llO
It'
1!11
1>
11!0
811
1112
BIJ
BH
615
616
Dl7
81
Rl9
BX>
BZ1
Bl1

MF.Ml<>JOCSlt>lllQIO
U!Qll

OIQ12
l!lQJS
IRQM
DllCKO

DRQO
nllCK'i-

D.llQS
l)ACKh-

nR
01\CX"/

c--m
Ol
m
1)4
05
f')6
[l'7
l.l8
"'
DIO
Ill!
Dl2
OU
014

DRQ7

nt5

<5V
MA!>TER
QI()

Dl6
011
l>I

823
1124
B'l5
1126
IJl7
D2ll
il2'l
bl
1131

A rninw. (-)sign Mier a signal lndlall!S

lhat it il> 'C'l!v low'.

150

emu;.
LAZI
LAZZ
LUI
U\20
1.Al<I
LAIS
tA17
Ml!MRMl!M\'{ll8
09
DIO
DI!
011
013
llH
D15

Compon...t 5\d
CJ
C2
Cl
C4
C5
a
(.7
Cll
C9
CIO
Cit
en
Cl-'I
Cl.f
CI5
C!6
C\7
C\8

1/0CHCKV1
Ll6
t:l!!
D4
w
Dl
Ill
[l(l
l/OOIRJJY
Al\N
A
AU
Al?
Al6
Al5
AH
t\13
Al2
All
AlO
,..,

Al
Al
A1
A4
AS
M
A1
AS
119
AlO
All
Al2
AH
Al4
AIS
Al.I>
A.l'l
All
Al9
A2C
All
"22

Al!

A23

"'
""
A5
A4
A3
.\2
Al
AO

A24

A26
Ail
A'.lll
A29
/\JlJ
All

Appendix4 - The Parallel Port in IBM-PC Computers

Appendix 4
The application board use a 1 6-character LCD , on single line,
PVC 1 60 1 0 1 P(N}. The display has more parts: the d isplay itself, a
microcontroller, a DDRAM (Display Data RAM } memory and a CGRAM
(Character Generator RAM} . The d isplay connector has 1 4 pins:

Pin

Signal

I/O

Function

1
2
3
4
5
6

GND
Von
Vo
RS
R/W
EN

7+14

DB O+DB 7

I
I
I
I
I
I
I

Ground
Log i c a l supp l y
LCD cont ra s t
Reg i s t e r s e l e c t i on
LCD read/wr i t e
Ac t ivat i on s igna l
Data bus

Pins 7-1 0 : D80-DB3 - 1/0 pins for data read/write from/to the d isplay
(will not be used for 4-bit transfers};
Pins 1 1 - 1 4: D 84-D87 - 1/0 pins for communication with the d isplay
(these are the pins used i n the case of 4-bit transfers};
Pin 5 : R/W - selection signal for read/write from/to the d isplay;
Pin 4 : RS - selection signal for the internal register; using the i nternal
register the d isplay can be programmed
0 = instructions register;
1 =data register;
Pin 2 : VDD - supply voltage for the display internal log ic;
Pin 3 : Vo - varying voltage applied to the display for contrast control;
P i n 1 : G N D - g round;
Pin 6 : E N (enable} - the activation of this pin selects the d isplay

The instruction register contains the command code (clear display,

cursor moving}; it is write only.
The d ata register contains the data that wil l be written i n DDRAM or
CG RAM .
The table below contains the typical commands for the LCD control .

1 51

Appendix4 - The Parallel Port in IBM-PC Computers

Command

Cl ear
display

CODE
DB DB DB DB DB DB DB DB
RS R/'i'l
7 6 5 4 3
2
1
0
0

Description
C l e a r s a l l d i s p l ay memory
and returns the cursor to
t h e home pos i t ion

Execut i on
t ime

l . 64s

Returns the cursor t o the

Re turn
home

Entry
mode set

home pos i t i on ( addre s s O ) .

A l s o returns the d i s p l ay
b e i ng s h i f t e d t o the
original pos i t i on . DDRAM
content s rema in unchanged .

l . 64s

S e t s the cursor move

direc t i on and spec i f i e s or
0

I /D

not to s h i f t the d i s p l ay .
The s e operat i ons are
perf ormed dur i ng data wr i t e

4 0 s

and read .

D i splay
ON/OFF
control

Cursor or
display
0
shi ft

1 S / C R/L

Func tion
set

1 DL

D i sp l ay ON/ O F F contro l . The

memory rema i n s unchanged in
O F F condi t i on . Cu rsor
ON/ O F F or b l inking .
Move s

Set CGRAM
0
address

MSB ACG

LSB

the cursor and s h i f t s

the d i s p l ay w i t hout
chanq ing DDRAM content s .
S e t s i n t e r f a c e d a t a l engt h
( DL ) , numb e r of d i sp l ay
l i nes ( N ) and chara c t e r
f ont

4 0s

4 0s

4 0s

(F)

S e t s the CGRAM addre s s .

CGRAM data is sent and
rece ived a f t e r t h i s

40s

s e t t i ng .

Set DDRAM
0
addr e s s

MSB ADD

S e t s t h e DDRAM addre s s .
DDRAM data is s ent and
LSB
rece ived a f t e r t h i s

4 0s

s e t t i ng .
Reads Busy F l ag

Read busy
f l ag &
0
address
Wri t e
data in
1
CG or
DDRAM
Read data
from CG
1
o r DDRAM

BF

M S B AC

W r i t e da ta

Re ad data

( BF ) ;

indi c a t e i n t e rnal operat i on

LSB i s b e i ng perf ormed and
r e a d s addre s s coun t e r
content s .

Wr i t e s i n t o DDRAM o r CGRAM

Reads dat a f rom CGRAM or

DDRAM

152

4 0 s

4 0s

4 0 s

Appendix4 - The Parallel Port in IBM-PC Computers

Flags:
Accompan i e s d i s p l ay s h i f t when
data is wr i t t en . For norma l
operat i ons , s e t to

S=l

I /D = l

I n c rement DL= l :

8 bits

I/D=O

Dec rement DL= O :

4 bits

S/C=l

D i s p l ay S h i f t N = l :

S / C= O

Cur s o r move N = 0 :

R/L= l

S r ight s h i f t F = l

R/L= l

Le f t s h i f t F = O :

BF=l
BF=O

(1)

l ine

l i ne

:5 1 0
5

dot s

DD RAM

C G RAM
ACG

Chara c t e r Gene rator

( CGRAM )

CGRAM addre s s

ADD

DDRAM component s addre s s ing

at DDRAM cursor addr e s s

AC

Inc rement e d for DDRAM and

CGRAM a l s o .

l = ON O = O F F
B l inking )

x 7 do t s

( Cursor -

l = ON O = O F F ( Cursor )

I n t e rn a l execut i on

Di s p l ay D a t a RAM

l = ON O =O F F ( D i s p l a y )
*

Ac cep t s i ns t ruct ions

Not r e l evant

DDRAM memory map for the 1 6x 1 character d isplay:

Character addresses:
Char.

JO

11

12

13

14

15

16

I 00 I 01 I 0 2 I 0 3 1 0 4 1 I 0 6 1 0 7 1 4 0 1 4 1 1 4 2 1 4 3 1 44 1 4 5 1 4 6 1 47 1
os

The DDRAM address is sent on 7 bits . Based on the memory map, one can
establish the addresses to be sent to the data bus d i rectly on 8 bits :
Character addresses:

From the physical address, O?h to 40h there are free memory
locations (to be used for other purposes) . To display the 1 6 characters , the
first 8 are displayed from address 80h and the next 8 from address CO.

1 53

Appendix 5- The Cache Memory

Appendix

The Cache memory characteristics identification for

non l ntel processors using

CPUID

instruction

The non l ntel processors follow the general lines of the CPU I D
returned information significance. For some families, some values have
other significance .
Many of the non l ntel processors accept extended levels of the
CPU I D instruction . Levels 80000005 and 80000006 return cache memory
descriptors for AMO and Cyrix families.
Regis ter

EAX

EBX

ECX

ECX

Cache des cription

4 M / 2 M L l TLB
Signi f i c ance
Bits
Dat a TLB a s s o c i a t ive ( FFh= fu l l y - a s s o c i a t ive )
31-24
Data TLB input s
23 - 16
Code TLB a s s oc i at ive ( FFh= fu l l y - a s s o c i a t ive )
15-8
Code TLB input s
7-0
4 k L l TLB
S igni f i cance
Bits
Data TLB as s o c i a t ive ( FFh= ful l y - a s s o c i at ive )
31 -24
Data TLB input s
23-16
Code TLB a s s oc i a t ive ( FFh= ful ly - as s o c i a t ive )
15-8
7-0
Code TLB input s
L l data ca che
S i gni f i cance
Bits
31-24
L l data cache s i z e in Koc t e t s
L l as sociat ive d a t a cache ( FFh= f u l l y 23-16
a s s o c i a t ive )
L l data cache l ine numb e r s
15-8
7-0
L l data cache l ine s i z e in oct e t s
L l code c ache
Bits
Signi f i cance
31-24
L l code cache s i ze in Koc t e t s
L l a s soc iat ive code cache ( FFh= fu l ly 2 3 - 16
a s s oc i at ive )
15 - 8
L l code cache l ine numbers
7-0
L l code cache l ine s i z e in oct e t s

T ab l e AS . 1

Decoded de scriptors value for l evel

cache L l and TLB

1 54

80000005

Appendix 5- The Cache Memory

Regis ter

Cache description
4 M / 2 M L2 TLB

EAX

31-28
2 7 - 16
1 5 - 12
11-0
4k Ll

EBX

ECX

Tab l e A S . 2 .

Bits

#1

Signi ficance

Bits

Data
Data
Code
Code
T1B # 1

T1B , a s s o c i a t ive
T1B input s
T1B , a s s o c i a t ive
T1B , input s

#2

Signi f icance

3 1 -28
27-16
1 5 - 12
11-0
Un i f i e d 12

Dat a T1B , a s s o c i a t ive

Data T1B , input s
Code TLB , a s s oc i at ive
Code T1B , input s
cache

3 1 - 15
23 - 16
15-8
7-0

L2
12
12
12

Bits

#2

#2
#2

Signi ficance

cache s i z e i n Koc t e t s
#2
a s s o c i a t ive cache
cache l ine s number
cache l ine s i z e i n o c t e t s

Dec oded de s c r ip t o r s va lue

c a c he L2

for

l eve l

80000005-

#1 TLB L2 u nified cache is indicated for value OOOOb in the most significant
positions
#2

OOOOb - L2 d isabled
000 1 b - d i rect mapping
00 1 0b - 2 ways
0 1 OOb - 4 ways
0 1 1 0b - 8 ways
1 000b - 1 6 ways
1 1 1 1 b - ful l

1 55

Appe ndix 5- The Cache Memory

Cpu-Z

[;..: '.

'

256 bits

Fig . AS . l Pentium processor Cache charac teristics

Fig . AS . 2 AMD processor Cache characteri stics

1 56

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RE F E R E N C ES

1 . Lupu, E . Microprocesoare. lndrumator de /aborator Risoprint 2000

2. Baruch , Z. Sisteme de intrare/ie$ire. lndrumator de laborator U .T. Pres 1 998
3. Tischer M . , Jennerich B. "LA BIBLE PC" PROGRAMMA TION S YS TEME.
M I C RO Application 1 997 Sixieme Edition
4. Nedevschi, S. Todora n , L. Microprocesoare UTCN 1 994
5. Rollins, D. Program Tech help V 6. 0. The electronic technical reference manual
Flambeaux Software, lnc. 1 995
6. Sztojanov, I. i col . De la poarta TTL la Microprocesor (vol. II) Ed . T E H N I C A
1 987
7 . [***]

www.pcguide. com

8. [***] "Microprocessors " I ntel 1 993

9. [***]

"Memory products " I ntel 1 993

1 0 . [***] " Intel Processor Identification and the CPU I D Instruction" AP-485 J u ly 2001
1 1 . [***] "AM O Processor Recognition" Application Note January 2002
1 2. Buchanan, W. PC interfacing, Communications and Windows Programing
Addison Wesley 1 999
1 3. [***] www.intel. com
1 4 . Lung u ,

V. Procesoare Intel. Programare in limbaj de asamblare.

1 5. [***] "Replacement for the M C 1 468 1 8" Application N ote 52 1

MAXIM Semiconductors 200 1

1 57

TEORA, 2000