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Comlementary CMOS Logic Gates: nMOS Pull-Down Network pMOS Pull-Up Network Static CMOS

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orengeneral

The document discusses complementary CMOS logic gates. It explains that CMOS gates are built using a pull-up pMOS network and a pull-down nMOS network. It provides examples of how to build CMOS gates from Boolean expressions by constructing the nMOS pull-down network from the uninverted expression and the pMOS pull-up network from the inverted expression. The document also discusses useful transformations between Boolean expressions and CMOS transistor-level schematics, including applying De Morgan's laws and reducing expressions to minimize the number of transistors needed.

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Comlementary CMOS Logic Gates: nMOS Pull-Down Network pMOS Pull-Up Network Static CMOS

Uploaded by

orengeneral
58 views12 pages
The document discusses complementary CMOS logic gates. It explains that CMOS gates are built using a pull-up pMOS network and a pull-down nMOS network. It provides examples of how to build CMOS gates from Boolean expressions by constructing the nMOS pull-down network from the uninverted expression and the pMOS pull-up network from the inverted expression. The document also discusses useful transformations between Boolean expressions and CMOS transistor-level schematics, including applying De Morgan's laws and reducing expressions to minimize the number of transistors needed.

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The document discusses complementary CMOS logic gates. It explains that CMOS gates are built using a pull-up pMOS network and a pull-down nMOS network. It provides examples of how to build CMOS gates from Boolean expressions by constructing the nMOS pull-down network from the uninverted expression and the pMOS pull-up network from the inverted expression. The document also discusses useful transformations between Boolean expressions and CMOS transistor-level schematics, including applying De Morgan's laws and reducing expressions to minimize the number of transistors needed.

Copyright:

© All Rights Reserved
Download as PDF, TXT or read online from Scribd
Download as pdf or txt
58 views12 pages

Comlementary CMOS Logic Gates: nMOS Pull-Down Network pMOS Pull-Up Network Static CMOS

Uploaded by

orengeneral
The document discusses complementary CMOS logic gates. It explains that CMOS gates are built using a pull-up pMOS network and a pull-down nMOS network. It provides examples of how to build CMOS gates from Boolean expressions by constructing the nMOS pull-down network from the uninverted expression and the pMOS pull-up network from the inverted expression. The document also discusses useful transformations between Boolean expressions and CMOS transistor-level schematics, including applying De Morgan's laws and reducing expressions to minimize the number of transistors needed.

Copyright:

© All Rights Reserved
Download as PDF, TXT or read online from Scribd
Download as pdf or txt
You are on page 1/ 12

Introduction

Advanced VLSI Design

CMPE 640

Complementary CMOS
Comlementary CMOS Logic Gates:
nMOS pull-down network
pMOS pull-up network
Static CMOS

pMOS
pull-up
network

inputs
output
nMOS
pull-down
network

Pull-down OFF

Pull-up OFF
Z (float)

Pull-up ON
1

Pull-down ON

X(Crowbar)

Complementary CMOS gates always produce


1 or 0
Pull-up network is complement (dual) of
pull-down network
1

Introduction

Advanced VLSI Design

CMPE 640

Building CMOS Gates (n-side)


CMOS is inherently inverting.
Gates with expression of the form F = ( exp ression ) are easier to build.
For making the n-side (pull-down network) use the un-inverted expression.
For e.g.: Implement F = ( ( A B ) + ( C D ) )
For n-side use F = ( A B ) + ( C D )
AND expressions are implemented using series connection of n transistors
OR expressions are implemented using parallel connection of n transistors
(A B)
AND: Series

(C D)

(A B) + (C D)

AND: Series

OR: Parallel

Introduction

Advanced VLSI Design

CMPE 640

Building CMOS Gates (p-side)


For making the p-side (pull-up network) invert the expression used for n-side.
For e.g.: Implement F = ( ( A B ) + ( C D ) )
For n-side use F = ( A B ) + ( C D ) (previous slide)
For p-side invert above expression: F = ( A + B ) ( C + D )
AND expressions are implemented using series connection of p transistors
OR expressions are implemented using parallel connection of p transistors
(A + B)

(C + D)

OR: Parallel

(A + B) (C + D)

OR: Parallel

AND: Series

Introduction

Advanced VLSI Design

CMPE 640

Building CMOS Gates (Final CMOS gate)


Combine the n-side (pull-down) and p-side (pull-up) to make the final gate.
F = ((A B) + (C D))

D
F

Introduction

Advanced VLSI Design

CMPE 640

Useful Transformations
You must know all the following transformations between levels of abstractions
Boolean expression
(with reductions)

1
2

CMOS transistor-level
schematic analysis

3
4

CMOS layout

(1) Boolean expression to CMOS transistor schematic


Previous analysis shows how to do this step
It assumes that the Boolean expression is already in the appropriate form, which may
not always be ture.
Boolean Expression Reduction
You should already know how to manipulate boolean expressions, e.g., using De
Morgan's Laws, from exercises in other courses.
The objective is to reduce a boolean expression so that it can be realized in full-complementary CMOS using the minimum number of transistors.
You are not expected to realize CMOS gates using pass structures in which the
inputs are used to drive the output of the gate. e.g. (Lecture 2: XOR, XNOR)
5

Advanced VLSI Design

Introduction

CMPE 640

Useful Transformations
The following heuristics can be applied as target reductions that will help you to obtain
minimum realizations:
Since CMOS is naturally inverting, you'll want to target a final expression of the
form:
F = ( expression )
Many times only uncomplemented literals are available as signals in your circuit.
Therefore, the reductions should attempt to remove the complemented literals in
the Boolean expression.
Application of De Morgan's Laws can be used to transform complemented literals
to NANDs and NORs.
You should analyze each transformation to learn the trade-offs.

Advanced VLSI Design

Introduction

CMPE 640

Transformation Examples
Let's try:
F = ( AB ) + ( C + D )E
The following reduction sequence can be applied that targets NANDs and removes the
complemented literals:
F = ( AB ) + ( C + D )E

Build Inverse : 14 Transistors

F = ( AB ) + ( C + D )E

Invert both sides.

F = AB ( C + D )E

How many transistors are needed here?

F = ( A + B ) ( C + D )E

F = A ( C + D )E + B ( C + D )E

Build here?:
F = ( A + B ) ( C + D )E
# transistors: 6 for OAI, 2 for
inverter for B, 6 for final OAI.
Multiply.

F = A ( C + D )E + B + ( C + D )E
F = A ( C + D )E + B + ( C + D )E

Or Build here?: 6 for OAI, 8 for B AOI,


6 for final AOI.
7

Advanced VLSI Design

Introduction

CMPE 640

Transformation Examples
Note that further reductions to NANDs and NORs may not pay off in the previous case.
In the next case, it is possible to get rid of an uncomplemented literal without increasing the
size of the OAI:
F = ( AB ) + ( C + D )E

Build Inverse : 16 Transistors

F = ( AB ) + ( C + D )E

Invert both sides.

F = AB ( C + D )E

Apply DeMorgan's Laws.

F = ( A + B ) ( C + D )E

Build here?:
F = ( A + B ) ( C + D )E
# transistors: 6 for OAI, 4 for
inverters, 6 for final OAI.

F = (A + B)(C + D + E)

Or Build here?: 4 for NOR, 2 for


inverter, 8 for final OAI.

Further transformations are not useful -- convince yourself.


8

Introduction

Advanced VLSI Design

CMPE 640

Transformation Examples
Expressions with repeated variables may be simplified to save a couple transistors
F = ABC + ACD
F = ABC + ACD

4 + 2 + 10 + 2

F = ( A + BC ) ( A + CD )

2 + 4 + 10

F = AA + ACD + ABC + BCCD


BCCD is redundant (covered) by the other terms, e.g,
F = ACD + BC ( A + CD ) = ACD + BC ( A + ACD )
F = ACD + ABC

2 + 4 + 10

F = ( A + CD ) + ABC
F = ( A + CD ) + ABC

6 + 8 ( 14 !)

Advanced VLSI Design

Introduction

CMPE 640

Transformation Examples
In contrast to:
F = ( AB ) + ( A + C )D
F = ( AB ) + ( A + C )D
F = ( A + B ) ( A + C )D
F = ( A + B ) ( AD + CD )
F = (A + B)(A + D)(C + D)

F = ( AB ) ( A + C )D
6 for AB NAND, 8 for OAI,
4 for final NAND.
F = ( A + B ) ( A + C )D
8 for OAI, 2 for inverted B,
6 for final OAI.

F = ( AA + AD + AB + BD ) ( C + D )
F = ABC + ABD + ADC + ADD + BDC + BDD
F = ABC + ABD + AD + BD
F = ABC + D ( A + B )
F = (A + B + C) + D(A + B)

6 for NOR, 2 for inverter,


8 for final OAI -- no better than
the earlier expression.

10

Introduction

Advanced VLSI Design

CMPE 640

Transformation Examples
Sometimes it is best to implement the inverse function and add an inverter.
For example, Carry, which has all uncomplemented inputs.
Carry = AB + C in ( A + B )
Carry = AB + C in ( A + B )
What about XOR and XNOR?
F = AB + AB
F = AB + AB
F = (A + B)(A + B)
F = AB + AB
F = AB + ( A + B )

How many transistors are needed here?

The best way to learn this is through practice.


Simply make up an expression of multiple variables and invert a couple of the literals
and/or subexpressions.
11

Advanced VLSI Design

Introduction

CMPE 640

Useful Transformations
(2) Translating from transistor-level schematics to Boolean expressions is straightforward.
Simply write the n-tree expression using the rules for series and parallel transistors given
earlier. Invert the final expression.
(3) Translating from transistor-level schematic diagrams to layout is covered in the laboratories.
(4) Translating from layout to transistor-level schematic diagrams is also covered in the
laboratories.
In general, start by identifying the transistor sources connected to VDD or GND
nodes.
Add series transistors in the schematic for transistors whose sources are connected to
drains of the previously identified transistors.
Add parallel transistors at fan-out points.
Label the transistors so it possible to connect the gates properly by tracing the poly
connections.
12

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