Prepared by: Dr.R.

Umamaheswari, EEE/ REC 1

UNIT V : VHDL
VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.
In the mid-1980s the U.S. Department of Defense in need todevelopa common platformto describe different digital systemsfrom
different VLSI suppliers/vendors and later in 1987 VHDL is standardized by IEEE. It has become now one of industrys standard
languages used to describe, simulate, test complex digital systemdesigns.
Purpose of Hardware Description Language:
For describing hardware.
As a modeling language.
For simulation of hardware.
For early performance estimation of system architecture.
For synthesis of hardware.
For fault simulation, test and verification of designs.
The other widely used hardware description language is Verilog. Primarily targeted for design of ASICs (Application Specific
Integrated Circuits). A third HDL language is ABEL (Advanced Boolean Equation Language) which was specifically designed for
Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in industry. This unit deals
with VHDL, as described by the IEEE standard 1076-1993.
A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed) in
parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical digital system. It also allows incorporation
of timing specifications (gate delays) as well as to describe a system as an interconnection of different component.
VHDL is the integration of
Sequential language
Concurrent language
Net-list language
Timing specification language
Waveform generation/simulation language
Mechanisms to reduce complexity (improve flexibility) are
Language abstraction
Design hierarchy
Abstraction levels
A digital system can be represented at different levels of abstraction. This keeps the description and design of complex systems
manageable. Figure shows different levels of abstraction. VHDL is rich in language abstractions, in addition to which the language
can be used to describe different abstraction levels, from functions right down to a gate description. Abstraction levels are a means
of concealing details
Hierarchical design
Onecan define components of units that are used over and over again. Once these components are defined they can be used as
blocks, cells or macros in a higher level entity. This can significantly reduce the complexity of large designs. While designing complex
systems Hierarchical design approaches are always preferred over flat designs.
VHDL analysis:
Reads one or more design units contained in a single file and compiles them into a design library after validating the syntax and
performs static semantic checks. Model - - - analysis- - - >simulation
VHDL design
description file
VHDL
analyser
Intermediate
format
WORK LIB
STD IEEE
Design library
Syntax check
Static semantic check
Complied descriptions
Prepared by: Dr.R.Umamaheswari, EEE/ REC 2
VHDL Synthesis(design)strategies :
Top to bottomdesign approach meansIncreasing Complexity. Synthesis can be done in each
level. The volume of information increases between the various abstraction levelseg.
Technologyinformation is required to synthesize from Register Transfer Level (RTL) to gate
level. Each transition (synthesis) generates more information. In order to implement a
function in an IC, the followings are required: technology information- wiring information-
gate information- set-up times.
The highest level of abstraction is the behavioral level that describes a system in terms of
what it does (or how it behaves) rather than in terms of its components and interconnection
between them. A behavioral description specifies the relationship between the input and
output signals. This could be a Boolean expression or a more abstract description such as the
Algorithmic or Register Transfer level.
As an example, let us consider a simple circuit that warns car passengers when the door is open or the seatbelt is not used whenever
the car key is inserted in the ignition lock. At the behavioral level this could be expressed as,
Warning =Ignition_on AND ( Door_open OR Seatbelt_off)
On the other hand, the structural level describes a system as a collection of gates and components
that are interconnected to perform a desired function. A structural description could be compared to
a schematic of interconnected logic gates. It is a representation that is usually closer to the physical
realization of a system. For the example above, the structural representation is given in fig.
VHDL allows one to describe a digital system at the structural or the behavioral level or both combined. The behavioral level can be
further divided into two kinds of styles: Data flow and Algorithmic. The dataflow representation describes how data moves through
the system. This is typically done in terms of data flow between registers (Register Transfer level). The data flow model makes use of
concurrent statements that are executed in parallel as soon as data arrives at the input. On the other hand, sequential statements
are executed in the sequence that they are specified. VHDL allows both concurrent
and sequential signal assignments that will determine the manner in which they
are executed.
RTLstands for Register-Transfer Level. It is an essential part of top-downdigital
design process. Logic synthesisoffers an automated route from an RTL design to
aGate-Level design. In RTL design a circuit is described as a set of registers and a
set of transfer functions describing the flow of data between the registers, (ie. FSM
+Datapath). As an important part of a complex design, this division is the main
objective of the hardware designer using synthesis. There areExamplesillustrates
that the RTL synthesis is more efficient than the behavior synthesis, although the
simulation of previous one requires a few clock cycles.
Register level /Dataflow- Most are like assigning expressions to signals
concurrent (if-then-else, Add, Subtract )
Behavioral -Write an algorithm that describes the circuits output- sequential
(functions and processes)
Structural - Define explicit components and the connections betweenthem.
(components, Gates and wires)
Register Transfer Level, or RTL design lies between a purely behavioral description of the desired circuit and a purely structural one.
An RTL description describes a circuits registers and the sequence of transfers between these registers but does not describe the
hardware used to carry out these operations.
The steps in RTL design are:
(1) determine the number and sizes of registers needed to hold the data used by the device,
(2) determine the logic and arithmetic operations that need to be performed on these register contents, and
(3) design a state machine whose outputs control how the register contents are updated in order to obtain the desired results.
Producing an RTL design is similar to writing a computer program in a conventional programming language. Choosing registers is the
same as choosing variables. Designing the flow of data in the datapath is analogous to writing expressions involving the variables
(registers) and operators (combinational functions). Designing the controller state machine is similar to deciding on the flow of
control within the program (if/then/else, while-loops, etc).
Prepared by: Dr.R.Umamaheswari, EEE/ REC 3
Circuits that divide up a computation into a sequence of arithmetic and logic operations are quite common and this type of design is
called Register Transfer Level (RTL) or dataflow design.
An RTL design is composed of
(1) registers and combinational function blocks (e.g. adders and multiplexers) called the datapath and
(2) a finite state machine, called the controller that controls the transfer of data through the function blocks and between the
registers.
In VHDL RTL design the gate-level design and optimization of the datapath (registers, multiplexers, and combinational functions) is
done by the synthesizer. However, the designer must design the state machine and decide which register transfers are performed in
which state.
RTL design is well suited for the design of CPUs and special-purpose processors such as disk drive controllers, video display cards,
network adapter cards, etc. It gives the designer great flexibility in choosing between processing speed and circuit complexity.
Basic Structure of a VHDL file
Basic designs constructs of VHDL model are an interface (entity declaration) and a body
(architectural description). An entity-architecture pair is a design entity.
A digital system described in VHDL consists of a design entity that can contain other entities
that are then considered components of the top-level entity. Each entity is modeled by an
entity declaration and an architecture body. One can consider the entity declaration as the
interface to the outside world that defines the input and output signals, while the
architecture body contains the description of the entity and is composed of interconnected
entities, processes and components, all operating concurrently, as schematically shown in
fig. In a typical design there will be many such entities connected together to perform the
desired function.
An VHDL model consist of 5 basic design units.
Entity declaration, Architecture Body, Configuration declaration, Package declaration,
Package bodydeclaration
1. Entity Declaration
entityNAME_OF_ENTITYis[ genericgeneric_declarations);]
port(signal_names: modetype;
signal_names: modetype;
:
signal_names: modetype);
end[NAME_OF_ENTITY] ;
The NAME_OF_ENTITY is a user-selected identifier
mode: in indicates that the signal is an input
out indicates that the signal is an output of the entity whose value can only be read by other entities that use it.
buffer indicates that the signal is an output of the entity whose value can be read inside the entitys architecture
inout the signal can be an input or an output.
type: bit can have the value 0 and 1
bit_vector is a vector of bit values (e.g. bit_vector (0 to 7)
std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9 values to indicate the value and strength of a
signal. Std_ulogic and std_logic are preferred over the bit or bit_vector types.
boolean can have the value TRUE and FALSE
integer can have a range of integer values
real can have a range of real values
character any printing character
time to indicate time
generic: generic declarations are optional and determine the local constants used for timing and sizing (e.g. bus widths) the
entity. A generic can have a default value.
The syntax for a generic follows,
generic( constant_name: type [:=value] ;
constant_name: type [:=value] ;
:
constant_name: type [:=value] );
Entity declaration
Architecture Body
Configuration declaration
Package declaration
Package body
Port
VHDL entity
Prepared by: Dr.R.Umamaheswari, EEE/ REC 4
2. Architecture body
architecturearchitecture_nameofNAME_OF_ENTITYis
--Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
Label : component-nameport map(port1=>signal1, port2=>signal2,port3=>signaln);
:
endarchitecture_name;
Notice that the order in which these statements are written has no bearing on the execution since these statements
areconcurrent andtherefore executed in parallel. Indeed, the schematic that is described by these statements is the same
independent of the order of the statements.
Delaymodels:1)Inertial delay 2)temporal delay
Example VHDL code half adder ( in all 3 different ways)
- - Hal f adder i n Dat a f l ow way
library i eee;
use i eee. st d_l ogi c_1164. all;
entity hal f Adder is
port( A, B : in st d_l ogi c;
sum, Cout : out st d_l ogi c) ;
end hal f Adder ;
architecture HA_DFLOWof hal f Adder is
begin
sum<= A xor B after 8ns;
Cout <= A and B after 4ns;
end HA_DFLOW;
configuration HA_conf i g of hal f Adder is
for HA_DFLOW
end for;
end HA_conf i g
- - Hal f adder i n Behavi or al way
library i eee;
use i eee. st d_l ogi c_1164. all;
entity hal f Adder is
por t ( A, B : in st d_l ogi c;
sum, Cout : out st d_l ogi c) ;
end hal f Adder ;
architecture HA_BEHAV of hal f Adder is
begin
Process ( A, B)
Variable V1, V2: Bi t ;
begin
V1: =A xor B;
V2: =A and B;
sum<= V1;
Cout <= V2;
end process;
end HA_BEHAV;
- - Hal f adder i n st r uct ur al way
library i eee;
use i eee. st d_l ogi c_1164. all;
entity hal f Adder is
port( A, B : in st d_l ogi c;
sum, Cout : out st d_l ogi c) ;
end hal f Adder ;
architecture HA_STRC of hal f Adder is
component XOR2 is - XOR2 separ at e ent i t y model
port( X, Y : in st d_l ogi c;
Z : out st d_l ogi c) ;
end component;
component AND2 is - AND2 separ at e ent i t y model
port( L, M : in st d_l ogi c;
N : out st d_l ogi c) ;
end component;
begin
G1 : XOR2 port map( A, B, sum) ;
G2 : AND2 port map( A, B, Cout ) ;
end HA_STRC;
library CMOS_LI B, MY_LI B;
Configuration HA_BI ND of hal f Adder is
for HA_STRC
for G1 : XOR2
use entity CMOS_LI B. XOR_GATE( DATAFLOW) ;
end for;
for G2 : AND2
use entity CMOS_LI B. AND_GATE( DATAFLOW) ;
end for;
end for;
end HA_BI ND;

3. Configuration declaration: Used for Binding of components
Structural modeling of design lends itself to hierarchical design, in wh
ich one can define components of units that are used over and over again. Once these components are defined they can be used as
blocks, cells or macros in a higher level entity. This can significantly reduce the complexity of large designs.
Prepared by: Dr.R.Umamaheswari, EEE/ REC 5
Library
If we keep the description of a circuits interface (the entity) separate from its contents (the architecture), we need a way to linkor
bindthem together
entity =block diagram
architecture (for an entity) =a more detailed circuit schematic for the block diagram
configuration =a parts list of the circuit components with their part numbers and manufacturers
-- configuration_declaration
configuration identifier of entity_nameis
block_configuration
end [configuration]identifier;
4. Library and Packages: libraryandusekeywords
A library can be considered as a place where the compiler stores information about a design
project. A VHDL package is a file or module that contains declarations of commonly used
objects, data type, component declarations, signal, procedures and functions that can be shared
among different VHDL models.
e.g., std_logic is defined in the package ieee.std_logic_1164 in the ieee library. In order to use
the std_logic one needs to specify the library and package. This is done at the beginning of the
VHDL file using thelibraryand theusekeywords as follows:
library ieee;
use ieee.std_logic_1164.all; -- The .all extension indicates to use all of the ieee.std_logic_1164 package.
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_signed.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_misc.all;
5. Package body declaration
One can add other libraries and packages. The syntax to declare a package is as follows:
-- Package declaration
packagename_of_packageis
package declarations
end packagename_of_package;
-- Package body declarations
package bodyname_of_packageis
package body declarations
end package bodyname_of_package;
For instance, the basic functions of the AND2, OR2, NAND2, NOR2, XOR2, etc. components need to be defined before one can use
them. This can be done in a package, e.g. basic_func for each of these components.
library i eee; - - Package decl ar at i on
use i eee. st d_l ogi c_1164. al l ;
package basi c_f unc is
component AND2 -- AND2 decl ar at i on
generic ( DELAY: t i me : =5ns) ;
port ( i n1, i n2: in st d_l ogi c; out 1: out st d_l ogi c) ;
end component;
component OR2 -- OR2 decl ar at i on
generic ( DELAY: t i me : =5ns) ;
port ( i n1, i n2: in st d_l ogi c; out 1: out st d_l ogi c) ;
end component;
end package basi c_f unc;
package body basi c_f unc is - - Package body decl ar at i ons
entity AND2 is - - 2 i nput AND gat e
Package Package
component
component
component
component
Prepared by: Dr.R.Umamaheswari, EEE/ REC 6
generic ( DELAY: t i me) ;
port ( i n1, i n2: in st d_l ogi c; out 1: out st d_l ogi c) ;
end AND2;
architecture model _conc of AND2 is
begin
out 1 <= i n1 and i n2 after DELAY;
end model _conc;
entity OR2 is - - 2 i nput OR gat e
generic ( DELAY: t i me) ;
port ( i n1, i n2: in st d_l ogi c; out 1: out st d_l ogi c) ;
end OR2;
architecture model _conc2 of AND2 is
begin
out 1 <= i n1 or i n2 after DELAY;
end model _conc2;
end package body basi c_f unc;
Basic language Elementsof VHDL
Identifiers : _,AZ,az,09
Keywords(Reserved words): in, out, or, and, port, map, end
Datatypes
1. Scalar type (enumeration, integer, physical, floating point)
2. Composite type(Characters, Strings and Bit Strings)
3. Access type
4. File type
Data Objects(constants, variables, signal, file)
A data object is created by anobject declarationand has avalueandtypeassociated with it. An object can be a Constant,
Variable, Signal or a File. Up to now we have seen signals that were used as input or output ports or internal nets. Signals can be
considered wires in a schematic that can have a current value and future values, and that are a function of the signal assignment
statements. On the other hand, Variables and Constants are used to model the behavior of a circuit and are used in processes,
procedures and functions, similarly as they would be in a programming language. Following is a brief discussion of each classof
objects.
Variable assignment eg. V1 :=A and B;
Signal assignment eg. Z <=A and B after 4 ns;
9 values for signal in IEEE std_logic:
0 -- Forcing 0
1 -- Forcing 1
X -- Forcing Unknown
- -- Dont Care
Z -- High Impedance
U Uninitialized
W Weak
L -- Weak 0
H -- Weak 1
Operators: VHDL supports different classes of operators that operate on signals, variables and constants. The different classes of
operators are summarized below.
Class
1. Logical operators and or nand nor xor xnor
2. Relational operators = /= < <= > >=
3. Shift operators sll srl sla sra rol ror
4.Addition operators + = &
5. Unary operators + -
6. Multiplying op. * / mod rem
7. Miscellaneous op. ** abs not
Statements
Behavioral Modeling:
Process(sequential statements)
Concurrent statement
If , if else Statements
Case statements
Loop statements
Next, Exit Statement
Wait statement (postponethe execution of a process)
Null statement (does not cause any action)
Structural Modeling
Component declaration
Prepared by: Dr.R.Umamaheswari, EEE/ REC 7
Component Instantiation and interconnections
(port map)
Test bench
A model (written in VHDL) that is used to exercise and verify the
correctness of the hardware model.
3 purposesof test bench
(1) To generate stimulus for simulation/waveform.
(2) To apply this stimulus to the entity under test and collect
the output responses.
(3) To compare output responses with expected values.
example for n bit adder with test bench
- - model desi gn
l i br ar y i eee;
use i eee. st d_l ogi c_1164. al l ;
use i eee. st d_l ogi c_ar i t h. al l ;
use i eee. st d_l ogi c_unsi gned. al l ;
ent i t y ADDER i s
gener i c( n: nat ur al : =2) ;
por t ( A: i n st d_l ogi c_vect or ( n- 1 downt o 0) ;
B: i n st d_l ogi c_vect or ( n- 1 downt o 0) ;
car r y: out st d_l ogi c;
sum: out st d_l ogi c_vect or ( n- 1 downt o 0) ) ;
end ADDER;
ar chi t ect ur e behv of ADDER i s
si gnal r esul t : st d_l ogi c_vect or ( n downt o 0) ; - - t empar ar y si gnal t o st or e t he r esul t
begi n
- - t he 3r d bi t shoul d be car r y
r esul t <= ( ' 0' & A) +( ' 0' & B) ;
sum<= r esul t ( n- 1 downt o 0) ;
car r y <= r esul t ( n) ;
end behv;
-- test bench
l i br ar y i eee;
use i eee. st d_l ogi c_1164. al l ;
use i eee. numer i c_st d. al l ;
ent i t y t est _add i s
gener i c ( wi dt h : i nt eger : = 17 ) ;
por t ( cl k : i n st d_ul ogi c;
r eset : i n st d_ul ogi c;
enabl e : i n st d_ul ogi c;
i np1, i np2 : i n st d_l ogi c_vect or ( wi dt h downt o 0) ;
sum : out st d_l ogi c_vect or ( ( wi dt h + 1) downt o 0) ) ;
end t est _add;
- - RTL descr i pt i on. Adds t wo i nput s t oget her ( unsi gned) i nt o an i nt eger
- - of " wi dt h + 1" i n l engt h.
ar chi t ect ur e r t l of t est _add i s
const ant t er mi nal _count : i nt eger : = 2**( sum' hi gh + 1 ) - 1;
subt ype adder _r ange i s i nt eger r ange 0 t o t er mi nal _count ;
si gnal sumx, i np1x, i np2x : adder _r ange;
begi n - - r t l
sum <= st d_l ogi c_vect or ( t o_unsi gned ( sumx, wi dt h + 2 ) ) ;
i np1x <= t o_i nt eger ( unsi gned ( i np1 ) ) ;
Match
Need
correction
Need
correction
good good
simulation simulation
VHDL
Entity
Synthesis
Tool
Net list
RTL
design
TEST BENCH
CODE
Gate level
design
Fabricate
IC
Results compare Results
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Prepared by: Dr.R.Umamaheswari, EEE/ REC 8
i np2x <= t o_i nt eger ( unsi gned ( i np2 ) ) ;
ADDER : pr ocess ( cl k, r eset )
begi n
i f r eset = ' 0' t hen sumx <= 0;
el si f r i si ng_edge ( cl k) t hen
i f enabl e = ' 1' t hen sumx <= i np1x + i np2x;
end i f ;
end i f ;
end pr ocess adder ;
end r t l ;
VHDL sample design file
1. Gates operations
-- AND gate
l i br ar y i eee;
use i eee. st d_l ogi c_1164. al l ;
ent i t y andGat e i s
por t ( A, B : i n st d_l ogi c;
F : out st d_l ogi c) ;
end andGat e;
ar chi t ect ur e f unc of andGat e i s
begi n
F <= A and B;
end f unc;
-- OR gate
l i br ar y i eee;
use i eee. st d_l ogi c_1164. al l ;
ent i t y or Gat e i s
por t ( A, B : i n st d_l ogi c;
F : out st d_l ogi c) ;
end or Gat e;
ar chi t ect ur e f unc of or Gat e i s
begi n
F <= A or B;
end f unc;
-- xor gate y x y x y x
entity XOR2 is
port ( A, B: in st d_l ogi c;
Z: out st d_l ogi c) ;
end XOR2;
architecture behavi or al _xor of XOR2 is
-- si gnal decl ar at i on ( of i nt er nal si gnal s X, Y)
signal X, Y: st d_l ogi c;
begin
X <= A and B;
Y <= ( not A) and ( not B) ;
Z <= X or Y;
End behavi or al _xor ;
-- VHDL code for AND-OR-INVERT gate
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
ent i t y AOI i s
por t ( A, B, C, D: i n STD_LOGI C;
F : out STD_LOGI C) ;
end AOI ;
ar chi t ect ur e V1 of AOI i s
begi n
F <= not ( ( A and B) or ( C and D) ) ;
end V1;
- - end of VHDL code
2. Full adder
St r uct ur al Behavi or
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Prepared by: Dr.R.Umamaheswari, EEE/ REC 9
l i br ar y i eee;
use i eee. st d_l ogi c_1164. al l ;
ent i t y f ul l Adder i s
por t ( A, B, Ci n : i n st d_l ogi c;
sum, Cout : out st d_l ogi c) ;
end f ul l Adder ;
ar chi t ect ur e FAf r omHA of f ul l Adder i s
component hal f Adder i s - - i mpor t Hal f Adder ent i t y
por t ( A, B : i n st d_l ogi c;
sum, Cout : out st d_l ogi c) ;
end component ;
component or Gat e i s - - i mpor t OR Gat e ent i t y
por t ( A, B : i n st d_l ogi c;
F : out st d_l ogi c) ;
end component ;
si gnal hal f Tohal f , hal f ToOr 1, hal f ToOr 2: st d_l ogi c;
begi n
G1: hal f Adder por t map( A, B, hal f Tohal f , hal f ToOr 1) ;
G2: hal f Adder por t map( hal f Tohal f , Ci n, sum, hal f ToOr 2) ;
G3: or Gat e por t map( hal f ToOr 1, hal f ToOr 2, Cout ) ;
end f ul l Adder ;
- - f ul l adder i n Behavi or al way
l i br ar y i eee;
use i eee. st d_l ogi c_1164. al l ;
ENTI TY f ul l _adder I S - - - Ful l Adder
PORT( a, b, c: I N BI T ;
sum, car r y : OUT BI T) ;
END f ul l _adder ;
ARCHI TECTURE f ul l _adder _beh OF f ul l _adder I S
BEGI N
PROCESS( a, b, c) - - Sensi t i vi t y l i st
VARI ABLE t emp : BI T;
BEGI N
t emp : = a XOR b;
sum<= t emp XOR c;
car r y <= ( a AND b) OR ( t emp AND c) ;
END PROCESS ;
END f ul l _adder _beh;
3. Four Bit Adder
Four Bit Adder Illustrating a hierarchical VHDL model
- - Exampl e of a f our bi t adder
library i eee;
use i eee. st d_l ogi c_1164. all;
- - def i ni t i on of a f ul l adder
entity FULLADDER is
port ( a, b, c: in st d_l ogi c;
sum, car r y: out st d_l ogi c) ;
end FULLADDER;
architecture f ul l adder _behav of FULLADDER is
begin
sum<= ( a xor b) xor c ;
car r y <= ( a and b) or ( c and ( a xor b) ) ;
end f ul l adder _behav;
- - 4- bi t adder
library i eee;
use i eee. st d_l ogi c_1164. all;
entity FOURBI TADD is
port ( a, b: in st d_l ogi c_vect or ( 3 downto 0) ;
Ci n : in st d_l ogi c;
sum: out st d_l ogi c_vect or ( 3 downto 0) ;
Cout , V: out st d_l ogi c) ;
end FOURBI TADD;
architecture f our adder _st r uct ur e of FOURBI TADD is
signal c: st d_l ogi c_vect or ( 4 downto 0) ;
component FULLADDER
port( a, b, c: in st d_l ogi c;
sum, car r y: out st d_l ogi c) ;
end component ;
begin
FA0: FULLADDER
port map ( a( 0) , b( 0) , Ci n, sum( 0) , c( 1) ) ;
FA1: FULLADDER
port map ( a( 1) , b( 1) , C( 1) , sum( 1) , c( 2) ) ;
FA2: FULLADDER
port map ( a( 2) , b( 2) , C( 2) , sum( 2) , c( 3) ) ;
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Prepared by: Dr.R.Umamaheswari, EEE/ REC 10
FA3: FULLADDER
port map ( a( 3) , b( 3) , C( 3) , sum( 3) , c( 4) ) ;
V <= c( 3) xor c( 4) ;
Cout <= c( 4) ;
end f our adder _st r uct ur e;
5. 6.
7. flipflop
- - t he descr i pt i on of J K Fl i p- Fl op i s based on f unct i onal t r ut h t abl e
l i br ar y i eee;
use i eee. st d_l ogi c_1164. al l ;
ent i t y J K_FF i s
por t ( cl ock: i n st d_l ogi c;
J , K: i n st d_l ogi c;
r eset : i n st d_l ogi c;
Q, Qbar : out st d_l ogi c) ;
end J K_FF;
ar chi t ect ur e behv of J K_FF i s
si gnal st at e: st d_l ogi c; - - def i ne t he usef ul si gnal s her e
si gnal i nput : st d_l ogi c_vect or ( 1 downt o 0) ;
begi n

i nput <= J & K; - - combi ne i nput s i nt o vect or
p: pr ocess( cl ock, r eset ) i s
begi n
i f ( r eset =' 1' ) t hen
st at e <= ' 0' ;
el si f ( r i si ng_edge( cl ock) ) t hen - - compar e t o t he t r ut h t abl e
case ( i nput ) i s
when " 11" => st at e <= not st at e;
when " 10" => st at e <= ' 1' ;
when " 01" => st at e <= ' 0' ;
when ot her s => nul l ;
end case;
end i f ;
end pr ocess;
11
Prepared by: Dr.R.Umamaheswari, EEE/ REC 11
Q <= st at e; - - concur r ent st at ement s
Qbar <= not st at e;
end behv;
8. synchronous counter (up/ down count er wi t h async. r eset and synchr onous par al l el l oad. )
l i br ar y I EEE; - - t ypi cal packages decl ar at i on
use I EEE. st d_l ogi c_1164. al l ;
use I EEE. numer i c_st d. al l ;
ent i t y COUNT_8B i s - - ent i t y
por t ( RESET, CLK, LD, UP : i n st d_l ogi c;
DI N : i n st d_l ogi c_vect or ( 7 downt o 0) ;
COUNT : out st d_l ogi c_vect or ( 7 downt o 0) ) ;
end COUNT_8B;
ar chi t ect ur e my_count of COUNT_8B i s - - ar chi t ect ur e i n Behavi or al Model
si gnal t _cnt : unsi gned( 7 downt o 0) ; - - i nt er nal count er si gnal
begi n
pr ocess ( CLK, RESET)
begi n
i f ( RESET = ' 1' ) t hen
t _cnt <= ( ot her s => ' 0' ) ; - - cl ear
el si f ( r i si ng_edge( CLK) ) t hen
i f ( LD = ' 1' ) t hen t _cnt <= unsi gned( DI N) ; - - l oad
el se
i f ( UP = ' 1' ) t hen t _cnt <= t _cnt + 1; - - i ncr
el se t _cnt <= t _cnt - 1; - - decr
end i f ;
end i f ;
end i f ;
end pr ocess;
COUNT <= st d_l ogi c_vect or ( t _cnt ) ;
end my_count ;
VHDL is a design description language not a language that automatically design the
circuits for you! You must first design on paper using truth table /state table and block
diagrams with interconnections, before you can describe it in VHDL!
VHDL versus C Terminology
Analyze - compile
Elaborate - link
Component - function
Instantiate - call
use - #include
package - DLL
library - directory
12
Prepared by: Dr.R.Umamaheswari, EEE/ REC 12
VHDL for n bit counter with test bench. demonstration
Counter Design Block
Counter Design Specifications
4-bit synchronous up counter. active high, synchronous reset. Active high enable.
Counter Design
1 library ieee ;
2 use ieee.std_logi c_1164.all;
3 use ieee.std_logi c_unsigned.all;
4
5 entity counter is
6 port( clk: in std_logic;
7 reset: in std_logic;
8 enable: in std_logic;
9 count: out std_logic_vector(3 downto 0)
10 );
11 end counter;
12
13 architecture behav of counter is
14 signal pre_count: std_logic_vector(3 downto 0);
15 begin
16 process(clk, enable, reset)
17 begin
18 if reset = '1' then
19 pre_count <= " 0000" ;
20 elsif (clk='1' and clk'event) then
21 if enable = '1' then
22 pre_count <= pre_count + " 1" ;
23 end if;
24 end if;
25 end process;
26 count <= pre_count;
27 end behav;
You could download file counter.vhd here
Counter Test Bench
Any digital circuit, no matter how complex, needs to be tested. For the counter logic, we need to provide a
clock and reset logic. Once the counter is out of reset, we toggle the enable input to the counter, and check
the waveform to see if the counter is counting correctly. The same is done in VHDL
13
Prepared by: Dr.R.Umamaheswari, EEE/ REC 13
Counter testbench consists of clock generator, reset control, enable control and
monitor/checker logic. Below is the simple code of testbench without the monitor/checker
logic.
1 library ieee ;
2 use ieee.std_logi c_1164.all;
3 use ieee.std_logi c_unsigned.all;
4 use ieee.std_logi c_textio.all;
5 use std.textio.all;
6
7 entity counter_tb is
8 end;
9
10 architecture counter_tb of counter_tb is
11
12 component counter
13 port ( count : out std_logic_vector(3 downto 0);
14 clk : in std_logic;
15 enable: in std_logic;
16 reset : in std_logic);
17 end component ;
18
19 signal clk : std_logic := '0';
20 signal reset : std_logic := '0';
21 signal enable : std_logic := '0';
22 signal count : std_logic_vector(3 downto 0);
23
24 begin
25
26 dut : counter
27 port map (
28 count => count,
29 clk => clk,
30 enable=> enable,
31 reset => reset );
32
33 clock : process
34 begin
35 wait for 1 ns; clk <= not clk;
36 end process clock;
37
14
Prepared by: Dr.R.Umamaheswari, EEE/ REC 14
38 stimulus : process
39 begin
40 wait for 5 ns; reset <= '1';
41 wait for 4 ns; reset <= '0';
42 wait for 4 ns; enable <= '1';
43 wait;
44 end process stimulus;
45
46 monitor : process (clk)
47 variable c_str : line;
48 begin
49 if (clk = '1' and clk'event) then
50 write(c_str,count);
51 assert false report time'image(now) &
52 " : Current Count Value : " & c_str.all
53 severity note;
54 deallocate(c_str);
55 end if;
56 end process monitor;
57
58 end counter_tb;
You could download file counter_tb.vhd here
time clk reset enable counter
0 1 0 0 xxxx
5 0 1 0 xxxx
10 1 1 0 xxxx
11 1 1 0 0000
15 0 0 0 0000
20 1 0 0 0000
25 0 0 1 0000
30 1 0 1 0000
31 1 0 1 0001
35 0 0 1 0001
40 1 0 1 0001
41 1 0 1 0010
45 0 0 1 0010
50 1 0 1 0010
51 1 0 1 0011
55 0 0 1 0011
60 1 0 1 0011
61 1 0 1 0100
65 0 0 1 0100
70 1 0 1 0100
71 1 0 1 0101
75 0 0 1 0101
80 1 0 1 0101
81 1 0 1 0110
85 0 0 1 0110
90 1 0 1 0110
91 1 0 1 0111
95 0 0 1 0111
100 1 0 1 0111
101 1 0 1 1000
105 0 0 1 1000
110 1 0 1 1000
111 1 0 1 1001
15
Prepared by: Dr.R.Umamaheswari, EEE/ REC 15
115 0 0 1 1001
120 1 0 1 1001
121 1 0 1 1010
125 0 0 0 1010
Counter Waveform