Transistor Gating: Reduction of Leakage Current

and Power in Full Subtractor Circuit

Milind Gautam
!e"t# $lectronics % Comm& 'TM uni(ersity Gwalior& 'ndia Milind#gautam*+,-gmail#com

Shyam kashe

!e"t# $lectronics % Comm# 'TM )ni(ersity Gwalior& 'ndia Shyam#akashe-itmuni(ersity#ac#i n much larger number of associated with the out"ut wiring# small "ro"ortion transistors on chi"# of dynamic "ower arises Abstract In this paper low-power designMaintaining high transistor from the short0circuit techniques proposed to minimize the standby leakage switching s"eeds& howe(er& current that flows power in nanoscale CMOS very large scale integration re7uires a commensurate momentarily while the ( !SI" systems by generating transistor grating down0scaling of the com"lementary de(ices technology# In low-power design $or circuit to reduce the transistor threshold (oltage 2"ushA"ull3 in a circuit are power supply voltage and this requires the transistor gi(ing rise to a significant simultaneously threshold voltages to also be reduced to maintain conducting during a throughput and noise margins#% this increases the amount of leakage "ower change in the out"ut subthreshold leakage current in p and n MOS&'(s# this dissi"ation e(en when the state# The dynamic "ower begins to increase the overall power in digital circuits# transistor is not switching# consum"tion 2Pdyn3 is )ow-ever% this increases the subthreshold leakage =ut as technologies gi(en by current o$ p and n MOS&'(s% which starts to set the
power savings obtained $rom power supply reduction# In nanometer regime 2)ltra transistor grating technology two sleep transistors !ee" Sub0Micron 2)!SM33& *MOS and +MOS are inserted in between the supply the dynamic "ower voltage and ground# , *MOS is inserted in between pulldissi"ation becomes more up network and network output and a +MOS is inserted lagging than the static in between pull-down network and ground# -uring nd standby mode both sleep transistor are turned o$$# .y"ower consum"tion# the aggressi(e applying this technique reduction in leakage current is des"ite of de(ice /0#123 and power is 45#623 #(he tool used is C,-'+C' downscaling I7(8OSO $or schematic simulation# (he simulation dimensions and decreasing the su""ly (oltages& which technology used is 51nm#

scales

down

to

the

Pdyn ?Bc(:ddfsw >here k ? technology factor& C ? ca"acitance of switching nodes& ;dd ? su""ly (oltage and fsw is the effecti(e switching fre7uency# >hile which leads to short0circuit "ower dissi"ation 2Psc3 and gi(en by

2:3

Keywords- CMOS; leakage current; low power; consum"tion of the single transistor grating; Full subtractor; transistor& with e1"onential

decrease

the

"ower

increase of o"erating fre7uencies results in a 9. '.TR/!)CT'/. steady increase of the 'n recent years& "ower consum"tion has become a o(erall "ower consum"tion# critical design concern for many combinational circuit >ith downscaling systems# the ad(antages of com"lementary metal0o1idetechnology& interconnect semiconductor2CM/S3 o(er com"eting technologies&resistance and ca"acitance such as transistor 0 transistor logic 2TTL3 and emitter increase the "ro"agation cou"led logic 2$CL3& has been its lower "ower dissi"ation delay#
456# to the growing need for low0(oltage &high0 The two main effects that "erformance& low0leakage systems& a (ariety of leakage0 contribute to the total "ower control techni7ues ha(e been de(elo"ed# Some de"end dissi"ation on a chi" are the on the use of multi"le0threshold (oltages# Low0threshold transistors are used to im"ro(e "erformance# 8igh0 acti(e and static "ower threshold de(ices are then used for leakage control# dissi"ation# The e1"ression Multi"le threshold CM/S 2MTCM/S3 496& 4:6 isolates low0 to com"ute the total "ower is threshold circuits from "ower and ground rails using high0 as follows threshold de(ices# Lowering the su""ly (oltage is the most effecti(e way to achie(e low0"ower "erformance T ?P @P @ because "ower dissi"ation in digital CM/S circuits is total dynamic sc a""ro1imately "ro"ortional to the s7uare of the su""ly (oltage# From the "oint of (iew of a""lications to battery0 Pstatic "owered mobile e7ui"ment& the su""ly (oltage should be 2 set at 9 ; 4<6# chi" designers ha(e relied on scaling down 9 the transistor su""ly (oltage in subse7uent generations 3 to reduce the dynamic "ower dissi"ation due to a

!ynamic dissi"ation "ower occurs when a transistor switches state and is due to ca"aciti(e charging and discharging

P ? ' #; # t f
sc sc dd

s sw

2C3

3/12/$31.00 c 2012 IEEE 1514 978-1-4673-4529-

Where Isc = short circuit current, ts = switching delay. In Nano CMOS circuits, Sub-threshold and Gate Lea age currents are !ro"en as the do#inant $actors in deciding the Static %ower and contribute signi$icantly to o"erall !ower consu#!tion. Sub threshold or wea in"ersion conduction current between source and drain in a MOS transistor occurs when gate "oltage is below the transistor threshold "oltage. &he Sub threshold or wea in"ersion current I ds can be e'!ressed as( Ids=Idso ;gs )t n"& *+ - 0)d s )T,
Idso = 0eff co1 -WL/)T :
-./

(5)

Where 0eff is the charge carrier #obility, C o1 is the gate ca!acitance 1unit area, W1L are width to length o$ channel ratio res!ecti"ely, )t is the threshold "oltage, )T is the ther#al "oltage, n is the sub-threshold swing coe$$icient, )gs is the transistor gate to source "oltage and )ds is the drain to source "oltage. &ransistor gating !ro!osed techni2ue has been de$ined, in this techni2ue we used two slee! transistors NMOS and %MOS are inserted in the circuit. &he %MOS slee! transistor -S/ is added in between the !ull-u! networ and network outputs and NMOS sleep transistor (S) is added in between the !ull-down networ and ground. &his techni2ue a!!lied on $ull subtractor circuit.

%ower gating techni2ue

34)I4WS O5 %34)IO6S WO37 &his section re"iews di$$erent a!!roaches $or sub-threshold lea age current reduction techni2ues. 8 techni2ue $or lea age !ower control is %ower gating *9,*:,, which turns o$$ the de"ices by cutting o$$ their su!!ly "oltage. %ower gating uses low-lea age %MOS transistors as header switches to turn o$$ !ower su!!lies to !arts o$ a design in standby or slee! #ode. NMOS as $ooter switches can also be used as slee! transistors. Inserting the slee! transistors di"ides the chi!;s !ower networ into !ull u! networ connected to the !ower su!!ly and a !ull down networ that dri"es the cells and can be turned o$$. 8n e'ternally switched !ower su!!ly is a "ery basic $or# o$ !ower gating to achie"e long ter# lea age !ower reduction. &o turn o$$ the bloc $or s#all inter"als o$ ti#e, internal !ower gating is #ore a!!ro!riate. CMOS switches which !ro"ide !ower to the circuit are controlled by !ower gating controllers.
&he #ulti threshold CMOS technology has two #ain $eatures. 5irst, a ti!e" and sleep" operational #odes are asso iated with M&CMOS technology, $or well-organi<ed !ower #anage#ent. Second, two dissi#ilar threshold "oltages are used $or N channel and % channel MOS54& in a single chi! *+=,. &his techni2ue based on disconnecting the low threshold "oltage -low-)t/ logic gates $ro# the !ower su!!ly and the ground line "ia cut-o$$ high threshold "oltage -high-)t/.

35.

M&CMOS techni2ue III. IM%L4M4N&8&ION O5 56LL S6>&38C&O3 8 $ull subtractor is a co#binational circuit that !er$or#s a subtraction between two bits ta ing into account that a + #ay ha"e been borrowed by a lower signi$icant stage. &his circuit has three in!uts and two out!uts such as 8, > and C denotes the in!uts, di$$erence and borrow are out!uts res!ecti"ely.

Figure 9# symbol of full subtractor

The two out"uts re"resent the difference and borrow& res"ecti(ely# The symbolic circuit for full subtractor is shown in Figure# The truth table for full subtractor is shown below#
T , D D D D 9 9 9 9
=L$90TR)T8 T =L$

9/F F)LL S)=TR

CT/R

. D D 9 9 D D 9 9

C D 9 D 9 D 9 D 9

-I&&'7'+C' D 9 9 D 9 D D 9

.O77O9 D 9 9 D D D D 9

The sim"lified logic e7uations from truth table are

Figure C# Transistor gating techni7ue

>here & =& C are the in"uts# /ut"uts are denoted by difference E and borrow as shown in wa(eform of full subtractor#

'n acti(e mode& both slee" transistors are turned on by a""lying the gate in"ut (oltage i#e# high 2D#*(3 for .M/S and low 2D(3 for PM/S& to reduced the resistance of the conducting "aths from "ower su""ly to ground& thereby reducing "erformance# =oth slee" transistors are turned off during standby mode by a""lying the gate in"ut (oltage i#e# low 2D(3 for .M/S and high 2D#*(3 for PM/S which reduces leakage current by increasing resistance of the "ath from "ower su""ly

#to ground#

Figure :# wa(eform of full subtractor

';# PR/P/S$! T$C8.'F)$ /. F)LL S)=TR CT/R

Figure <# wa(eform of "ro"osed full subtractor

and

'n this "a"er a new techni7ue of leakage reduction 0

$%&NS'S$O % (&$'N( $)*+N',-)" .as /een demonrasted# 'n this techni7ue leakage current is reduced by inserting e1tra slee" transistors between "ower su""ly

ground# PM/S

slee" transistor 2s3 is inserted in between "ull0 u" network and the network this out"ut and 'n "a"er we an .M/S analyGe slee" transistor (s) reduction of is inserted in leakage on Full /etween t.e the subtractor pull0down the networks and under t.e 0round as influence of s.own in transistor 1i0#3" gating techni7ue in nanometer CM/S technology#

;# 8ere the Full S'M subtractor is )L circuit T' simulated /. using R$ cadence S) simulation LT tools in <,nm

CM/S technology# 'n <,nm technology when su""ly (oltage is a""lied on full subtractor is D#*;& leakage current % leakage "ower is reduced by9*#,5H and :<#C5H#

1516 2013 3
rd

IEEE Computing Internati Conference onal (IACC) Advance

Figure ,# wa(eform of leakage current and "ower

CB./>L$!G$M$.T The author would like to thank 'TM )ni(ersity Gwalior for Cadence simulation tool for work has to be done# R$F$R$.C$

234 S# Shigematsu et al#, & 30; high0s"eed MTCM/S circuit scheme

for "ower0down appli ations," in Proc# '$$$ Sym"# ;LS' Circuits !ig#Tech# Pa"ers""# 9:,9:I&9++,#

254 S#

Mutoh et al#, 30; "ower su""ly high0s"eed digital circuit technologywith multithreshold0!olta0e *MOS," '$$$ J# Solid0State Circuits& (ol#CD& ""# 5<*5,C& ug# 9++,# 9# =rodersen& # Chandrakasan& and S# S.en0, 6esi0n techni7ues for porta/le s7ste#s," in ZSSCC Dig. Tech. Papers, Feb#9++C ""# 9I509I+& #
;dd: circuit techni7ue to reduce leakage in dee" submicron #e#ories," in Proc. IEEE ISLPED& ""# +D+,& :DDD&# a .e

234 R#
Figure I# >a(eform of "ro"osed leakage current and "ower

284 M# !# Powell& S#08# Eang& =# Falsafi& B. %o7, and $. N. 9i:a7ku#ar, Gated0

;' C/.CL)S'/. 'n this "a"er we "ro"osed a transistor gating techni7ue that reduces the "ower dissi"ation of the full subtractor# CM/S technology im"ro(es the "erformance and reduces "ower consum"tion# From the simulation result it is cleared that after a""lying this techni7ue we ha(e reduced9*#,5 H in leakage current and :<#C5 H in leakage "ower# Simulation of results for full subtractor is done by Cadence simulation tool in <,nm CM/S technology at D#* su""ly (oltage#

254 ;.*. <ark and 9. ;. Moone7 ''', Sleep7 sta k leaka0e redu tion,"
IEEETrans. VLSI Systems& (ol# 9<& no# 99& ""# 9:,D0 9:IC& .o(# :DDI #

2=4 M#

Johnson& !# Somasekhar& L#0>. *.iou, and ?. %o7, @eaka0e ontrol wit. eAAi ient use oA transistor sta ks in sin0le t.res.old *MOS," IEEE Trans. VLSI Systems#& (ol# 9D& no# 9& ""# 9,& Feb# :DD:# IEEE Trans. De ice !ater. "e#.&(ol# 5& no# :& ""# <DI<9,& Jun# :DD5# >iley Publishers& .ew Eork& :DDD#

2B4 ># %. $onti, MOS te .nolo07 dri!ers,"

2394

'$$$ Transactions on 'nstrumentation and Measurements& ;ol# ,+& .o# ,& May :D9D#

2C4 ..?. %o7 and S. *. <rasad, @ow0Power CM/S ;LS' Circuit !esign", 294
bdollahi& #& Fallah& F#& and Pedram& M# Leakage Current Reductionin CM/S ;LS' Circuits by 'n"ut ;ector Control# '$$$ Transactions on;ery Large Scale 'ntegration 2;LS'3 Systems 9:& : 2February :DD<3& 9<D# +. $.apli7al and N. %an0anat.an, 6esi0n oA eAAi ient re(ersible binary subtractors /ased on a new re!ersi/le 0ate," in Proc. the IEEEComp$ter Society %nn$a# Symposi$m on VLSI & Tam"a& Florida& ""# ::+:C<& & May:DD+# ;. +alter and 1. Na:#, & 0ate0le(el leakage "ower reduction method for ultra low power #os ir uits," in Proc. IEEE C$stom Integrated Circ$its Con&.& 9++*& ""# <*,<*5& 9++*# B#0># Cheng and C#0*. $sen0, ,uantu# Aull adder and su/tra tor,"E#ectronics Letters& (ol# C5& no# ::& ""# 9C<C 9C<<& /ct :DD:#
<.aniku#ar M and N. S.an#uk.a %ao, & @ow <ower and 8igh S"eed !esign for ;LS' Logic Circuits )sing Multi0Threshold ;oltage CM/S

23D4 2334

2354 2334

$e .nolo07", 'nternational ;ournal oA *o#puter S ien e and 'nformation Technologies 2'JCS'T3& ;ol# C2C3& :D9:& <9C90<9CC #

2384 2354 23=4 23B4 23C4

J# Bao& # Chandrakasan& and !# ntoniadis& Transistor siGing issues and tool for multi0 t.res.old *MOS te .nolo07," in Proc. '(th D%C& 9++*& ""# <D+<9<# +. $.apli7al, M.E Srini!as and +.% &ra/nia, %e!ersi/le @o0i S7nt.esis oA +alA, 1ull and <arallelSu/tra tors", <ro . oA t.e 5DD5 'ntl. Conf# on $mbedded Systems and ""lications& June :DD,& Las ;egas&""#9I,0959# E.S. 6eepaksu/ra#an7an and &drian NuFneG, &nal7sis oA Su/t.res.old
Leakage Reduction in CM/S !igital Circuits& Proceedings of the 9Cth .asa ;LS' Sym"osium& Post Falls& 'daho& )S & June ,0I& :DD* #

Baushik Roy& Saibal Mukho"adhyay and 8amid Mahmoodi0 Meimand& Leakage current mechanisms and Leakage current reduction techni7ues in !ee" Sub Micrometer CM/S Circuits& in Proceedings oh '$$$& ;ol0+9& .o0:& :DDC# 8eungJun Jeon&Eong0=in Bim and Minsu Choi& Standby Leakage Power Reduction Techni7ues for .anoscale CM/S ;LS' Systems&

2013 3 IEEE

rd

International Computing Conference Advance (IACC) 1517

&.Monpapassorn, Programmable wide range (oltageadderAsubtractor and its appli ation as an en oder," ')) <ro eedin0 oA *ir uits 6e!i es and Systems& (ol# 9,:& ""# I+**D:& :DD,#

25D4

&pproa . to a-niAied E*6 and Einar7 &dderHSu/tra tor", 53st 'nternationalConference on ;LS' !esign :DD5& "ages ,<*0,,:& Jan :DD5#

Sreehari ;eeramachaneni& M& Birthi BrishnaK ;& Prateek G& S# Subroto&S& =harat& M#=#Srini!as, & No!el *arr70Look head

1518 2013 3 IEEE International Advance Computing Conference (IACC)

rd