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Pin On Side of Chip

The document discusses simple input/output (I/O) using the MSP430 microcontroller. It explains that the MSP430 uses memory-mapped I/O, where writing to specific memory locations controls the logic state of pins (for outputs) and reading from locations returns the logic states of pins (for inputs). It describes how up to 8 ports are supported (P1 to P8) and each port is associated with memory locations for input (PIN), output (POUT) and direction (PDIR). The document provides an example of using Port 1 to monitor a push button and control a light emitting diode (LED) when the button is pressed.

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Alonso Corado
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0% found this document useful (0 votes)
30 views3 pages

Pin On Side of Chip

The document discusses simple input/output (I/O) using the MSP430 microcontroller. It explains that the MSP430 uses memory-mapped I/O, where writing to specific memory locations controls the logic state of pins (for outputs) and reading from locations returns the logic states of pins (for inputs). It describes how up to 8 ports are supported (P1 to P8) and each port is associated with memory locations for input (PIN), output (POUT) and direction (PDIR). The document provides an example of using Port 1 to monitor a push button and control a light emitting diode (LED) when the button is pressed.

Uploaded by

Alonso Corado
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Simple Input/Output using the MSP430 (note: these notes are written with the MSP430F149 in mind !

he MSP430 uses memor" mapped I/O# From a programmer$s perspe%ti&e' the e((e%t o( this is that writing to parti%ular memor" lo%ations %hanges the logi% state o( pins (outputs on the side o( the %hip# )eads (rom parti%ular memor" lo%ations return the logi% states o( parti%ular pins (inputs # *p to + ports are supported : P1 to P+ depending on the model o( the MSP430 ,eing used# -ll ports .map to/ 0 ,it memor" lo%ations# 1a%h port is asso%iated with (at least three memor" lo%ations: PnI2' PnO*! and Pn3I)(e%tion where $n$ represents the port num,er# 4onsider Port1 (or a moment# P1I2 is mapped to memor" address 50 (he6 P1O*! is mapped to memor" address 51 (he6 P13I) is mapped to memor" address 55 (he6 # !he 3ata dire%tion register determines whether a parti%ular ,it in a port is an input or an output# Figure 1 shows how ,it 1 o( port 1 ma" ,e %on(igured as an input or an output ," setting or %learing ,it 1 o( the 3ire%tion register# I( a 3I)e%tion register ,it is a .1/ then the %orresponding port data ,it is an output# I( a 3I)e%tion register ,it is a .0/ then the %orresponding port data ,it is an input#
3ata (low P1O*! Pin on side of chip

P1I2 3ata (low P13I) Inside MSP430

2ow lets sa" we want to use Port 1 to monitor the status o( a push ,utton and to %ontrol a 7ight 1mitting 3iode when the ,utton is pressed# !he %ir%uit %ould ,e represents as shown in Figure 5 ,elow:

)1 )5 P1 3#3;

,1 ,0

Figure 5 !o turn on the 713' ,it1 o( PO)!1 should ,e set to 0# !o turn o(( the 713' ,it1 o( PO)!1 should ,e set to 1# !he program %ontinuall" monitors P1I2 %he%8ing to see whether its least signi(i%ant ,it is a 0 or 1# !his ,it will ,e 9ero i( the ,utton is pressed' and i( so' the 713 is turned on# :e %ould program this in 4 as (ollows:

typedef unsigned char byte; #define P1IN *((byte *)0x20) #define P1OU *((byte *)0x21) #define P1!I" *((byte *)0x22) #define P#IN *((byte *) 0x1c ) #define P#OU *((byte *) 0x1d ) #define P#!I" *((byte *) 0x1e ) $$ %atchd&g ti'er definiti&ns (see (ater) #define %! )* *((sh&rt *)0x120) #define %! +O*! 0x00,0 #define %! P% 0x-a00 .&id 'ain(.&id) / %! ) * 0 %! P% 1 %! +O*!; $$ 2t&p 3atchd&g ti'er (see (ater) P1!I" 40 0x02; $$ 2et P251 is an &utput 3hi(e( 1001 ) / if( (P1IN 6 0x01) 70 0) / $$ 2%I )+ I2 OP8N 2O U"N O99 *8! P1OU 0 P1OU 4 2; : e(se / $$ 2%I )+ I2 OP8N 2O U"N ON *8! P1OU 0 P1OU 6 0xfd; : : :

Ports 1 to + (where a&aila,le are memor" mapped as (ollows (note the .06/ in (ront implies <1= : Port PnIN PnOUT PnDIR PnSEL P1 P5 P3 P4 P> P+ 0650 0650 0610 061% 0630 0634 0651 0659 0619 061d 0631 063> 0655 065a 061a 061e 0635 063+ 065+ 065e 061, 061( 0633 063?

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