Chapter 6: Sequential Logics

Introduction Most digital systems are made up of both combinational circuits and memory elements

A general digital system that combines combinational bi ti l logic l i gates t with ith memory devices d i

Chapter 6: Sequential Logics

The external outputs of a digital system are a function of both its external inputs and the i f information ti stored t di in its it memory elements l t The Th most important i memory element l is i the h flipfli flop (FF) A logic gate by itself has no storage capability in any real circuit, there will be a small time i t interval l between b t the th connection ti of f inputs i t and d the appearance of the outputs

Chapter 6: Sequential Logics

This interval is called propagation delay and has no effect on the final output(s) of the circuit Any logic circuit in which the order in time of applying inputs is important is termed a sequential circuit Sequential logics (or state logic) are digital circuits i it containing t i i a memory Registers, memories and microprocessors are typical examples of sequential logic

Chapter 6: Sequential Logics

Sequential S i l logic l i circuits i i (SLC) can be b classified l ifi d by b the way they are driven
Synchronously with a master clock and Asynchronously

A synchronous circuit or system is one in which all the changes take place simultaneously at a time determined by a signal at some control input common to all sections In an asynchronous system, there is no common control; a change in one section of the system causes further changes in others through the system in a manner, manner which is determined only by the speed with which each section operates

Chapter 6: Sequential Logics

SLCs are circuits with state, and can be further classified as:
Even-driven, where the circuit elements respond directly to changes in their inputs and no clock synchronizing signal is used Clock-driven, a master clock generator, or state generator, which controls the operation of all devices in the system Pulse-driven, circuits where input signals do not overlap and where a very fast response is possible

Chapter 6: Sequential Logics

In order to follow a sequence of inputs, the circuit must contain some form of memory to retain k knowledge l d of f those th inputs i t which hi h have h already l d occurred Most sequential systems are based on a number of simple sequential circuit elements known as bistables or flip flip-flops flops Circuits used for timing, sequencing and storage functions may be divided into three distinct categories:
Flip-flops/Latches Counters Shift registers

Chapter 6: Flip-flops (Bi-stables)

A flip-flop is the basic memory element used in sequential logic systems It is a bistable device which stores binary information o at o in t the e form o o of a 0 0 o or a 1, , It can be maintained indefinitely in either of the states t t It can also be switched from one state to the other Its It b basic i function f ti i is memory or storage t of fa single bit of binary data

Chapter 6: Flip-flops (Bi-stables)

It operates in one of two modes
A synchronous (or clocked) mode Asynchronous (or unclocked) mode

Synchronous means that that, the output changes state only at a specified point on a triggering input called the clock (designated as a control input, C) That is, the changes in the output occur in synchronism with the clock The flip-flop will change state only when a trigger pulse is applied to one of its input terminals

Chapter 6: Flip-flops (Bi-stables)

A flip-flop has two output terminals that are usually labeled as Q and When the circuit is in the state Q=1, it is said to b SET be Conversely, when Q=0, the circuit is said to be RESET

Chapter 6: Types of Flip-flops

There are four basic types of flip-flops flip flops
S-C or S-R flip-flop J-K J K flip-flop fli fl D flip-flop (Delay or Data latch) T flip-flop p p (Trigger ( gg or Toggle gg )

The SR and JK flip-flops can act as 1bit stores and may be interconnected to provide various other more complex functions such as counters cou te s a and d registers eg ste s The D flip-flop is used mainly to provide a time delay equal to the periodic time of the clock waveform

Chapter 6: Types of Flip-flops

The Tflip-flop acts as a toggle, that is, it changes state every time the clock waveform is at tl logical i l1

The various kinds of flip-flops can be constructed t t db by th the suitable it bl i interconnection t ti of f two or more NOR or NAND gates

Latches and Flip-flops

The Th operation i of f a latch l h is i sensitive i i to the h voltage level of it inputs only and not upon a transition of the clock waveform A flip-flop changes its output state only when there is a transition of the clock waveform The term flip flip-flop flop has come to mostly denote non-transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches However, However as this distinction is quite new, new the two words are sometimes used interchangeably

Latches and Flip-flops

A flip-flop fli fl changes h its i output state only l when h there is a transition of the clock waveform Three possibilities exist:
Master-Slave M t Sl or pulse-triggered l ti d which hi h responds d to t the th present state of the input(s) when the clock waveform changes from low to high and then back to low A leading-edge triggered, responds to the input(s) when the clock waveform changes from low to high A trailing trailing-edge edge triggered, responds to the input(s) when the clock waveform has made a transition from high to low

Most M t flip-flops fli fl are edge d triggered ti d devices d i

Latches and Flip-flops p p

Latches and Flip-flops

A flip-flop has two output terminals that are usually labeled as Q and The h output Q is called ll d the h normal l FF output The output is called inverted FF output

Whenever we refer to the state of a FF, we are referring to the state of its normal (Q) output Note that the HIGH or 1 state is also referred to as the SET state Whenever the inputs to a FF cause it to go to the (Q = 1/ =0) state, we call this setting the

FF

Latches and Flip-flops

In a similar way way, the LOW or 0 state is also referred to as the CLEAR or RESET state Whenever the inputs to a FF cause it to go to the (Q = 0/ =1) state, we call this clearing or resetting the FF A FF can have one or more inputs These inputs are used to cause the FF to switch b k and back d forth f th ("flip-flop") ("fli fl ") between b t its it possible ibl output states Most FF inputs need only to be momentarily activated (pulsed) in order to cause a change in the FF output p state The flip-flop is also known as bistable multivibrator

NAND Gate Latch

The most basic FF circuit can be constructed from either two NAND gates or two NOR gates The NAND gate version is called a NAND gate latch or simply a latch
SET TRUTH TABLE S Q S 1 0 1 0 R 1 1 0 0 Q no change g 1 Set 0 Reset Indeterminate

G1

CLEAR

G2

NAND Gate Latch

Its I operation i can be b conveniently i l placed l d in i a truth table and is summarized as follows
SET = CLEAR = 1. 1 This condition is the normal resting state, and it has no effect on the output state. The Q and outputs will remain in whatever state they were prior to this input condition. condition SET = 0, CLEAR = 1. This will always cause the output to go to the Q = 1 state, where it will remain even after SET returns HIGH. This is called setting the latch. SET = 1, CLEAR = 0. This will always produce the Q = 0 state, where the output will remain even after CLEAR returns HIGH. This is called clearing or resetting the latch. SET = CLEAR = 0. This condition tries to set and clear the latch at the same time and can produce ambiguous results. It should not be used

NOR gate latch

NOR gate latch

Two T cross-coupled l d NOR gates can be b used d as a NOR gate latch The arrangement is similar to the NAND latch except that the Q and outputs have reversed positions The analysis of the operation of the NOR latch can be performed in exactly the same manner as for the NAND latch The results can be placed in a truth table and are summarized as follows:

NOR gate latch

SET = CLEAR = 0. This is the normal resting state for the NOR latch, and it has no effect on the output state Q and will remain in whatever state they state. were prior to the occurrence of this input condition. SET = 1, CLEAR = 0. This will always set Q = 1, where it will remain even after SET returns to 0. SET = 0, CLEAR = 1. This will always clear Q = 0, where it will remain even after CLEAR returns to 0. SET = 1, CLEAR = 1. This condition tries to set and clear l the th latch l t h at t the th same time, ti and d it produces d Q = = 0. If the inputs are returned to 0 simultaneously, the resulting output state is unpredictable. This input condition should not be used

Truth-table of NOR gat Latch and SR flip flop

INPUTS S 0 R 0 OUTPUTS COMMENTS Qn 0 Qn+1 0 Qn =Qn+1 (storageor nochangein state) Qn1 =1 (SET) Qn1 =0 (RESET) Notdefined

1 1 0 0 1 1

0 0 1 1 1 1

0 1 0 1 0 1

1 1 0 0 X X

Truth-table of NOR gate Latch and SR flip flop

Qn is the state of the output Q prior to the application of the conditions listed in the input Qn+1 is the state of the output Q after the application of the input conditions At all times, the Q terminal is complementary to the terminal (i.e. if Q=1, then = 0 )

Clock Signals
Digital systems can operate either asynchronously or synchronously In asynchronous systems, the outputs of logic circuits can change state any time one or more of the inputs change In synchronous systems, the exact times at which hi h any output t t can change h state t t are determined by a signal commonly called the clock

Clock Signals
This clock signal is generally a rectangular pulse train or a square wave The clock signal is distributed to all parts of the system, and most (if not all) of the system outputs can change state only when the clock makes a transition When the clock signal changes from a 0 to a 1, this is called the Positive Positive-Going Going Transition (PGT) when the clock g goes from 1 to 0, this is the Negative-Going Transition (NGT)

Clock Signals

The synchronizing action of the clock signals is accomplished through the use of clocked flip-flops that are designed to change states on one or the other of the clock's transitions

Clocked Flip-flops

Clocked Flip-flops
Clocked FFs have a clock input that is typically labeled CLK, CK, or CP In I most t clocked l k d FFs FF the th CLK input i t is i edge-triggered, d ti d which means that it is activated by a signal transition This contrasts with the latches, which are leveltriggered Clocked FFs also have one or more control inputs that can have various names names, depending on their operation The Th control t l inputs i t will ill have h no effect ff t on Q until til the th active clock transition occurs

Clocked Flip-flops
In I other h words, d their h i effect ff is i synchronized h i d with ih the signal applied to CLK For F thi this reason th they are called ll d synchronous h control inputs In summary, summary we can say that the control inputs get the FF outputs ready to change While the active transition at the CLK input actually triggers the change The control inputs control the WHAT (i.e., (i e what state the output will go to) The CLK input determines the WHEN

Setup and Hold Times

Two T timing i i requirements i must be b met if a clocked FF is to respond reliably to its control inputs when the active CLK transition occurs The setup time, ts, is the time interval i immediately di l preceding di the h active i transition i i of f the CLK signal during which the control input must be maintained at the proper level IC manufacturers usually specify the minimum allowable ll bl setup time i ts(min) ( i )

If this time requirement q is not met, , the FF may y not respond reliably when the clock edge occurs

Setup and Hold Times

The hold time, time tH , is the time interval immediately following the active transition of the CLK signal during which the synchronous control input must be maintained at the proper level IC manufacturers usually specify the minimum acceptable value of hold time tH (min) If this requirement is not met, the FF will not trigger reliably to ensure that a clocked FF will respond properly when the active clock transition occurs

Setup and Hold Times

the control inputs must be stable (unchanging) for at least a time interval equal to ts(min) prior to the clock transition, , and for at least a time interval equal q to tH(min) after the clock transition IC flip flip-flops flops will have minimum allowable ts and tH values in the nanosecond range Setup times are usually in the range 5 to 50 ns whereas hold times are generally from 0 to 10 ns These timing requirements are very important in synchronous systems, because there will be many situations where the synchronous control inputs to a FF are changing at approximately the same time as the CLK input

Clocked S-C Flip-flop

Clocked S-C Flip-flop

the logic symbol for a clocked S S-C C flip-flop flip flop that is triggered by the positive-going edge of the clock signal is shown above This means that the FF can change states only when h a signal i l applied li d to t its it clock l k input i t makes k a transition from 0 to 1 The S and C inputs control the state of the FF in the same manner as described earlier for the NOR gate latch l h But the FF does not respond p to these inputs p until the occurrence of the PGT of the clock signal

Clocked S-C Flip-flop

The Th truth h table bl shows h how h the h FF output will ill respond to the PGT at the CLK input for the various combinations of S and C inputs The up arrow () indicates that a PGT is required at

CLK

The label Qo indicates the level at Q prior to the

PGT

This nomenclature is widely used by IC manufacturers on their IC data sheets The operation of the clocked S-C flip-flop can be illustrated by a waveform

Clocked S-C Flip-flop

If we assume that the setup and hold time requirements are being met in all cases, we can analyze these waveforms as follows: Initially I iti ll all ll inputs i t are 0 and d the th Q output t ti is assumed to be 0; that is, Qo = 0 When the PGT of the first clock pulse occurs (point a), the S and C inputs are both 0, so the FF is not affected and remains in the Q = 0 state (i.e., Q = Qo) When the third clock pulse makes its positive transition (point e), it finds that S = 0 and C = 1 which causes the FF to clear to the 0 state The fourth pulse sets the FF once again to the Q = 1 state (point g) because S = 1 and C = 0 when the positive edge occurs The fifth pulse also finds that S = 1 and C = 0 when it makes its positive-going transition. However, , Q is already y high, g , so it remains in that state The S = C = 1 condition should not be used, because it results in an ambiguous condition

Clocked S-C Flip-flop

The symbol and the truth table for a clocked S-C flip-flop th t t that triggers i on th the negative-going ti i t transition iti at t it its CLK input i t The small circle and triangle on the CLK input indicates that this FF will trigger only when the CLK input goes from 1 to 0

Clocked J-K Flip-Flop

not result in an ambiguous output

The J and K inputs control the state of the FF in the same ways as the S and C inputs do for the clocked S-C S C flip-flop flip flop except for one major difference: the J = K = 1 condition does For this condition, the FF will always go to its opposite state upon the positive transition of the clock signal This is called the toggle mode of operation

Clocked J-K Flip-Flop

The operation of this FF is illustrated by the waveforms shown below
Initially all inputs are 0, and the Q output is assumed to be 1; that is, Qo = 1. When the positive-going edge of the first clock pulse l occurs (point ( i a), ) the h J=0 0, K = 1 condition exists. Thus, the FF will be cleared to the Q = 0 state The second clock pulse finds J = K = 1 when it makes its positive transition (point c). This causes the FF to toggle to its opposite state, Q

=1

At point i, i J = K = 1, 1 and so the FF toggles to its opposite state. The same thing occurs at point k

At point e on the clock waveform, waveform J and K are both 0, so that the FF does not change states on this transition At point g, J = 1 and K = 0. This is the condition that sets Q to the 1 state. state However, However it is already 1, and so it will remain there

Clocked J-K Flip-Flop

shows the symbol for a clocked J-K flip-flop that triggers on the negative-going negative going clock clock-signal signal transitions This FF operates in the same manner as the positive-edge FF of figure 3.13 except that the output can change states only on negative-going clock-signal transitions (points b, d, f, h, and j)

Clocked J-K Flip-Flop

The J-K flip-flop is much more versatile than the S-C flip-flop because it has no ambiguous states The J = K = 1 condition, which produces the toggling operation, finds extensive use in all types of binary counters In essence, the J-K flip-flop can do anything the S C flip-flop S-C fli fl can do d plus l operate t i in the th t toggle l mode

The Master-Slave J-K flip-flop

When the clock is high, the inverted clock is low and isolates the slave from the master The master responds to the data present at its J and K inputs p and stores the resultant state At the end of the clock pulse, the inverted clock goes high g g and then the data stored by y the master is transferred to the slave and appears at the output terminals This means that, the output state of a masterslave J-K flip-flop changes at the trailing edge of the clock pulse

Clocked D Flip-flop

Unlike the S-C and J-K flip-flops, this flip-flop has only one synchronous control input, D, which stands for data The operation of the D flip flip-flop flop is very simple: Q will go to the same state that is present on the D input when a PGT occurs at CLK

Clocked D Flip-flop
In other words, the level present at D will be stored in the flip flip-flop flop at the instant the PGT occurs The operation of the D flip-flop can be described in a waveform

Clocked D Flip-flop
Assume that Q is initially HIGH. When the first PGT occurs at point a, the D input is LOW; thus, thus Q will go to the 0 state Even though the D input level changes between points a and b, it has no effect on Q; Q is storing the LOW that was on D at point a When the PGT at b occurs, Q goes HIGH since D is HIGH at that time Q stores this HIGH until the PGT at point c causes Q to go LOW, since D is LOW at that time In a similar manner, the Q output takes on the levels present at D when the PGTs occur at points d, e, f and g Note that Q stays HIGH at point e because D is still HIGH

Clocked D Flip-flop
Again, it is important to remember that Q can change only when a PGT occurs The D input has no effect between PGTs A negative negative-edge-triggered edge triggered D flip flip-flop flop operates in the same way we just described except that Q will take on the value of D when a NGT occurs at

CLK

The symbol for the D flip-flop that triggers on NGTs will have a bubble on the CLK input

Implementation of the D Flip-Flop

An edge-triggered D flip-flop is easily implemented by adding a single INVERTER to the edge-triggered edge triggered J-K flip-flop

If you try both values of D, you should see that Q takes on the level present at D when a PGT occurs

The T flip-flop
This flip-flop is made from a J-K flip-flop merely by connecting its J and K terminals together This means at all times, times J=K Substituting in the truth table of a J-K flip-flop gives the truth table below
J 0 0 1 1 K 0 0 1 1 Q 0 1 0 1 Q+ 0 1 1 0

From o t the e tab table e it t is s appa apparent e tt that, at, when e t the ec clock oc is s at 1, , the flip-flop will change state, or toggle, each time there is a trigger (T) pulse applied to its input

The T flip-flop
The T flip-flop is not available as an integrated circuit since it is so easily obtained from a J-K JK flip flop