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Lecture11 Decoders

The document discusses different types of decoders and encoders used in combinational logic design. It describes decoders as logic circuits with multiple inputs and outputs that activate the output corresponding to the binary input code. Encoders are the opposite, with multiple inputs mapping to a smaller number of outputs. Priority encoders are introduced to handle the situation when multiple decoder inputs are active simultaneously, by selecting the output with the highest priority. Expansion techniques allow building larger decoders from smaller decoder components. Examples of decoder and encoder logic diagrams, truth tables, and applications are provided.

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42 views26 pages

Lecture11 Decoders

The document discusses different types of decoders and encoders used in combinational logic design. It describes decoders as logic circuits with multiple inputs and outputs that activate the output corresponding to the binary input code. Encoders are the opposite, with multiple inputs mapping to a smaller number of outputs. Priority encoders are introduced to handle the situation when multiple decoder inputs are active simultaneously, by selecting the output with the highest priority. Expansion techniques allow building larger decoders from smaller decoder components. Examples of decoder and encoder logic diagrams, truth tables, and applications are provided.

Uploaded by

python17
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Combinational Logic Design

14/11/2013

Topics
Decoders Encoders Priority Encoders

!! !! !!

Fall 2013

EC381/Digital Systems I

Decoders
!! Typically

n inputs and 2n outputs !! Drives high the output corresponding to binary code of input

74139
Fall 2013 EC381/Digital Systems I 3

2-to-4 Line Decoder

!!

Notice they are minterms


EC381/Digital Systems I 4

Fall 2013

Truth Table, 3-to-8 Decoder

!! Notice

they are minterms


EC381/Digital Systems I 5

Fall 2013

3-to-8 Line Decoder Schematic

Fall 2013

EC381/Digital Systems I

2-to-4 with Enable

Fall 2013

EC381/Digital Systems I

Enable Used for Expansion

Fall 2013

EC381/Digital Systems I

Variations
Sometimes, in implementation decoders are done with NAND gates rather than AND gates. With NAND gates, the table illustrating the decoder operation would look like this:

So pay attention In using a decoder, it is useful to know when the output is intended to be active high, or active low!
Fall 2013 EC381/Digital Systems I 9

Decoder Expansion
!! !! !! !! !!

!!

A 2-to-4 Line decoder requires 4 (2-input) AND gates A 3-to-8 line decoder requires 8 (3-input) AND gates If we want to design a 6-to-64 line decoder then we will need? 64 (6-input) AND gates! Unfortunately, as decoders become larger, this approach gives a high gate input count! If we have decoders with enables, we can use multiple, small decoders to implement larger decoders.

Fall 2013

EC381/Digital Systems I

10

Decoder Expansion: Example


!! 4to16

decoder Using 3to8 decoders

Fall 2013

EC381/Digital Systems I

11

Decoder Expansion Example


!!

!!

!!

When w =0, the top decoder is enabled and the other is disabled. The bottom decoder outputs are all 0s, and the top eight outputs generate minterms 0000 to 0111. When w = 1, the enable conditions are reversed
EC381/Digital Systems I 12

Fall 2013

Example decoder tree: 4to16 decoder Using 2to4 decoders

Fall 2013

EC381/Digital Systems I

13

Uses for Decoders


!! Implement

logic circuits! !! Memory address lines !! Decoders are used in Micro Computer Interfacing for Keyboard and Display applications.

Fall 2013

EC381/Digital Systems I

14

Decoders as General-purpose Logic


!!

n:2n decoder implements any function of n variables


"! "! "!

With the variables used as control inputs Enable inputs tied to 1 and Appropriate minterms summed to form the function

Decoder generates appropriate minterm based on control signals (it "decodes" control signals)

Fall 2013

EC381/Digital Systems I

15

Decoders as General-purpose Logic


!!

Example: Implement the following boolean functions


1.! 2.!

S(x,y,z) = SUM(m(1,2,4,7))

C(x,y,z) = SUM(m(3,5,6,7))

Fall 2013

EC381/Digital Systems I

16

Example
!!

F1 = A' B C' D + A' B' C D + A B C D


0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD
17

F1

Enable

4:16 DEC

Fall 2013

EC381/Digital Systems I

A B C D

Encoder
Encoder is the opposite of decoder !! 2n inputs !! n outputs
!!

Fall 2013

EC381/Digital Systems I

18

Truth Table

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EC381/Digital Systems I

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Inputs are Minterms


A0 = D1 + D3 + D5 + D7

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EC381/Digital Systems I

20

Whats the Problem?


What if D3 and D6 both high? !! Simple OR circuit will set A to 7 !! Solution?
!!

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EC381/Digital Systems I

21

Priority Encoder
!!

Chooses one with highest priority


"!

Largest number, usually

!!

Note dont cares

What if all inputs are zero?


Fall 2013 EC381/Digital Systems I 22

Priority Encoder

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EC381/Digital Systems I

23

K Map for a priority encoder


!! X

on input means we must satisfy for both possibilities: 0, 1

Valid (V) is OR of inputs

Fall 2013

EC381/Digital Systems I

24

K Map for a priority encoder

Fall 2013

EC381/Digital Systems I

25

Logic Diagram of a 4-input Priority Encoder

Fall 2013

EC381/Digital Systems I

26

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