Evm5515 TechRef Revb

TMS320C5515 Evaluation Module (EVM) Technical Reference
2010
DSP Development Systems
TMS320C5515 Evaluation Module (EVM) Technical Reference
512705-0001 Rev. A February 2010
SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.
WARNING
To minimize risk of electric shock hazard, use only the following power supply for the EVM module with Medical Development Applications: SL Power AULT Model MW173KB0503F01.
Copyright 2010 Spectrum Digital, Inc.
Contents
Introduction to the TMS320C5515 Evaluation Module ....................... 1-1 Provides you with a description of the TMS320C5515 EVM, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 C5515 GPIO Terminal Functions ......................................... 1-4 1.5 C5515 EVM Memory Map .............................................. 1-7 1.6 C5515 I2C Addressing ................................................. 1-8 2 Operation and Physical Specifications ...................................... 2-1 Describes the operation and physical layout of the TMS320C5515 EVM and its connectors. 2.1 Board Layout ....................................................... 2-3 2.2 Connector Index .................................................... 2-5 2.2.1 J1, RS-232 Connector .............................................. 2-6 2.2.2 J2, Embedded USB Emulation Connector ............................. 2-7 2.2.3 J3, I2C Probe ..................................................... 2-7 2.2.4 J4, Headphone Connector ........................................... 2-8 2.2.5 J5, HDR4 Connector ............................................... 2-8 2 2.2.6 J6, I C Probe Headers ............................................. 2-9 2.2.7 J7, Stereo Out Connector ........................................... 2-9 2.2.8 J8, External JTAG Header ......................................... 2-10 2.2.9 J9, Stereo In 1 Connector .......................................... 2-10 2.2.10 J10, Daughter Card Interface ...................................... 2-11 2.2.11 J11, USB Type B Connector ....................................... 2-11 2.2.12 J12, Stereo In 2 Connector ........................................ 2-12 2.2.13 J13, Daughter Card Interface ...................................... 2-12 2.2.14 J14, Daughter Card Interface ...................................... 2-13 2.2.15 J15, MMC/SD Connector .......................................... 2-14 2.2.16 J16, +5 Volt In Connector ......................................... 2-15 2.2.17 J17, Embedded Emulation Interface ............................... 2-15 2.2.18 J18, Battery Holder .............................................. 2-15 2.2.19 J19, Display Interface ............................................. 2-16 2.2.20 M1, Left Microphone .............................................. 2-16 2.2.21 M2, Right Microphone ............................................ 2-16 2.2.22 Blue Tooth Board Interface ....................................... 2-17 2.2.22.1 P1, Blue Tooth Board Interface Connector ......................... 2-17 2.2.22.2 P2, Blue Tooth Board Interface Connector ......................... 2-18 2.3 System LEDs ..................................................... 2-18
2.4 C5515 EVM Switches ............................................. 2.4.1 SW1, RESET Switch .............................................. 2.4.2 SW2, WAKEUP Switch ............................................ 2.4.3 SW4, LDO Option DIP Switches ..................................... 2.4.4 SW5, On/Off Switch ............................................... 2.4.5 SW6-SW15, Function Switches ...................................... 2.5 Jumpers .......................................................... 2.5.1 C5515 EVM Option Jumpers ........................................ 2.5.1.1 JP2, nRESET Source Select ..................................... 2.5.1.2 JP3, UART_EN Select .......................................... 2.5.1.3 JP5, WAKEUP Source Select .................................... 2.5.1.4 JP6, LDO_EN Source Select .................................... 2.5.1.5 JP9, CLK_SEL Source Select ..................................... 2.5.1.6 JP12, MIC_BIAS Source Select ................................... 2.5.1.7 JP39, VIN Select .............................................. 2.5.2 C5515 EVM Power Domain Probe Points ............................ 2.6 Test Points ........................................................ A Schematics .............................................................. Contains the schematics for the TMS320C5515 EVM B Mechanical Information .................................................. Contains the mechanical information about the TMS320C5515 EVM
2-19 2-19 2-19 2-20 2-20 2-21 2-22 2-23 2-25 2-25 2-26 2-26 2-27 2-27 2-28 2-29 2-31 A-1 B-1
About This Manual This document describes the board level operations of the TMS320C5515 Evaluation Module (EVM). The EVM is based on the Texas Instruments TMS320C5515 Digital Signal Processor. The TMS320C5515 EVM is a table top card to allow engineers and software developers to evaluate certain characteristics of the TMS320C5515 DSP to determine if the processor meets the designers application requirements. Evaluators can create software to execute on board or expand the system in a variety of ways. The TMS320C5515 EVM can be used to develop TMS320C5504 applications since the TMS320C5504 processor is a subset of the TMS320C5515. Notational Conventions
This document uses the following conventions. The TMS320C5515 will sometimes be referred to as the C55XX. The TMS320C5515 EVM will sometimes be referred to as the EVM. Program listings, program examples, and interactive displays are shown is a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320C55XX DSP CPU Reference Guide Texas Instruments TMS320C55XX DSP Peripherals Reference Guide
Table 1: Hardware History Revision A B Prototype Release Production Release History
Table 2: Manual History Revision A History Production Release
Chapter 1 Introduction to the TMS320C5515 EVM
Chapter One provides a description of the TMS320C5515 EVM along with the key features and a block diagram of the circuit board.
Topic
1.1 1.2 1.3 1.4 1.5 1.6 Key Features Development Tools Power Supply C5515 GPIO Terminal Functions C5515 EVM Memory Map C5515 I2C Addressing
Page
1-2 1-3 1-3 1-4 1-7 1-8
1-1
Spectrum Digital, Inc

1.1 Key Features The C5515 EVM is a standalone development platform that enables users to evaluate and develop applications for the TI TMS320C5515 Digital Signal Processor (DSP). The EVM also serves as a hardware reference design for the TMS320C5515 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.
Figure 1-1, TMS320C5515 EVM The EVM comes with a full complement of on-board devices that suit a wide variety of application environments. Key features include: A Texas Instruments TMS320C5515 DSP operating up to 100 Mhz. 128 Mbytes of Mobile SDRAM 16 Megabytes of NOR Flash 64 Megabytes of NAND Flash 128 x 128 bit mapped color LCD display
1-2
TMS320C5515 EVM Technical Reference

TPS65023 Power Management IC for individual C5515 power rail control TLV320AIC3204 stereo codec with line in, line out, headphone, mic in, on board microphones MMC / SD Media Card Connector User USB 2.0 port via C5515 I2C EEPROM (256Kbits) and SPI EEPROM (256Kbits) Expansion connectors for Blue Tooth interface RS-232 Interface External JTAG emulation interface Embedded JTAG controller 10 User push button switches INA219 power measurement devices Optional battery power 1.2 Development Tools The EVM is designed to work with TIs Code Composer Studio (CCS) Integrated Development Environment (IDE). Code Composer Studio communicates with the EVM board through the external emulator header, or on board emulation. An EVM specific version of Code Composer Studio ships with the EVM.
1.3 Power Supply The EVM operates from a +5V external power supply or battery.
WARNING
To minimize risk of electric shock hazard, use only the following power supply for the EVM module with Medical Development Applications: SL Power AULT Model MW173KB0503F01.
1-3

1.4 C5515 GPIO Terminal Functions The C5515 has multiple GIO signals that can be used for system level tasks. The GIO signals are connected to various connectors on the EVM. Refer to the discussion of the connectors later in this document for details. The next table describes how the GIO lines are used on the EVM.
1-4

Table 1: C5515 GPIO Terminal Functions
C5515 Pin #
M8 L10 M11 L9 M10
C5515 Default Multiplexed Function

XF MMC0_CLK MMC0_CMD MMC0_DATA0 MMC0_DATA1
GPIO Pin
XF GP[0] GP[1] GP[2] GP[3]
Routed To
LED D2, TP4 MMC0_CLK = SH16, J15-5, MMC/SD connector GP[0] = SH18, ADS_GPIO0, J13-12 MMC0_CMD = SH16, J15-2, MMC/SD connector GP[1] = SH18, ADS_GPIO1, J13-8 MMC0_DATA0 = SH16, J15-7, MMC/SD connector GP[2] = SH18, ADS_GPIO2, J13-22 MMC0_DATA1 = SH16, J15-8, MMC/SD connector GP[3] = SH18, ADS_GPIO3, J13-21 MMC0_DATA2 = SH16, J15-9, MMC/SD connector GP[4] = SH5, GPIO4, P1-10 GP[4] = SH18, ADS_GPIO4, J13-1 MMC0_DATA3 = SH16, J15-1, MMC/SD connector GP[5] = SH5, GPIO, P1-12 GP[5] = SH18, ADS_GPIO5, TP14 MMC1_CLK, SH5, P1-15, Blue Tooth Board Interface GP[6] = SH18, I2S1_CLK, J13-5 GP[6] = SH5, I2S1_CLK_CC, P2-17 GP[6] = SH16, MMC0_WP, J15-WP, TP19 MMC1_CMD = SH5, P1-17, Blue Tooth Board Interface GP[7] =I2S1_FS, SH18, J13-9 GP[7] = I2S1_FS_CC, SH5, P2-11 GP[7] = MMC0_INS, SH16, J15-Card Detect, TP22 MMC1_DATA0 = SH5, P1-2, Blue Tooth Board Interface GP[8] = I2S1_DX, SH18, J13-19 GP[8] = I2S1_DX_CC, SH5, P2-8 MMC1_DATA1 = SH18, P1-4, Blue Tooth Board Interface GP[9] = I2S1_RX, SH18, J13-14 GP[9] = I2S1_RX_CC, SH5, P2-10 MMC1_DATA2, SH5, P1-6, Blue Tooth Board Interface GP[10] = AIC_RST, SH19, U12-31 GP[10] = ADS_GPIO10, SH18, J13-6 MMC1_DATA3 = SH5, P1-8, Blue Tooth Board Interface GP[11] = GPIO, SH18, J13-11 GP[11] = GPIO11_LCD_PWR, SH20, J19-?? LCD_DATA0 = SH20, J19-14 Input LCD_DATA0 = SPI_ALT_RX , SH5, P1-20 LCD_DATA1 = SH20, J19-13 LCD_DATA1 = SPI_ALT_D, SH5, P1-18 LCD_DATA2 = SH20, J19-12 LCD_DATA2 = GPIO12, SH5, P2-13 LCD_DATA3 = SH20, J19-11 LCD_DATA3 = GPIO13, SH5, P2-20 LCD_DATA4 = SH20, J19-10 LCD_DATA4 = GPIO14_CC, SH5, P2-15 LCD_DATA5 = SH20, J19-9 LCD_DATA6 = SH20, J19-8 LCD_DATA7 = SH20, J19-7 LCD_DATA8 = I2S2_CLK, SH19, U12-2 LCD_DATA8 = SPI_CLK, SH17, U9-6 LCD_DATA8 = SPI_CLK, SH18, J13-3 LCD_DATA8 = I2S2_CLK, SH19, U12-2
L12
MMC0_DATA2
GP[4]
L11
MMC0_DATA3
GP[5]
M13
MMC1_CLK
GP[6]
L14
MMC1_CMD
GP[7]
M14
MMC1_DATA0
GP[8]
M12
MMC1_DATA1
GP[9]
K14
MMC1_DATA2
GP[10]
L13 P6 N6 P7 N7 N8 P9 N9 P10 N10
MMC1_DATA3 LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 LCD_DATA8
GP[11] SPI_RX SPI_TX GP[12] GP[13] GP[14] GP[15] GP[16] GP[17] GP[18]
1-5

Table 1: C5515 GPIO Terminal Functions
C5515 Pin # C5515 Default Multiplexed Function
LCD_DATA9
GPIO Pin
Routed To
LCD_DATA9 = I2S2_FS, SH19, U12-3 LCD_DATA9 = SPI_CS0, SH17, U9-1 LCD_DATA9 = SPI_CS0, SH18, J13-7 LCD_DATA9 = I2S2_FS, SH19, U12-3 LCD_DATA10 = I2S2_RX, SG 19, U12-5 LCD_DATA10 = SPI_RX, SH17, U9-2 LCD_DATA10 = SPI_RX, SH18, J13-13 LCD_DATA10 = I2S2_RX, SH19, U12-5 LCD_DATA11 = I2S2_DX, SH19, U12-4 LCD_DATA11 = SPI_DX, SH17, U9-5 LCD_DATA11 = SPI_DX, SH18, J13-11 LCD_DATA11 = I2S2_DX, SH19, U12-4 LCD_DATA12 = UART_RTS, SH5, P1-3 LCD_DATA12 = UART_RTX, SH17, U5-12 LCD_DATA13 = UART_CTS, SH5, P2-18 LCD_DATA12 = UART_CTS, SH 17, U5-10 LCD_DATA14 = UART_RX, SH5, P1-7 LCD_DATA14 = UART_RX, SH17, U5-15 LCD_DATA15 = UART_TX, SH5, P1-9 LCD_DATA15 = UART_TX, SH17, U5-13 LCD_EN_RDB = LCD_RE, SH20, J19-15 LCD_EN_RDB = LCD_RE = SPI_ALT_CLK, SH5, P1-16 LCD_CS0_E0 = LCD_BIAS_OE, SH20, J19-19 LCD_CS1_E1 = LCD_MCLK = SPI_ALT_CS1, SH5, P1-14 LCD_RW_WRB = LCD_nWE, SH20, J19-16 LCD_RS = LCD_ALE, SH20, J19-20
P11
GP[19]
N11
LCD_DATA10
GP[20]
P12
LCD_DATA11
GP[27]
N12 P13 N13 P14 N3 P4 N4 P5 N5
LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 LCD_EN_RDB LCD_CS0_E0 LCD_CS1_E1 LCD_RW_WRB LCD_RS
GP[28] GP[29] GP[30] GP[31] SPIO_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_CS3
1-6

1.5 C5515 EVM Memory Map The C5515 EVM supports on chip DARAM, off chip SDRAM, off chip NOR flash, and off chip NAND Flash. The addressing for each of these memory blocks is shown in the figure below.
CPU Byte Address 000000h 0000C0h Internal DARAM 010000h Internal DARAM 050000h 800000h C00000h E00000h F00000h FE0000h FFFFFFh Mobile SDRAM External-CS0 Space NOR Flash External-CS2 Space Not Used External-CS3 Space NAND Flash External-CS4 Space Not Used External-CS5 Space ROM (if MPNMC=0) External-CS5 Space (if MPNMC=1)
MEMORY BLOCKS
(MMR Reserved)
Figure 1-2, EVM C5515 Memory Map
1-7

1.6 C5515 I2C Addressing The C5515 EVM has multiple I2C devices for different purposes. The table below shows the addresses of these devices on the I2C bus. Table 2: C5515 GIO Schedule
EVM I2C Device TLV320AIC3204 INA219 INA219 INA219 INA219 INA219 INA219 INA219 TPS62023 CAT24WC256X I2C Address 0x18 0x40 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x50
2
Function Audio CODEC CPU core power measurement, VDDC, U3 CPU DVDD EMIF power measurement, DC_VDD_IO2 U7 CPU USB LDO power measurement, USB_VDD_IN, U21 CPU DVDD IO power measurement, DC_VDD_IO1, U20 CPU 3V3 power measurement, 3.3V, U27 CPU 1V8 power measurement, 1.8V, U23 CPU 5V0 power measurement, 5V, U24 PMIC - Not Used I C Interface EEPROM
1-8
Chapter 2 Physical Description
This chapter describes the physical layout of the TMS320C5515 EVM and its connectors.
Topic
2.1 Board Layout 2.2 Connector Index 2.2.1 J1, RS-232 Connector 2.2.2 J2, Embedded USB Emulation Connector 2.2.3 J3, I2C Probe 2.2.4 J4, Headphone Connector 2.2.5 J5, HDR4 Connector 2.2.6 J6, I2C Probe 2.2.7 J7, Stereo Out Connector 2.2.8 J8, External JTAG Header 2.2.9 J9, Stereo In 1 Connector 2.2.10 J10, Daughter Card Interface 2.2.11 J11, USB Type B Connector 2.2.12 J12, Stereo In 2 Connector 2.2.13 J13, Daughter Card Interface 2.2.14 J14, Daughter Card Interface 2.2.15 J15, MMC/SD Connector 2.2.16 J16, +5 Volt In Connector 2.2.17 J18, Battery Holder 2.2.18 J19, Display Interface 2.2.19 M1, Left Microphone 2.2.20 M2, Right Microphone 2.2.21 Blue Tooth Board Interface 2.2.21.1 P1, Blue Tooth Board Interface Connector 2.2.21.2 P2, Blue Tooth Board Interface Connector
Page
2-3 2-5 2-6 2-7 2-7 2-8 2-8 2-9 2-9 2-10 2-10 2-11 2-11 2-12 2-12 2-13 2-14 2-15 2-15 2-16 2-16 2-16 2-17 2-17 2-18
2-1
Spectrum Digital, Inc Topic

2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.5 2.5.1 2.5.1.1 2.5.1.2 2.5.1.3 2.5.1.4 2.5.1.5 2.5.1.6 2.5.1.7 2.5.2 2.6 System LEDs C5515 EVM Switches SW1, RESET Switch SW2, WAKEUP Switch SW4, LDO Option DIP Switches SW5, On/Off Switch SW6-SW15, Function Switches Jumpers C5515 EVM Option Jumpers JP2, nRESET Source Select JP3, UART_EN Select JP5, WAKEUP Source Select JP6, LDO_EN Source Select JP9, CLK_SEL Source Select JP12, MIC_BIAS Source Select JP39, VIN Source Select C5515 EVM Power Domain Probe Points Test Points
Page
2-18 2-19 2-19 2-19 2-20 2-20 2-21 2-22 2-23 2-25 2-25 2-26 2-26 2-27 2-27 2-28 2-29 2-31
2-2

2.1 Board Layout The C5515 EVM is a 6.35 x 5.75 inch (161 x 146 mm.) ten (10) layer board which is powered by an external +5 volt only power supply. Figure 2-1 shows the layout of the top side of the C5515 EVM.
J1 DS1 P1 J10 P2 J3 D2 SW1 SW2 M1
J2
J5 J4 J6
J8 J13
J7
J9 J11 J14 J12 J15 SW4
M2 SW5 SW8
J16 SW12
SW9
SW6
SW10
SW13
SW14
SW11
SW15
SW7
D8
Figure 2-1, TMS320C5515 EVM (Top)
2-3

Figure 2-2 shows the layout of the bottom side of the C5515 EVM.
J18
J19
Figure 2-2, TMS320C5515 EVM (Bottom)
2-4

2.2 Connector Index The TMS320C5515 EVM has twenty-three (23) connectors which provide the user access to the various signals on the EVM. Table 1: New TMS320C5515 EVM Connectors
Connector / Schematic Page J1 / 17 J2 / 25 J3 / 15 J4 / 19 J5 / 19 J6 / 2 J7 / 19 J8 / 4 J9 / 19 J10 / 18 J11 / 3 J12 / 19 J13 / 18 J14 / 18 J15 / 16 J16 / 13 J17 / 23 J18 / 13 J19 / 20 M1 / 19 M2 / 19 P1 / 5 P2 / 5 # Pins 9 5 3 2 4 3 2 14 2 10 4 2 22 20 18 2 10 2 30 2 2 20 20 RS-232 Embedded USB Emulation Port I
2C
Function
Board Side Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Bottom Bottom Bottom Top Top Top Top
Probe
Headphones Out HDR4 Connector I

2C
Probe Headers
Stereo Out JTAG Header Stereo In 1 Daughter Card Interface USB Type B Connector Stereo In 2 Daughter Card Interface Daughter Card Interface MMC/SD Card +5 Volt In Factory use only Battery Holder Display Interface Left Microphone Right Microphone Blue Tooth Board Interface blue tooth Board Interface
2-5

2.2.1 J1, RS-232 Connector The C5515 EVM has an RS-232 connector, J1, which brings out the transmit and receive of the processor. This EVM uses the MAX3222 RS-232 line driver. The pin positions for the J1 connector as viewed from the edge of the printed circuit board are shown below.
1 6 2 7 3 8 4 9 5
Figure 2-3, J1, DB9 Male Connector The pin numbers and their corresponding signals are shown in the table below. This corresponds to a DB-9 connector interface used on personal computers. Table 2: J1, RS-232 UART Pinout
Pin # 1 2 3 4 5 6 7 8 9 10 11 Signal Name No Connect RXD TXD No Connect No Connect No Connect RTS CTS GND GND_SHIELD GND_SHIELD
2-6

2.2.2 J2, Embedded USB Emulation Connector Connector J2 provides a Mini-B Universal Serial Bus (USB) Interface to the embedded JTAG emulation logic on the EVM. This allows for code development and debug without the use of an external emulator. This USB connector is for embedded emulation support only.
2.2.3 J3, I2C Probe Headers Connector J3 brings out the I2C signals from the C5515 processor. The signals are shown in the table below. Table 3: J3, I2C Probe Headers
Pin # 1 2 3 Signal Name I2C_SDA I2C_SCL GND
Shown below is a top view of the J3 connector. GND SCL SDA 1 Figure 2-4, Top View of the J3 Connector J3
2-7

2.2.4 J4, Headphone Connector Connector J4 is a headphone/speaker jack. It can drive standard headphones or a high impedance speaker directly. These outputs connect to HEADPHONE LOUT and HEADPHONE_ROUT of the TLV320AIC3204. The standard 3.5 mm jack is shown in the figure below.
Ground Right Headphone Left Headphone Figure 2-5, Headphone Connector
2.2.5 J5, HDR4 Connector The HDR4 connector brings out 4 signals from the TLV320AIC3204. These signals are shown in the table below. Table 4: J5, HDR4 Connector
Pin # 1 2 3 4 Signal Name AIC_SCLK AIC_MISO AIC_SPI_SEL AIC_MOSI
Shown below is a top view of the J5 connector. AIC_MOSI AIC_SPI_SEL AIC_MISO J5 1 AIC_SCLK
Figure 2-6, Top View of the J5 Connector
2-8

2.2.6 J6, I2C Probe Connector J6 brings out the I2C signals from the C5515 processor. The signals are shown in the table below. Table 5: J6, I2C Probe Headers
Pin # 1 2 3 Signal Name I2C_SDA I2C_SCL GND
Shown below is a top view of the J6 connector. J6 GND SCL 1 2.2.7 J7, Stereo Out Connector The audio line out, J7, is a stereo output. These outputs connect to AIC3254_LOUT and AIC3254_ROUT of the TLV320AIC3204.The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below. SDA Ground Right Line Out Left Line Out Figure 2-8, Stereo Out Connector
Figure 2-7, Top View of the J6 Connector
2-9

2.2.8 J8, External JTAG Header The TMS320C5515 EVM is supplied with a 14 pin header interface, J8. This is the standard interface used by JTAG emulators to interface to Texas Instruments processors. The pinout for the connector is shown in the figure below. Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal * Embed/External EMU Select
TMS TDI Vcc TDO RTCK TCK EMU0
1 3 5 7 9 11 13
2 4 6 8 10 12 14
TRSTGND no pin (key) GND * GND GND EMU1
Figure 2-9, JTAG INTERFACE
2.2.9 J9, Stereo In 1 Connector The J9 connector in is a stereo input. The input connector is a 3.5 mm stereo jack. These inputs connect to AIC_LINE2L and AIC_LINE2R of the TLV320AIC3204. The signals on the mating plug are shown in the figure below.
Ground Right Line In Left Line In Figure 2-10, Stereo In 1 Jack
2-10

2.2.10 J10, Daughter Card Interface The TMS320C5515 EVM has 3 daughter card interfaces, J10, J13, and J14. The Medical Development Kit (MDK) daughter cards from Texas Instruments use these interfaces. For more information about these cards refer to the following web sites: http://focus.ti.com/docs/toolsw/folders/print/tmdxmdkek1258.html http://focus.ti.com/docs/toolsw/folders/print/tmdxmdkds3254.html http://focus.ti.com/docs/toolsw/folders/print/tmdxmdkpo8328.html Connector J10 is a 2 x 5 double row male header (.1 in. centers) used to interface to plug on daughter cards. The signals on this connector are shown in the table below. Table 6: J10, Daughter Card Interface
Pin # 2 4 6 8 10 Signal Name NC NC NC NC V5 Pin # 1 3 5 7 9 Signal Name NC NC GND V1.8 V3.3
2.2.11 J11, USB Type B Connector The J11 connector is a USB Type B connector. This connector interfaces directly to the C5515 processor. The signals on this connector are shown in the table below. Table 7: J11, USB Type B Connector
Pin # 1 2 3 4 5 5 USB Signal VBUS DD+ GND GND GND C5515 Signal, Pin USB VBUS, J12 USB_DM, J14 USB_DP, H14
2-11

2.2.12 J12, Stereo In 2 Connector The J12 connector in is a stereo input. The input connector is a 3.5 mm stereo jack. These inputs connect to AIC_LINE3L and AIC_LINE3R of the TLV320AIC3204. The signals on the mating plug are shown in the figure below.
Ground Right Line In Left Line In Figure 2-11, Stereo In 2 Jack
2.2.13 J13, Daughter Card Interface Connector J13 is a 2 x 11 double row male header (.1 in. centers) used to interface to plug on daughter cards. The signals on this connector are shown in the table below. Table 8: J13, Daughter Card Interface
Pin # 1 3 5 7 9 11 13 15 17 19 21 Signal Name ADS_GPIO4 SPI_CLK GPIO6 / I2S1_CLK SPI_CS0 GPIO7 / I2S1_FS SPI_DX SPI_RX INT1 XF GPIO8 / I2S1_DX ADS_GPIO3 Pin # 2 4 6 8 10 12 14 16 18 20 22 Signal Name GPIO11 GND ADS_GPIO10 ADS_GPIO1 GND ADS_GPIO0 GPIO9 / I2S1_RX I2C_SCL GND I2C_SDA ADS_GPIO2
2-12

2.2.14 J14, Daughter Card Interface Connector J14 is a 2 x 10 double row male header (.1 in. centers) used to interface to plug on daughter cards. The signals on this connector are shown in the table below. Table 9: J14, Daughter Card Interface
Pin # 2 4 6 8 10 12 14 16 18 20 Signal Name GPAIN0 GPAIN1 GPAIN2 GPAIN3 NC NC NC NC NC NC Pin # 1 3 5 7 9 11 13 15 17 19 Signal Name No connect No connect No connect No connect GND GND GND NC GND GND
2-13

2.2.15 J15, MMC/SD Connector Connector J15 is used to provide a MMC/SD interface to the C5515 processor. The signals on this connector are shown in the table below. Table 10: J15, MMC/SD Connector
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Signal Name MMC0_DATA3 MMC0_CMD GND VDD_IO1 MMC0_CLK GND MMC0_DATA0 MMC0_DATA1 MMC0_DATA2 WP COM / GND CARD_DETECT No Connect No Connect No Connect No Connect No Connect No Connect
2-14

2.2.16 J16, +5 Volt In Connector Power (+5 volts) is brought onto the TMS320C5515 EVM via the J16 connector. The connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The diagram of J7 is shown below. +5V J16 Ground PC Board Front View Figure 2-12, J16, TMS320C5515 EVM Power Connector
2.2.17 J18, Battery Holder Connector J18 is a battery holder on the bottom side of the board. This battery holder will accommodate two (2) AA size batteries. The ground and positive voltage from the battery go to the voltage regulator U26, TPS61030-ADJ. Jumper JP39 is used to select the voltage input source (power jack or the battery holder).
2-15

2.2.18 J19, Display Interface Connector J19 provides an interface to a display module. This connector is located on the bottom side of the board. The signals on this connector are shown in the table below. Table 11: J19, Display Interface
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signal Name GND V13 VCOMH VDD_IO1 / VDDIO VSL NC LCD_DATA7 / D7 LCD_DATA6 / D6 LCD_DATA5 / D5 LCD_DATA4 / D4 LCD_DATA3 / D3 LCD_DATA2 / D2 LCD_DATA1 / D1 LCD_DATA0 / D0 LCD_RE / E/RDn Pin # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Signal Name LCD_nWE / R/Wn GND / BS0 VDD_IO1 / BS1 LCD_BIAS_OE / CEn LCD_ALE / D/Cn nRESET / RESETn IREF GPIO1 GPIO0 NC-25 VDD VDD_IO1 / VCI GND / VSS NC-29 GND / NC-30
2.2.19 M1, Left Microphone The M1 microphone (left channel) connects to the AIC_MIC1L input of the TLV320AIC3204.
2.2.20 M2, Right Microphone The M2 microphone (right channel) connects to the AIC_MIC1R input of the TLV320AIC3204.
2-16

2.2.21 Blue Tooth Board Interface Connectors Connectors P1 and P2 make up the Blue Tooth Board Interface. Both connectors are 2 x 10 double row headers and are specifically spaced to interface directly to Texas Instruments Blue Tooth modules. 2.2.21.1 P1, Blue Tooth Board Interface Connector Connector P1 is a 2 x 10 double row used to interface to plug on daughter cards. The signals on this connector are shown in the table below. Table 12: P1, Blue Tooth Board Interface
Pin # 1 3 5 7 9 11 13 15 17 19 Signal Name GND UART_RTS RTC_CLKOUT UART_RX UART_TX I2C_SDA I2C_SCL MMC1_CLK MMC1_CMD GND Pin # 2 4 6 8 10 12 14 16 18 20 Signal Name MMC1_DATA0 MMC1_DATA1 MMC1_DATA2 MMC1_DATA3 GPIO4 GPIO5 SPI_ALT_CS1 SPI_ALT_CLK SPI_ALT_DX SPI_ALT_RX
2-17

2.2.21.2 P2, Blue Tooth Board Interface Connector Connector P2 is a 2 x 10 double row used to interface to plug on daughter cards. The signals on this connector are shown in the table below. Table 13: P2, Blue Tooth Board Interface
Pin # 1 3 5 7 9 11 13 15 17 19 Signal Name NC NC NC V3.3 V3.3 I2S1_FS_CC GPIO12 GPIO14_CC I2S1_CLK_CC GPIO14_CC Pin # 2 4 6 8 10 12 14 16 18 20 Signal Name GND NC NC I2S1_DX_CC I2S1_RX_CC NC NC NC UART_CTS GPIO13
2.3 System LEDs TheTMS320C5515 EVM has three light emitting diodes (LEDs). These LEDs indicate various conditions on the EVM. These function of each LED is shown in the table below. Table 14: System LEDs
Reference Designator D2 D8 DS1 Color Green Red Green Function Connected to the XF bit on the C5515 processor Indicates +5 volts is applied at the J7 connector Emulator busy Schematic Page 2 13 N/A
2-18

2.4 C5515 EVM Switches The C5515 EVM has 14 switches. A list of the switches is shown in the table below: Table 15: TMS320C5515 EVM Switches
Switch SW1 SW2 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12 SW13 SW14 SW15 Silkscreen Nomenclature/ Function RESET WAKEUP 2 Position DIP Power On/Off MENU UP MODE SHIFT REWIND (RWD) PLAY FORWARD (FWD) STOP DOWN (DN) REC Schematic Page 14 2 14 13 18 18 18 18 18 18 18 18 18 18 Board Side Top Top Top Top Top Top Top Top Top Top Top Top Top Top
2.4.1 SW1, RESET Switch This switch asserts the nRESET signal to all major components on the C5515 EVM board. 2.4.2 SW2, WAKEUP Switch Wakeup is an active high external input signal used to wake up the core from the power off state. It can be configured as an active low open drain output signal. A pull up / pull-down jumper (JP5) is provided to accommodate both active high and active low states.
2-19

2.4.3 SW4, LDO Option DIP Switches SW4 is a 4 position DIP used to select LDO options. The table below shows the functions of the 4 positions. When switch is in the ON position a logic 0 is applied to the signal. When the switch is in the OFF position a logic 1 is applied to the signal. VDD_IO1_SEL ON 2 1 SW4 Tied to DEFLDO2 on TPS65023
Tied to DEFCDCD1 on TPS65023 V_CORE_SEL Figure 2-13, SW4 Switch
Table 16: LDO Option DIP Switches

Switch Position 1 - ON * 1 - OFF 2 - ON * 2 - OFF Signal State Low High Low High Signal V_CORE_SEL = 1.3V V_CORE_SEL = 1.05V VDD_IO1_SEL = 3.3V VDD_IO1_SEL = 1.8V Function For proper device operation, this switch must be in the ON position For proper device operation, this switch must be in the ON position Default Setting ON/Low
ON/Low
* default position 2.4.4 SW5, Power On/Off Switch The On/Off switch provides +5 volts to the logic on the board. In the OFF position this switch interrupts the power from the power supply as well as the battery holder.
2-20

2.4.5 SW6 - SW15, Function Switches Switches SW6-SW15 are push button momentary switches which are read by the processor. These switches can take on any function defined by user software. The silk screen nomenclature is provided for user convenience and are shown in the table below. Table 17: Function Switches
Switch # SW6 SW7 SW8 SW9 SW10 SW11 SW12 SW13 SW14 SW15 Silk Screen Name MENU UP MODE SHIFT REWIND (RWD) PLAY FORWARD (FWD) STOP DOWN (DN) REC
2-21

2.5 Jumpers The C5515 EVM has twenty-nine (29) jumpers locations. These jumpers can be divided into 3 classes; factory installed options, user options, and power domain probe points. The following sections describe the jumpers in these classes. The position of these jumpers on the top side of the EVM board are shown in the figures below.
JP3 JP38 JP15 JP11 JP9 JP37 JP1 JP4 JP2 JP5 JP7
JP8
JP40
JP14 JP17 JP12 JP19 JP20 JP23 JP13 JP18 JP16 JP6 JP25 JP22 JP21 JP24 JP39 JP26
Figure 2-14, TMS320C5515 EVM Jumpers (Top)
2-22

2.5.1 C5515 EVM Option Jumpers The C5515 EVMs option jumpers fall into two categories; user selectable, and factory installed. The table below shows lists the user option jumpers and their function. Table 18: C5515 EVM User Option Jumpers
Jumper #/ Schematic Page
JP2 / 12
Nomenclature
# of Positions
Setting
1-2*
Function
Use RESET from TPS65023 Use RESET from SW1 UART transceiver enabled UART transceiver disabled WAKEUP pin uses pull up WAKEUP pin uses pull down Enable internal DSP LDO Disable internal DSP LDO CLK_SEL tied to VDD_IO1 CLK_SEL tied to GND Use 3.3V Use AIC output Power is from battery Power is from external 5v supply
nRESET Select
2-3 Shorted *
JP3 / 17
UART_EN
Open 1-2
JP5 / 2
WK_PU_PD_SEL
2-3* Shorted *
JP6 / 10
LDO_EN
Open Shorted
JP9 / 3
CLK_SEL
Open * 1-2
JP12 / 10
MIC_BIAS
2-3* 1-2
JP39 / 13
VIN Select
2-3*
* Factory default
2-23

The factory installed jumpers are pre-configured with a zero (0) ohm resistor at the factory and are not meant to be changed by users. These jumpers are not populated with a jumper header. The table below lists the factory installed option jumpers and their function. Table 19: C5515 EVM Factory Installed Power Domain Configuration
JP1 / 11
Nomenclature
# of Positions
Setting
1 - 2 *+
Function
Internal DSP-LDO used DSP will use external 1.3 volt CVDDRTC tied to V1.3 Do Not Use LDO_IN tied to V1.8 LDO_IN tied to V3.3 DSP will use internal USB LDO DSP will use external 1.3V Internal Analog-LDO used DSP will use external 1.3V Internal Analog-LDO used DSP will use external 1.3V
CPU VDDC Select
2-3 1-2*
JP4 / 3
RTC
2-3 1-2*
JP11 / 10
LDOI Select
2-3 1 - 2 *z
JP15 / 11
USB_VDD_IN Select
2-3 1-2*
JP16 / 10
VDDA_ANA Select
2-3 1-2*
JP18 / 10
VDDA_PLL Select
2-3
* Default + JP6 must be installed Z USB LDO must be enabled in software
2-24

2.5.1.1 JP2, nRESET Source Select Jumper JP2 is a three position jumper that allows the user to the select the source of the nRESET signal to the C5515 processor. This jumper is pre-configured at the factory with a jumper in the 2-3 position (*).The table below shows the positions and their function. Table 20: JP2, nRESET Source Select
Jumper Position 1-2 * 2-3 Function PWR_RSTn is the source of the nRESET signal to the C5515 Processor SW1 is the source of the nRESET signal to the C5515 Processor
Shown below is a top view of the JP2. 1 JP2 1-2 Position JP2 2-3 Position 1
Figure 2-15, Top View of the Jumper JP2
2.5.1.2 JP3, UART_EN Select Jumper JP3 is a two position populated jumper that enables/disables the UART driver on the EVM. This jumper is pre-configured at the factory with a jumper in place (*). The table below shows the positions and their function. Table 21: JP3, UART Enable Jumper
Jumper Position Open Shorted * Function EN_L pulled to GND thereby disabling the MAX3222 line driver EN_L pulled to +3.3 thereby enabling the MAX3222 line driver
Shown below is a top view of the JP3. UART_EN UART_EN
JP22
JP22
Factory Configuration
Open
Shorted
Figure 2-16, Top View of the Jumper JP3
2-25

2.5.1.3 JP5, WAKEUP Source Select Jumper JP5 is a three position jumper that allows the user to the select the a pull up or pull down WAKEUP signal to the C5515 processor (U13-E8). This jumper is pre-configured at the factory with a jumper in the 2-3 position (*). The 1-2 position allows the switch, SW2, to wake up the processor. The table below shows the positions and their function. Table 22: JP5, WAKEUP Source Select
Jumper Position 1-2 2-3 * Function Depressing switch SW2 wakes up the C5515 Processor (uses pull up) WAKEUP pin uses Pull Down
Shown below is a top view of the JP5. JP5 1 WK_PU_PD JP5 1 WK_PU_PD JP6
Shorted
1-2 Position 2-3 Position Figure 2-17, Top View of the Jumper JP5 2.5.1.4 JP6, LDO_EN Source Select Jumper JP6 is a two position jumper located on the top side of the circuit board that selects the level of the LDO_EN signal. When the jumper is shorted, LDO_EN is pulled to GND enabling on-chip LDOs. If the jumper is open, LDO_EN is pulled high disabling on-chip LDOs. This jumper must be installed. The table below shows the positions and their function. Table 23: JP6, LDO_EN Select
Jumper Position Open Shorted * Function LDO_EN, is pulled high, LDOs enabled LDO_EN is low, the internal LDO is enabled
* Default Shown below is a top view of the JP6. JP6

Open
Figure 2-18, Top View of the Jumper JP6 2-26 TMS320C5515 EVM Technical Reference

2.5.1.5 JP9, CLK_SEL Source Select Jumper JP9 is a two position jumper that determines if the DSP uses an external or internal oscillator. The shorted state allows an external oscillator to be used when an oscillator is populated in the 8 pin OSC1 socket. An open jumper means the DSP will use an internal oscillator. The jumper is pre-configured at the factory in the open state. The table below shows the positions and their function. Table 24: JP9, CLK_SEL Select
Jumper Position Open * Shorted Function Use internal oscillator for DSP clock Use external oscillator for DSP clock
* Default Shown below is a top view of the JP9. JP9 CLK_SEL 1 JP9 CLK_SEL 1
Function When R209 is installed bias is 3.3 volts Bias from TLV320AIC3204 MICBIAS pin
Factory Configuration
Open Shorted Figure 2-19, Top View of the Jumper JP9
2.5.1.6 JP12, MIC_BIAS Source Select Jumper JP12 is a three position populated jumper that selects the source of the microphone bias used for AIC MIC1L and AIC MIC1R on the TLV320AIC3204. The table below shows the positions and their function. Table 25: JP12, Microphone Bias Select
Jumper Position 1-2 2-3 *
* Default Shown below is a top view of the JP12. JP12 MIC_BIAS JP12 MIC_BIAS 1 1
1-2 Position 2-3 Position Figure 2-20, Top View of the Jumper JP12 2-27

2.5.1.7 JP39, VIN Source Select Jumper JP39 is a three position populated jumper located on the top side of the circuit board that selects the source of the incoming +5 volts. The table below shows the positions and their function. Table 26: JP39, VIN Source Select
Jumper Position 1-2 2-3* Function Battery is selected as source for +5 volts input External power supply is selected as source for +5 volts input, J16
* default Shown below is a top view of the JP39 with silkscreen markings. JP39 VIN_SEL EXT BAT 1-2 BAT 2-3 5V EXT BAT 1-2 BAT 2-3 5V JP39 VIN_SEL Factory Setting
1-2 Position 2-3 Position Figure 2-21, Top View of the Jumper JP39
2-28

2.5.2 C5515 EVM Power Domain Probe Points The C5515 EVM has pre-designed probe points in the circuitry which could be used to observe power domains. Several of the power domains have INA219 power monitors and these domains have a 1 ohm resistor shunted on the EVM. The probe points with power monitors are shown in the table below. Table 27: C5515 EVM Power Probe Points With Power Monitors
JP8 / 11 JP17 / 11 JP20 / 15 JP22 / 13 JP23 / 15 JP25 / 15 JP37 / 11 JP38 / 11
Signal
# of Positions
1 Ohm Shunt Resistor Installed at factory

Monitor Monitor Monitor Monitor Monitor - 0 Monitor Monitor Monitor
TPS65023_VCC_1V8 C5515 VDD_IO1 V1.8 VIN_EVM VDD_IO2 V3.3 VDDC USB_VDD_IN
2 2 2 2 2 2 2 2
Shown below is a diagram of a typical Power Domain Probe Point with a one (1) ohm resistor.
One (1) ohm resistor Figure 2-22, Diagram of a typical jumper
2-29

The remaining pre-configured power probe points are shunted with zero (0) ohm resistors as shown below. Table 28: C5515 EVM Power Probe Points With 0 Ohm Resistors
JP7 / 19 JP13 / 2 JP14 / 19 JP19 / 10 JP21 / 15 JP24 / 15 JP26 / 15 JP40 / 19
Signal
# of Positions
0 Ohm Shunt Resistor Installed at factory

Yes Yes Yes Yes Yes Yes Yes Yes
AIC HPVDD C5515 VDDIO4 AIC IOVDD USB_VDDA3P3 V1.3 VDD_IO1 CPU_VCC_CORE AIC AVDD
2 2 2 2 2 2 2 2
Shown below is a diagram of a typical Power Domain Probe Point with a zero (0) ohm resistor.
Zero (0) ohm resistor Figure 2-23, Diagram of a typical jumper
2-30

2.6 Test Points The C5515 EVM has forty-one (41) test points. The position of these test points on the top side of the C5515 EVM are shown in the figures below.
TP1 TP21 TP17 TP4 TP2 TP3
TP5
TP6 TP10 TP11 TP14 TP15 TP16 TP19 TP22 TP20 TP25 TP26 TP27 TP24 TP23 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP8 TP12 TP18 TP7 TP9
Figure 2-24, TMS320C5515 EVM Test Points (Top)
2-31

Figure below shows the location of test points on the bottom side of the C5515 EVM.
TP41 TP40
TP39 TP38
TP36
TP35 TP37
Figure 2-25, TMS320C5515 EVM Test Points (Bottom)
2-32

The table below shows the signals present on each user test point. Table 29: C5515 EVM User Test Points
Test Point #
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34
Signal
GND nRESET WAKUP XF AIC_GPIO INT1 INT0 RTC_CLKOUT CLKOUT GND USB_3.3V GPIO5 GND VBUS TPS65023_VCC_3V3 V_PWR_MON MMC0.WP INTn LOWBATn MMC0.INS VPWR_IN GND PWRFAILn PWRFAIL_SNS LOWBAT_SNS VBATOUT GND GND +5V Input Battery + Battery GND
Schematic Page #
11 12 2 2 19 2 2 2 3 15 27 18 19 3 15 15 16 14 14 16 13 17 14 14 14 13 18 13 13 13 13 3
2-33

The table below shows the signals present on each test point used exclusively by the factory. Table 30: C5515 EVM Factory Test Points
Test Point #
TP10 TP11 TP35 TP36 TP37 TP38 TP39 TP40 TP41
Signal
USB_1.6V USB_3.3V GPIO_1 GPIO_0 CLKOUT ODEMU1n ODEMU0n TCKR USB_2.5V
Schematic Page #
27 27 24 24 23 24 24 24 27
2-34
Appendix A Schematics
This appendix contains the schematics for the TMS320C5515 EVM. Board components with designators over 200 (e.g. DS210, R211) are part of Spectrum Digitals embedded JTAG emulator and are not included in these schematics.
A-1
A-2
REV
A B
2
NOTES, UNLESS OTHERWISE SPECIFIED:

Initial schematic for layout Update TPS65023 Enable Logic 12/15/2009 RRP 10/15/2009 RRP
DESCRIPTION
DATE
APPROVED
1.
RESISTANCE VALUES IN OHMS.
2.
CAPACTITANCE VALUES IN MICROFARADS.
3.
REFERENCE DESIGNATORS USED:
4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATED CIRCUITS THEY SHOULD BE PLACED NEAR.
Schematic Contents
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 1617 18 19 20 -
TITLE PAGE TMS320C5515 GPIO / MMC / SPI / I2C TMS320C5515 CLOCKS / JTAG / USB EMULATION - JTAG CC Board Interface TMS320C5515 EMIF Mobile DRAM Interface NAND Flash Interface NOR Flash Interface TMS320C5515 Power CPU Decoupling Caps RESET Power Input TPS65023 Power Management POWER Router MMC / SD UART / EEPROMs SAR Resistor Network CODEC COLOR LCD INTERFACE
REVISION STATUS OF SHEETS
REV DWN R.R.P. T.W.K. R.R.P. R.R.P. C.M.D. R.R.P. R.R.P.

4
SHEET CHK ENGR ENGR-MGR A QA MFG NEXT ASSY RLSE APPLICATION USED ON 17 A A A 10 9 7 8 A 18 19 20 A A A
REV
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size:B Date:

3 2
SHEET
TMS320C5515 EVALUATION MODULE TITLE SHEET DWG NO 512702-0001 Monday, February 01, 2010
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REV
SHEET
11
12
13
14
15
16
REV
Revision: B Sheet 1 of 20
SHEET
DATE 10/15/2009 DATE 10/15/2009 DATE 10/15/2009 DATE 10/15/2009 DATE 10/15/2009 DATE 10/15/2009 DATE 10/15/2009
VDD_IO1 U13A 18 18 18 18 R204 C50 1uF C135 0.1uF GP[4] GP[5] R47 R51 R215 GP[6] GP[7] GP[8] GP[9] GPAIN3 GPAIN2 GPAIN1 GPAIN0
JP13
NO-POP 1
VDDIO4
PWR JP
GPAIN3 GPAIN2 GPAIN1 GPAIN0
GP[0] GP[1] GP[2] GP[3]
R43 R34 R31 R28 0 0 0 0
0 0 0 0
ADS_GPIO0 ADS_GPIO1 ADS_GPIO2 ADS_GPIO3 GPIO4 5 ADS_GPIO4 18 ADS_GPIO5 18
18 18 18 18
R193
R120 SW2
ADC
JP5
MMC0_CLK/I2S0_CLK/GP[0] MMC0_CMD/I2S0_FS/GP[1] MMC0_D0/I2S0_DX/GP[2] MMC0_D1/I2S0_RX/GP[3] MMC0_D2/GP[4] DVDDIO MMC0_D3/GP[5]
L10 M11 L9 M10 L12 L11

MMC0_CLK 16 MMC0_CMD 16 MMC0_DATA0 16 MMC0_DATA1 16 MMC0_DATA2 16 MMC0_DATA3 16
GP[0] GP[1] GP[2] GP[3] GP[4] GP[5]
GPIO5
10K
C11 B11 A11 D10 GPAIN3 GPAIN2 GPAIN1 GPAIN0 1 2

C93 0.1uF TP8 RTC_CLKOUT RTC_CLKOUTD8
1 2 3 3 4 Wakeup F8 DVDDRTC RTC_CLKOUT WAKEUP

5 5 5 5
VDDA_ANA
MMC1_CLK/I2S1_CLK/GP[6] MMC1_CMD/I2S1_FS/GP[7] MMC1_D0/I2S1_DX/GP[8] MMC1_D1/I2S1_RX/GP[9] MMC1_D2/GP[10] DVDDIO MMC1_D3/GP[1]1 M13 L14 M14 M12 K14 L13
MMC1_CLK 5 MMC1_CMD 5 MMC1_DATA0 MMC1_DATA1 MMC1_DATA2 MMC1_DATA3 GP[6] GP[7] GP[8] GP[9] GP[10] GP[11]
WAKEUP_PU-PD_SEL
R112
R196 R287 R46 R288 R202 R191
0 0 0 0 0 0
10K 5 RTC_CLKOUT WAKEUP
TP3 WAKEUP
I2S1_CLK 18 MMC0.WP 16 I2S1_FS 18 MMC0.INS 16 I2S1_DX 18 I2S1_RX 18 GP[6] GP[7] GP[8] GP[9] R39 R205 R42 R36 0 0 0 0
E8
I2S1_CLK_CC 5 I2S1_FS_CC 5 I2S1_DX_CC 5 I2S1_RX_CC 5
DVDDRTC
VDD_IO1 R20 R14 100K 100K
TP7 INT0
TP6 INT1
LCD_D[0]/SPI_RX LCD_D[1]/SPI_TX LCD_D[2]/GP[12] LCD_D[3]/GP[13] LCD_D[4]/GP[14] LCD_D[5]/GP[I5] LCD_D[6]/GP[16] LCD_D[7]/GP[17]
P6 N6 P7 N7 N8 P9 N9 P10
LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7
20 20 20 20 20 20 20 20
R208 GP[10] R50 GP[11] R37
0 AIC_RST 0 ADS_GPIO10 0 GPIO11
AIC_RST 19 ADS_GPIO10 18 GPIO11 18

C
18 INT1 13 INT0 12,19,20 nRESET
E7 C6 D6 M8 INT1n INT0n RESETn XF
LCD_DATA8 19 LCD_DATA9 19 LCD_DATA10 19 LCD_DATA11 19
R195 LCD_RE LCD_RE
0 GPIO11_LCD_PWR R13 LCD_MCLK R12 0 0
GPIO11_LCD_PWR 20 SPI_ALT_CLK 5
DVDDIO
LCD_EN_RDB/SPI0_CLK N3
R124 XF
1K
D2
LCD_D[8]/I2S2_CLK/GP[18]/SPI_CLK LCD_D[9]/I2S2_FS/GP[19]/ SPI_CS0 LCD_D[10]/I2S2_RX/GP[20]/SPI_RX LCD_D[11]/I2S2_DX/GP[27]/SPI_TX LCD_D[12]/UART_RTS/GP[28]/I2S3_CLK LCD_D[13]/UART_CTS/GP[29]/I2S3_FS LCD_D[14]/UART_RX/GP[30]/I2S3_RX LCD_D[15]/UART_DX/GP[31]/I2S3_DX
N10 P11 N11 P12 N12 P13 N13 P14
TP4 XF
C13 C14 RSV5_(GND) RSV4_(GND)
SPI_ALT_CS1 5 LCD_RE 20 LCD_BIAS_OE 20 LCD_nWE 20 LCD_ALE 20 LCD_DATA0 R16 0 SPI_ALT_RX 5 LCD_DATA1 R18 LCD_DATA2 R22 0 0 GPIO12 LCD_DATA3 R25 LCD_DATA4 R289 0 GPIO13 0 GPIO14_CC LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 SPI_ALT_DX 5 GPIO12 5 GPIO13 5 GPIO14_CC 5
18 XF VDD_IO1
I2C
B8 B7 SDA SCL
LCD_CS0_E0/SPI_CS0 LCD_CS1_E1/SPI_CS1 LCD_RW_WRB/SPI_CS2 LCD_RS/SPI_CS3
P4 N4 P5 N5
LCD_BIAS_OE LCD_MCLK LCD_nWE LCD_ALE
R19 10K 10K TMS320C5515
R26
DVDDIO
DVDDIO
I2C_SDA I2C_SCL
I2S2_CLK 19 I2S2_FS 19 I2S2_RX 19 I2S2_DX 19 LCD_DATA8 LCD_DATA9 LCD_DATA10 R24 R29 R27 LCD_DATA11 R32 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 R30 R35 R33 R40 0 0 0 0 SPI_CLK SPI_CS0 SPI_RX SPI_DX 0 UART_RTS 0 UART_CTS 0 UART_RX 0 UART_TX SPI_CLK 17,18 SPI_CS0 17,18 SPI_RX 17,18 SPI_DX 17,18 UART_RTS 5,17 UART_CTS 5,17 UART_RX 5,17 UART_TX 5,17
J6
5,14,15,17,18,19 I2C_SDA 5,14,15,17,18,19 I2C_SCL
1 2 3
I2C Probe Point Headers
HEADER 3

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Revision: A Sheet 2 of 20
A-3
L7 TDI TDO TCK RTCXI EMU0 EMU1 VSS_RTC C9 B9 M7 M6

R23 0
Oscillator Socket
A-4
CPU_3V3_USB FB6
1 2 BLM21PG221SN1D
C57 10uF 0.1uF 1000pF C152 C169
AGND U13D
TP16 VBUS
D
C47 33pF Y2 12.000MHz R49 NO-POP 0
R56
USB_XI
G12 USBVDD_OSC USB_VBUS G13 USB_MXI USB_DM USB_DP USB_MXO USB_VSSOSC

100K
J12 S1 J14 H14

USB_DM USB_DP
USB_VBUS
J11
C48 33pF 0
R57
USB_XO
G14 F11 USB_R1 USB_VSSREF G10

10K 1%
1 2 3 4 VBUS DD+ GND

C58 10uF R236 C177 0.1uF
S2 G9
USB_R1
D3 R201 6.2V
USB-B connector V1.3
USBVDD_OSC
TP9 NC-CLKOUT
R117
JP4 0 0
A7 CLKOUT CLKIN CLK_SEL

R116
V3.3 P OP
CLKOUT
Place as close as possible to Y2
A8 1 C7
VDD_IO1
CLK_SEL
R189 0 OSC_V 10K R157
CLKIN JP9 2
1 2 3
C99 1uF R113 NO-POP NO-POP
VDDC
C
DVDDIO
M9 CVDDRTC TRSTN TMS RTCXO A9
R179 0
R55 NO-POP
R217 NO-POP
C8
C31 33pF
C161 0.01uF R210 OSC1 47K
C162 1uF
L8
3 2
32.768KHz Y1 C39 33pF
R199
33
8 7 6 5 VCC_8 NC-7 NC-6 OUT L6 M5 OE_8 NC-2 NC-3 GND
1 2 3 4
R207 10K
R54 0 V3.3 TMS320C5515
DVDDIO
CVDDRTC
TP34
R174 R168 U11 10K 100 VDD_IO1 GND

PLACE CLOSE TO TCK PIN
VCCB
C130
6 4
15pF
1 5 3 2 VCCA DIR A GND B

SN74AVC1T45
DIR=H : A to B DIR=L : B to A
TARGET_EMU1 4 TARGET_EMU0 4 TARGET_TCK 4 TARGET_TDO 4 TARGET_TDI 4 TARGET_TMS 4 TARGET_TRSTn 4 SPECTRUM DIGITAL INCORPORATED Title: AUDIO_MCLK 19 Page Contents: Size:B Date:
4 3 2 A
TMS320C5515 EVALUATION MODULE CLOCK,JTAG,USB DWG NO 512702-0001 Wednesday, February 03, 2010
1
VDD_IO1 VDD_IO1 R176 R200 1K TARGET_TRSTn J8 10K TARGET_TMS TARGET_TDI TARGET_TDO TARGET_TCK R211 0 R222 100K TARGET_EMU0 TARGET_TRSTn 3 TARGET_TMS 3 TARGET_TDI 3 TARGET_TDO 3 TARGET_TCK 3 TARGET_EMU0 3
D
R185 NO-POP
NO-POP R48 R175 10K
USBSEL - HIGH, SELECT EMBEDDED EMULATION
USBSEL - LOW, SELECT EXTERNAL XDS EMULATION
C45 100nF R220 100K
2 4 6 8 10 12 14 nTRST TMS 4 TDI 6 K Vcc ey 8 TDO 10 RTCK 12 TCK EMU1 EMU0 JTAG
1 3 5 7 9 11 13
3V3_EMU
R216
REMOVE IF USING BOARD ON QUICKTURN
TARGET_EMU1 VDD_IO1
10K 3V3_EMU
TARGET_EMU1 3
EMBED_EMU_SELn
G 4 5 1A1 1A2 2A1 2A2 6 7

3V3_EMU R233 10K EMBED_EMU_XRSp 12 EMBED_EMU_SELn
Q3 BSS138
C174 0.1 uF
U22
1 VCCA
VCCB 1B1 1B2 2B1 2B2
16 13 12 11 10
R232 R230 R228 R225
C175 0.1 uF
C
33 33 33 33
2 15 3 14
1DIR 1OEn 2DIR 2OEn GND.1 GND.2 8 9
DIR AND OEn ARE ON A POWER DOMAIN OEn L L DIR L H FUNCTION B->A B<-A
R229 SN74AVC4T245PWRE4 USB1_1 3V3_EMU VDD_IO1 33
EMBED_EMU_XRSp
DSP_RS_OUTp
C163 0.1 uF R213 R214 33 33
U19
1 4 5
VCCA 1A1 1A2 6 7

R212 0
VCCB 1B1 1B2 2A1 2A2 2 15

EMBED_EMU_SELn
16 13 12
C167 0.1 uF
R221 NO-POP
3V3_EMU
T_TRSTn T_TMS T_TDI T_TCK T_TCK_RET T_TDO T_EMU0 T_EMU1 3V3_EMU
T_TRSTn T_TMS T_TDI T_TCK T_TCK_RET T_TDO T_EMU0 T_EMU1
2B1 2B2 1DIR 1OEn 3 14 2DIR 2OEn GND.1 GND.2
11 10
G ND
GND
VDD_IO1
8 9
OEn L L
DIR L H
FUNCTION B->A B<-A
T_PWRLOSSn
SN74AVC4T245PWRE4 SPECTRUM DIGITAL INCORPORATED

A
Embedded_USB
Title: Page Contents: Size:B Date:

4 3 2
TMS320C5515 EVALUATION MODULE JTAG INTERFACE DWG NO 512702-0001 Monday, February 01, 2010
1
A-5
A-6
4 3 2 1
NOTE: DIMENSIONS AND LOCATIONS OF THESE CONNECTORS
MUST MEET SPECIFICATION FOR INTERFACE MODULES
P2 P1
V3.3 2 I2S1_FS_CC 2 GPIO12 2 GPIO14_CC 2 I2S1_CLK_CC UART_CTS 2,17 GPIO13 2
I2S1_DX_CC 2 I2S1_RX_CC 2
C
2,17 UART_RTS 2 RTC_CLKOUT 2,17 UART_RX 2,17 UART_TX 2,14,15,17,18,19 I2C_SDA 2,14,15,17,18,19 I2C_SCL 2 MMC1_CLK 2 MMC1_CMD GPIO4 GPIO5
1 3 5 7 9 11 13 15 17 19
MMC1_DATA0 2 MMC1_DATA1 2 MMC1_DATA2 2 MMC1_DATA3 2 GPIO4 2 GPIO5 2 SPI_ALT_CS1 2 SPI_ALT_CLK 2 SPI_ALT_DX 2 SPI_ALT_RX 2
2 4 6 8 10 12 14 16 18 20
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
HEADER 10X2 HEADER 10X2
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date:

4 3 2
TMS320C5515 EVALUATION MODULE CC BOARD INTERFACE DWG NO 512702-0001 Monday, February 01, 2010
1
RN5 A15 A14 A10 A13 A11 A12 A9 CPU_A15 CPU_A14 CPU_A10 CPU_A13 CPU_A11 CPU_A12 CPU_A9 CPU_A20 CPU_A19 CPU_A18 CPU_A17 CPU_A16 CPU_A15 CPU_A14 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CPU_SDRAS CPU_SDCAS CPU_SDCLK CPU_SDCKE R151 R152 R159 R158 0 22 22 22 SDRAS SDCAS SDCLK SDCKE
RPACK8-22
U13C
9 9 7,9 9 7,8,9 8,9 7,9
A15 A14 A10 A13 A11 A12 A9
8 7 6 5 4 3 2 1 J3 G4 G2 F2 E2 N1 M1 EM_A[20]/GP[26] EM_A[19]/GP[25] EM_A[18]/GP[24] EM_A[17]/GP[23] EM_A[16]/GP[22] EM_A[15]/GP[21] EM_A[14] EM_A[13] EM_A[12]/(CLE) EM_A[11]/(ALE) EM_A[10] EM_A[9] EM_A[8] EM_A[7] EM_A[6] A6 B4 M3 N2 B3 A4 P1 B5 EM_DQM1 EM_DQM0 EM_R/Wn EM_WEn EM_OEn
9 EM_WAIT2 8 EM_WAIT4
9 10 11 12 13 14 15 16 EM_D[15] EM_D[14] EM_D[13] EM_D[12] EM_D[11] EM_D[10] EM_D[9] EM_D[8] EM_D[7] EM_D[6] EM_D[5] EM_D[4] EM_D[3] EM_D[2] EM_D[1] EM_D[0] H3 K5 M2 L4 D4 F3 E5 G3
RPACK8-22 9 10 11 12 13 14 15 16 CPU_A8 CPU_A20 CPU_A7 CPU_A19 CPU_A18 CPU_A17 CPU_A6 CPU_A16 CPU_A13 CPU_A12 CPU_A11 CPU_A10 CPU_A9 CPU_A8 CPU_A7 CPU_A6
J4 K3 K4 L3 C4 D3 F4 E3
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7,9 7,9 7,9 7,9 7,9 7,9 7,9 7,9 7,8,9 7,8,9 7,8,9 7,8,9 7,8,9 7,8,9 7,8,9 7,8,9
RN6 A8 A20 A7 A19 A18 A17 A6 A16
7,9 9 7,9 9 9 9 7,9 9 RN7
A8 A20 A7 A19 A18 A17 A6 A16
8 7 6 5 4 3 2 1
L1 K1 K2 L2 J2 J1 H2 F1
SDRASn SDCASn EM_SDCLK SDCKE SD_CE0n SD_CE1n
SDRAS 7 SDCAS 7 SDCLK 7 SDCKE 7 CPU_SDCE0 R150 R283 CPU_DQM1 CPU_DQM0 R119 R118 22 SD_CEXn NO-POP 22 22 DQM1 DQM0 SD_CEXn 7 DQM1 DQM0 7 7
7,9 7,9 7,9 7,9 7,9 7,9 7,9 7,9
A2 A5 A3 A4 A0 A1 BA0 BA1
A2 A5 A3 A4 A0 A1 BA0 BA1
8 7 6 5 4 3 2 1
RPACK8-22 9 10 11 12 13 14 15 16 CPU_A2 CPU_A5 CPU_A3 CPU_A4 CPU_A0 CPU_A1 CPU_BA0 CPU_BA1
CPU_A5 CPU_A4 CPU_A3 CPU_A2 CPU_A1 CPU_A0 CPU_BA1 CPU_BA0
D1 C1 D2 E1 C2 B2 B1 A1 EM_A[5] EM_A[4] EM_A[3] EM_A[2] EM_A[1] EM_A[0] EM_BA[1] EM_BA[0]
B6 H1 E4
CPU_RnW CPU_WE CPU_OE R156 R155 R153 22 22 22 WE OE EM_CS2n WE OE 7,8,9 8,9 EM_CS2n 9
EM_WAIT2 EM_WAIT3 EM_WAIT4 EM_WAIT5
D5 K6 G1 H4 EM_WAIT2 EM_WAIT3 EM_WAIT4 EM_WAIT5
R17 10K
R15 10K
DVDDEMIF
TMS320C5515
EM_CS2n EM_CS3n EM_CS4n EM_CS5n
C5 M4 C3 A3
CPU_EM_CS2n CPU_EM_CS3n CPU_EM_CS4n CPU_EM_CS5n
R154
22
EM_CS4n
EM_CS4n 8
B

4 3 2
TMS320C5515 EVALUATION MODULE TMS320C5515 EMIF DWG NO 512702-0001 Monday, February 01, 2010
1
A-7
A-8
4 3 2 1
U4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

RN1
6,9 6,9 6,9 6,9 6,9 6,9 6,9 6,9 6,9 6,9 6,9 6,8,9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
H7 H8 J8 J7 J3 J2 H3 H2 H1 G3 H9 G2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 CLK 1 2 3 4 5 6 7 8

D0 D1 D2 D3 D4 D5 D6 D7 6,8,9 6,8,9 6,8,9 6,8,9 6,8,9 6,8,9 6,8,9 6,8,9
A8 B9 B8 C9 C8 D9 D8 E9
SDRAM_D0 SDRAM_D1 SDRAM_D2 SDRAM_D3 SDRAM_D4 SDRAM_D5 SDRAM_D6 SDRAM_D7
RN2 SDRAM_D0 SDRAM_D1 SDRAM_D2 SDRAM_D3 SDRAM_D4 SDRAM_D5 SDRAM_D6 SDRAM_D7
RPACK8-10 D0 16 D1 15 D2 14 D3 13 D4 12 D5 11 D6 10 D7 9
6,9 6,9 6 SDCLK SDCLK
BA0 BA1
BA0 BA1
G7 G8 F2
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
E1 D2 D1 C2 C1 B2 B1 A2 1 2 3 4 5 6 7 8
D8 D9 D10 D11 D12 D13 D14 D15 6,9 6,9 6,9 6,9 6,9 6,9 6,9 6,9
RPACK8-10 D8 16 D9 15 D10 14 D11 13 D12 12 D13 11 D14 10 D15 9
VDD_IO2
6 SDCAS 6 SDCKE 6 DQM1 6 DQM0 6 SDRAS 6,8,9 WE 6 SD_CEXn
SDCAS SDCKE DQM1 DQM0 SDRAS WE SD_CEXn
F7 F3 F1 E8 F8 F9 G9 CAS CKE DQMH DQML RAS WE CS NC1 NC2 G1 E2
+C87
C90 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C89
C98
C94
C88
C101
C97
4.7uF
A9 E7 J9 A7 B3 C7 D3 VCC1 VCC2 VCC3 VCCQ1 VCCQ2 VCCQ3 VCCQ4 VSSQ1 VSSQ2 VSSQ3 VSSQ4
MT48H4M16LF
A3 B7 C3 D7 VSS1 VSS2 VSS3
A1 E3 J1

4 3 2
TMS320C5515 EVALUATION MODULE MOBILE SDRAM DWG NO 512702-0001 Monday, February 01, 2010
1
VDD_IO2
C78 C82 U2A U2B 0.1uF 0.1uF R104 10K C86 10uF
6 EM_WAIT4 6,9 OE 6 EM_CS4n VDD_IO2 10K A12 A11 CLE ALE R107
A3 A6 B2 A4 Vss.1 R/B RE CE G4 H6 F6 H1 Vcc Vss.2 CLE ALE WE WP I/O3 I/O2 I/O1 I/O0 H3 H2 G2 F2
D3 D2 D1 D0 6,7,9 6,7,9 6,7,9 6,7,9 D3 D2 D1 D0
I/O7 I/O6 I/O5 I/O4
G6 H5 G5 H4
D7 D6 D5 D4 6,7,9 6,7,9 6,7,9 6,7,9
D7 D6 D5 D4
43.N.C. 42.N.C. 41.N.C. 40.N.C. 39.N.C. 38.N.C. 37.N.C. 36.N.C. 35.N.C. 34.N.C.
G3 G1 F5 F4 F3 F1 E6 E5 E4 E3
VccQ Vss.3
1 2 3 4 5 6 7 8 9 10 11
B3 A2 A5 A1
K9F1208R0C-JIB0
K9F1208R0C-JIB0
NAND
12 13 14 15 B1 B4 B5 B6 C1 C2 C3
N.C.12 N.C.13 N.C.14 N.C.15 N.C.16 N.C.17 N.C.18 N.C.19 N.C.20 N.C.21 N.C.22
6,9 6,7,9 6,7,9
A12 A11 WE
N.C.1 N.C.2 N.C.3 N.C.4 N.C.5 N.C.6 N.C.7 N.C.8 N.C.9 N.C.10 N.C.11
33.N.C. 32.N.C. 31.N.C. 30.N.C. 29.N.C. 28.N.C. 27.N.C. 26.N.C. 25.N.C. 24.N.C. 23.N.C.
E2 E1 D6 D5 D4 D3 D2 D1 C6 C5 C4

4 3 2
TMS320C5515 EVALUATION MODULE NAND FLASH DWG NO 512702-0001 Monday, February 01, 2010
1
A-9
A-10
4 3 2 1
U1
D
VDD_IO2
R101 NO-POP
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 WAIT F7

R103 NO-POP EM_WAIT2 6
F2 E2 G3 E4 E5 G5 G6 H7 E1 E3 F3 F4 F5 H5 G7 E7
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 6,7,8 6,7,8 6,7,8 6,7,8 6,7,8 6,7,8 6,7,8 6,7,8 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7,8 6,8 6 6 6 6 6 6 6 6 6,7
BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 BA0
BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 BA0
A1 B1 C1 D1 D2 A2 C2 A3 B3 C3 D3 C4 A5 B5 C5 D7 D8 A7 B7 C7 C8 A8 G1 H8 B6 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 NC/A24 NC/A25 VPP
R105 10K C76 .1uF C77 .1uF C81 .1uF C84 .1uF
A4
VDD_IO2
6 EM_CS2n 6,8 OE
EM_CS2n
B4 F8 CE OE WE RSTn WPn CLK ADV G8
VCC.1 VCC.2 VCCQ.1 VCCQ.2 VCCQ.3
H3 A6 D5 G4 D6
6,7,8 12 1V8_SYS_RESETz VDD_IO2 FLASH_WPn 1V8_SYS_RESETz
WE
D4 C6 E6 F6 RFU.1 RFU.2 RFU.3 RFU.4 RFU.5 PC28F128P30T85
VSS.1 VSS.2 VSS.3 VSS.4
B2 H4 H2 H6
R106 0
F1 H1 G2 B8 E8

4 3 2
TMS320C5515 EVALUATION MODULE NOR FLASH DWG NO 512702-0001 Monday, February 01, 2010
1
VDD_SAR FB3 R223 0
A
C134 0.01uF C55 10uF PLL C151 0.1uF C171 1000pF U13B R282 NO-POP
1 2 B 3 C
JP18 NO-POP
V3.3 FB8
1 2 BLM21AG151SN1D
JP19 NO-POP
CPU_3V3_USB
PWR JP
1 2 BLM21PG221SN1D
V1.3 V1.8 LDO_IN LDO_IN R194 0
R231
VDDA_PLL H12 USB_VDDA3P3 LDOI.2

FB10
VSSA_PLL F14 E10 D13 D12

LDO_EN RSV6 DSP_LDO1.3 DSP_LDO_OUT LDO_IN
D9 2
C155 0.1uF R182 NO-POP DSP_LDO_OUT
A B 3 C
1
JP11 NO-POP
DSP LDOI SEL
C10
USB_VDD_IN
H11 USB_VSSA3P3 RSV6

C53 C139 C173
DSP_LDOO
1 2 BLM21PG221SN1D H10 USB_VDDA1P3 DSP_LDO_EN

1uF 0.1uF 0.01uF
V3.3
VDDC
H9
AGND FB9 AGND
USB_VSSA1P3
1 2 BLM21PG221SN1D J13 USB_VDD1P3

C54 10uF 0.1uF 1000pF C150 C172
CVDD.1 CVDD.2 CVDD.3 CVDD.4 CVDD.5 RSV1(CVDD) RSV2(CVDD)

R181
F6 H8 J6 K10 L5 J11 J10
0 LDO_IN DC_VDD_IO1 R234 DC_VDD_IO1 0
CPU_3V3_USB AGND AGND
H13 USB_VSS1P3
FB7
1 2 BLM21PG221SN1D USB_VDDPLL
C56 10uF 0.1uF 1000pF C137 C170
100K
100K
100K
G8
DVDDIO.1 DVDDIO.2 DVDDIO.3 DVDDIO.4 DVDDIO.5 DVDDIO.6
F7 K7 K12 N14 P3 P8
R64
R66
DC_VDD_IO2 POR_BGRST LDO_EN PM_CTL RSV6
LDO_IN AGND LDO_IN AGND
F13 LDOI.3
C154 USB_LDO_OUT 0.1uF LDO_IN LDO_IN
A B
F12 USB_LDOO
DVDDEMIF.1 DVDDEMIF.2 DVDDEMIF.3 DVDDEMIF.4 DVDDEMIF.5 DVDDEMIF.6 DVDDEMIF.7 DVDDEMIF.8 DVDDEMIF.9
A2 A5 E6 F5 G5 H5 H7 J5 P2
DC_VDD_IO2 R285
SAR LDOI SEL
USB_LDO_OUT
JP6 JUMPER 2
R65
G11 USB_VSSPLL
R67 100K
R286 0
R284 0
B12 LDOI.1 ANA_LDO (RSV0)POR_BGRST (RSV3)PM_CTL VDDA_ANA

SAR_LDO12 SAR_LDO12
C147 0.1uF
A12 C12 D14 A10
VDD_SAR DC_VDD_SAR
POR_BGRST PM_CTL
DSP_LDO_EN: If high, the DSP_LDOO is tri-stated If low, the DSP_LDOO is 1.3V or 1.05V depending on DSP_LDO_V
C51 1 uF C158 0.1uF 0.1uF
C142
B13
BG_CAP
SAR_LDO12
B10 B14
VSSA_ANA.1 VSSA_ANA.2
TMS320C5515 FB5 FB2
VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSS.6 VSS.7 VSS.8 VSS.9 VSS.10 VSS.11 VSS.12 VSS.13 VSS.14 VSS.15 VSS.16 VSS.17 VSS.18 VSS.19 VSS.20 VSS.21
A13 A14 D7 D11 E9 E11 E12 E13 E14 F9 F10 G6 G7 H6 J7 J8 J9 K8 K9 K11 K13
SAR_LDO12 AGND R226
SPECTRUM DIGITAL INCORPORATED
JP16 NO-POP R218
1 2 BLM21AG151SN1D
AGND PLL
1 2 BLM21AG151SN1D
Title: Page Contents: Size:B Date: TMS320C5515 EVALUATION MODULE TMS320C5515 POWER DWG NO 512702-0001 Monday, February 01, 2010 Sheet 10 o f Revision: A 20
V1.3
PWR JP
NO-POP
A-11
VIN-
GND
A1 A0
SCL SDA
8 7
5 6
VIN-
VIN+
U3 INA219IDCN
GND
A1 A0
SCL SDA
VS
V_PWR_MON I2 C_SCL_PWR I2C_SDA_PWR
R108 0 DSP_LDO_OUT
VS
I
1
DSP_LDO_OUT
VIN+
R1
1 1%
2 B
JP1 NO-POP U7 INA219IDCN
VDDC
R102 NO-POP
8 7
5 6
1
R59 1 1%
2 2 B A 1
USB_LDO_OUT
R219 NO-POP
USB_LDO_OUT
VIN-
VIN-
VIN+
GND
U21 INA219IDCN V_PWR_MON
VIN+
U20 INA219IDCN
A1 A0
SCL SDA
8 7
5 6
GND
A1 A0
SCL SDA
8 7
5 6
VS
VS
A-12
DC_VDD_IO2 DC_VDD_ IO2 C22 C122 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.01uF 0.01uF 1uF 1uF 0.01uF 1uF 0.01uF C127 C148 C144 C132 C133 C116 C111 C106 C105 C109 C110 C113 C124 C118 C119 C129
D
VDDC
VD DC
C120
C125
1uF
0.01uF
DC_VDD_IO2 CPU_VCC_ CORE R146 1 1% JP37 1

NO-POP
JP8 1 TPS65023_VCC_1V8
NO-POP 2
V_PWR_MON
C102 0.1uF
C
C83 0.1uF DC_VDD_IO1 C46 10uF V1.3 JP38 JP15 NO-POP

NO-POP
DC_VDD_IO1
I2C_SCL_PWR I2C_SDA_PWR C153 0.1uF
C157 0.1uF
C160 0.1uF
C140 0.1uF
C141 0.1uF
C159 0.1uF
USB_VDD_IN DC_VDD_IO1 JP17 1 NO-POP 2 VDD_IO1
I
R227 0
R224
1 1%
B
V_PWR_MON
C165 0.1uF C166 0.1uF 13,15 I2C_SCL_PWR 13,15 I2C_SDA_PWR TP1 GND Title: Page Contents: Size: B Date:
4 3 2
V_PWR_MON
I2C_SCL_PWR I2C_SDA_PWR
I2C_SCL_PWR I2C_SDA_PWR
SPECTRUM DIGITAL INCORPORATED TMS320C5515 EVALUATION MODULE CPU DECOUPLING CAPS DWG NO 512702-0001 Monday, February 01, 2010
1
Revision: A Sheet 11 o f 20
VDD_IO1
D
R109 100K
14 PWR_RSTn
TP2 nRESET VDD_IO1 JP2
1 2 3
HEADER 3 R100 100K 14 PB_RESET C75 100nF C79 .1uF
nRESET 2,19,20
VDD_IO2 VDD_IO1
C80 .1uF U29
6 VCCA VCCB DIR A B GND SN74AVC1T45 4

1V8_SYS_RESETz 1V8_SYS_RESETz 9
1 5 3 2
VDD_IO1
R203 10K R183 33
D
EMBED_EMU_XRSp
G S
R198 10K
Q4 BSS138

4 3 2
TMS320C5515 EVALUATION MODULE RESET DWG NO 512702-0001 Monday, February 01, 2010
1
Revision: B Sheet 12 o f 20
A-13
J16 Power Jack
SMCJ06A
TP30
TP31
LEDRED
Max Input: 5VDC, 4 A. Use only recommended power supplies.

3 2 1 1 2 VIN+ VINU24 INA219IDCN V_PWR_MON
VS
SDA SCL
A0 A1
JP39 HEADER 3
6 5
7 8
V_PWR_MON C59 0.1uF TP28
GND
2 0
INT0
R254
17
PWR_PAD
A-14
4 3 2 1
SW5A TP23
V5
1
F1 VPWR_IN VIN_EVM D7
+ POP
2
FUSE_3A 470 D8 220uF JP22 2 C73
D
1
R95
1201M2S3AQE2
1
1 1%
R239
I2C_SCL_PWR 11,15 I2C_SDA_PWR 11,15
VBATOUT R88 U26
TPS61030-ADJ
9 EN VBAT 6
C190 0.1uF B+ TP32 L9 6.8uH 20% SW5B
18 Battery_Measurement
Battery Holder
1 2 SW1 SW2
R256 1M 1%
+
C72 R92 10uF 475K 1%
1 4 12
R261
VOUT15 VOUT14 VOUT13
15 14 13
C184 2.2uF
C67
+
B
1201M2S3AQE2
FB 7 LBI NC
R255 1M 1%
220uF
GND 16
R93 TP33 B182K 1% R91 0
180K 1%
J18
8 11 3 4 5 SYNC GND PGND3 PGND4 PGND5 LBO 10

4 3 2
TMS320C5515 EVALUATION MODULE POWER IN DWG NO 512702-0001 Monday, February 01, 2010
1
VIN_EVM
C66 10uF VIN_EVM TPS65023_VCC_1V8 0 L6 C185 0.1uF R79 NO-POP

+
R247 2.2uH
TP26 TP-60 TPS65023_VCC_3V3 TP27 TP-60 TP25 TP-60 R84 100K VRTC VRTC R245 1K
C181 22uF
41
40 39 38 37 36 35 34 33 32 31
U25
R70 4.7K
R69 4.7K
R71 10K
VIN_EVM
+
C68 10uF L7 L8 2.2uH 2.2uH
AGND1 LOWBAT_SNS PWRFAIL_SNS VCC VINDCDC2 L2 PGND2 VDCDC2 DEFDCDC2 PWRFAILn
PWR_PAD
C189 22uF
R258 22.1K
TP20 TP-60 R77 R76 NO-POP NO-POP
I2C_SDA 2,5,15,17,18,19 I2C_SCL 2,5,15,17,18,19 PWR_RSTn 12 VIN_EVM C60 0.001uF
VIN_EVM
TPS65023_VCC_CORE
+ +
C69 C188 22uF VIN_EVM VIN_EVM
1 2 3 4 5 6 7 8 9 10 DEFDCDC3 VDCDC3 PGND3 L3 VINCDDC3 VINDCDC1 L1 PGND1 VDCDC1 DEFCDCD1 HOT_RESETn DEFLDO1 DEFLDO2 VSYSIN VBACKUP VRTC AGND2 VLDO2 VINLDO VLDO1 SDAT SCLK INTn RESPWRONn TRESPWRON DCDC1_EN DCDC2_EN DCDC3_EN LDO_EN LOWBATn
29 30 28 27 26 25 24 23 22 21
10uF R85 100K 1%
R74 2K TP21 TP-60 TPS65023 TPS65023_LDO_1V3
R73 47K
R72 10K
11 12 13 14 15 16 17 18 19 20
V_CORE_SEL OFF = 1.05V ON = 1.30V default
R82 10K R259 243K 1% R257 130K 1%
R83 NO-POP
+
C64 22uF VIN_EVM TPS65023_LDO_VLDO2
C63 NO-POP
C62 0.1uF
C61 0.1uF
VDD_IO1_SEL OFF = 1.8V ON = 3.3V default
SW4
ON
R252 NO-POP
R251 10K
VIN_EVM VIN_EVM VRTC R81 NO-POP

+
R75 10K
1 2
4 3
C182 2.2uF C183 R80 0 R250 0 SPECTRUM DIGITAL INCORPORATED Title: TMS320C5515 EVALUATION MODULE Page Contents: Size: B Date: POWER MANAGEMENT DWG NO 512702-0001 Monday, February 01, 2010 Sheet 14 o f Revision: B 20
A
DIP_SWITCH_2
+ +
C65 10uF 2.2uF R78 NO-POP
VOUT = VDEFDCDC * (( R85 + R257eq)/R257eq ) . DEFLDO2 VDEFDCDC = 0.6 0 0 1 1 DEFLDO1 0 1 0 1 VLDO1 VLDO2 1.3 V 3.3 V 2.8 V 3.3 V 1.3 V 1.8 V 1.8 V 3.3 V
SW1 R3 33
3 4
1 2
RESET
PB_RESET 12
A-15
VS
SDA SCL
A0 A1
6 5
7 8
GND
V_PWR_MON
VIN+
VIN-
U27 INA219IDCN
VIN-
VIN+
VS
SDA SCL
A0 A1
GND
6 5
7 8
A-16
JP25 2
NO-POP
TPS65023_VCC_3V3
VDD_IO1 Power Supply

V3.3 VDD_IO1 V1.3 TPS65023_LDO_VLDO2 JP24 NO-POPPOP 2 1 TPS65023_LDO_1V3 JP21 NO-POP
1
R265
1 1%
2
R237 0
R241
C191 0.1uF V_PWR_MON
I2C_SCL_PWR I2C_SDA_PWR JP26

NO-POP
TPS65023_VCC_1V8
JP23
NO-POP
2 1
VDD_IO2 0 R264 TPS65023_VCC_CORE CPU_VCC_CORE R238
VDD_IO2 Power Supply

V_PWR_MON V_PWR_MON JP20
NO-POP
2
V1.8 2.2K R235 11,13 I2C_SCL_PWR 11,13 I2C_SDA_PWR I2C_SDA_PWR I2C_SCL_PWR
R137
R145 2.2K
1 1%
J3 2,5,14,17,18,19 I2C_SDA 2,5,14,17,18,19 I2C_SCL R133 R147 0 0
U23 INA219IDCN
V_PWR_MON
1 2 3
HEADER 3
Power Monitor I2C Probe Point Headers
C179 0.1uF V_PWR_MON V_PWR_MON R68 I2C_SCL_PWR I2C_SDA_PWR 0

+
TP18 Test Point_1
TP17 Test Point_1
TPS65023_VCC_3V3
TP12 GND SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date: TMS320C5515 EVALUATION MODULE POWER ROUTER DWG NO 512702-0001 Monday, February 01, 2010 Sheet 15 o f Revision: A 20
A
C178 33uF

4 3
VDD_IO1
VDD_IO1
R290 10K 10K 10K 10K MMC0.WP 2
10K 10K
NO-POP
R240 R242
R248
R262 R263 R266
J15
TP19 TP22
2 MMC0_DATA2 2 MMC0_DATA3 2 MMC0_CMD
WP COM CARD_DETECT
WP CO CD
MMC0.WP MMC0.INS
C
2 MMC0_CLK 2 MMC0_DATA0 2 MMC0_DATA1
R293 1K R291 VDD_IO1 10K MMC0.INS 2
9 1 2 3 4 5 6 7 8 DAT2 DAT3 CMD VSS1 VDD CLK VSS2 DAT0 DAT1
C187
+
MMC/SD_CARD C186 0.1uF
10uF

4 3 2
TMS320C5515 EVALUATION MODULE MMC/SD SOCKETS DWG NO 512702-0001 Monday, February 01, 2010
1
A-17
1 6 2 7 3 8 4 9 5
A-18
4 3 2 1
TP24 GND VDD_IO1 VDD_IO1 R2 U5 R121 10K

UART_EN
CTS RXD RTS TXD
VDD_IO1
R125 10K
JP3 POP
10K
1 EN_L 17 8 15 10 11
CONNECTOR DB9
GND SHIELD
2 VCC
J1
1 19 13 12 16 9 T1IN T2IN R1IN R2IN 10 T1OUT T2OUT R1OUT R2OUT
2,5 UART_TX
I2S3_CLK
I2S3_DX
2,5 UART_RTS C95 0.1uF 0.1uF R5 C4 0.1uF 0.1uF 0.1uF C3 C92 C100
2 4 5 6 C1+ C1C2+ C2V+ VNC-1 NC-2 SHUTDOWN

10K MAX3222
3 7 14 11 20
18 GND
2,5 UART_CTS
I2S3_RX
I2S3_FS
2,5 UART_RX
256K-Bit I2C EEPROM

VDD_IO1 U6 R130 R129 R128 10K 10K 10K C91 0.1uF
B
1 2 3 4 A0 VCC A1 WP NC SCL VSS SDA 24WC256
8 7 6 5
2,5,14,15,18,19 I2C_ SDA 2,5,14,15,18,19 I2C_SCL 0 0
R114 R115
256K-Bit SPI EEPROM

VDD_IO1 U9 2,18 SPI_CS0
1 CS SIN SCLK GND

CAT25C256K
VCC HOLD WP SO 2 3
0.1uF
8 7
C115
2,18 SPI_DX 2,18 SPI_CLK
5 6 4
SPI_RX 2,18 Title: Page Contents: Size: B Date:
SPECTRUM DIGITAL INCORPORATED TMS320C5515 EVALUATION MODULE RS232(UART)/EEPROM DWG NO 512702-0001 Monday, February 01, 2010
3 2 1

4
LAYOUT NOTE: These 3 connectors need to be placed in specific coordinates to allow for Interfacing to the ADS Codec Daughter Card
V1.8 J14 J13
D
V3.3
J10 ADS_GPIO4 GPIO6 GPIO7 ADS_GPIO10 ADS_GPIO1 ADS_GPIO0 GPIO9 GPIO11
2 2 2 2 V5
R260 R249 R246 R243
NO-POP NO-POP NO-POP NO-POP
GPIO11 2 ADS_GPIO10 2 ADS_GPIO1 2 ADS_GPIO0 2 I2S1_RX 2
2 4 6 8 10
1 3 5 7 9
2 4 6 8 10 12 14 16 18 20
HEADER 5X2 GPIO8 ADS_GPIO3 HEADER 11x2 TP14 2 ADS_GPIO4 2,17 SPI_CLK 2 I2S1_CLK 2,17 SPI_CS0 2 I2S1_FS 2,17 SPI_DX 2,17 SPI_RX 2 INT1 2 XF 2 I2S1_DX 2 ADS_GPIO3
1 3 5 7 9 11 13 15 17 19
1 3 5 7 9 11 13 15 17 19 21
2 4 6 8 10 12 14 16 18 20 22
ADS_GPIO2
I2C_SCL 2,5,14,15,17,19 I2C_SDA 2,5,14,15,17,19 ADS_GPIO2 2
HEADER 10X2
ADS_GPIO5 GPIO5
ADS_GPIO5 2
TP29 VDD_SAR GND
R273 20k R253 GPAIN R272 24.9K 1% 5.36K 1% 5.49K 1% 6.34K 1% R280 R99 R98 R270 4.75K 1% R271 6.49K 1% R268 17.4K 1% R267 22.6K 1% R269 60.4K 1% 0
Remove R105 for Internal Voltage Measurement

C197 C196 0.1uF SW9 Shift SW13 STOP SW15 REC SW12 FWD NO-POP
SW11 PLAY
SW10 RWD
SW7 UP
SW14 DN
SW8 MODE
SW6 MENU
GPAIN Battery Measurement

2 GPAIN0
R89 0
13 Battery_Measurement SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date:

4 3 2 A
TMS320C5515 EVALUATION MODULE SAR RESISTOR NETWORK DWG NO 512702-0001 Monday, February 01, 2010
1
A-19
V1.8
6 29
R209 NO-POP 0 MIC1_IN C37 0.1uF nRESET 2,12,20 AIC_RST 2 R144 AIC_RST NO-POP TLV320AIC3204IRHBT GND-A R188 MIC_DET U12
24 26
IOVDD DVDD
10uF GND-A 1 2 GND-A
LEFT MIC
AVDD HPVDD
TP5
IOVSS AVSS DVSS
AIC_GPIO
2 4 5 3 1
C180 0.47uF
PPAD
7 17 28
33
A-20
FB11 1
2
PWRJP R292 0
JP40 1
NO-POP 2
BLM21AG151SN1D C17 22uF VDD_IO1 FB12 1 0.1uF 0.1uF 22uF C107 C117 C25
2
D
JP14 2 GND-A BLM21AG151SN1D C32 10uF V3.3A JP7 1 R186 R187 C108 C18 V3.3A 0.1uF 22uF R139 0 C44 2.2K 2.2K PWRJP NO-POP 2 0.1uF C126 PWRJP R192 0 JP12
Route all mic lines away from digital signals!
NO-POP 1
MIC_BIAS
3 2 1
Remove if not using with I2C
M1
RESET BCLK WCLK DIN DOUT

0 0 0 0
31
M2
+
1 2
GND-A C164 0.47uF C168 0.47uF R177 R180 0 0 I2C_SCL 2,5,14,15,17,18 I2C_SDA 2,5,14,15,17,18
MIC2_IN
C38 0.1uF
RIGHT MIC
AIC_MBIAS AIC_MIC1L AIC_MIC1R AIC_LINE2L AIC_LINE2R AIC_LINE3L AIC_LINE3R
19 13 14 15 16 20 21 MICBIAS IN1_L IN1_R IN2_L IN2_R IN3_L IN3_R 2 3 4 5

I2S2_CLK 2 I2S2_FS 2 I2S2_DX 2 I2S2_RX 2 AIC_IISCLK AIC_IISFS AIC_IISD0 AIC_IISD1 R161 R165 R169 R173 AUDIO_MCLK 3
J9
STEREO IN 1
30 32
GND-A C176 0.47uF VDD_IO1 V3.3
2 4 5 3 1 LDO_SEL GPIO REF
25 27 22 23 HPL HPR LOL LOR MCLK
SJ1-3515-SMT, 5PJACK STEREO
J12
18
SCL/SSZ SDA/MOSI SPI_SEL MISO SCLK/MIC_DET
9 10 12 11 8
STEREO IN 2
GND-A CONN_HP_LOUT GND-A 10uF CONN_HP_ROUT
+ +
V3.3A FB4
R136 NO-POP J5
SJ1-3515-SMT, 5PJACK STEREO C5 0.1uF MIC_DET GND-A 4.7K GND-A VDD_IO1 R170 R141 AIC3254_ROUT
0 = LDO_OFF
1 2 BLM21AG151SN1D
B
J4 220uF 220uF HEADPHONE_ROUT HEADPHONE_LOUT C30 C128
AIC_MOSI AIC_SPI_SEL AIC_MISO AIC_SCLK
4 3 2 1
R135
HDR4
Tie Analog Power to Digital Power through single point connection or Ferrite Bead. FB1
HEADPHONES OUT
C1
2 4 5 3 1
1 2 BLM21AG151SN1D
TP15 GND GND-A
SJ1-3515-SMT, 5PJACK STEREO 100 NO-POP 100 C145 1uF

1 = LDO_ON
J7 C114 1uF AIC3254_LOUT
STEREO OUT
R197 C121 .047uF C156 .047uF R140 4.7K GND-A GND-A GND-A
2 4 5 3 1
SJ1-3515-SMT, 5PJACK STEREO

4 3 2
TMS320C5515 EVALUATION MODULE CODEC DWG NO 512702-0001 Monday, February 01, 2010
1
V13
C202 4.7uF,16V C200 10uF C201 10uF D14 MMBD4148 D15 MMBD4148
C194 10uF,16V
3
VDD_IO1 J19
R281
R275
50
VDD_IO1 R274 R277 2 LCD_BIAS_OE 2 LCD_ALE 2,12,19 nRESET R276 560K 1% 0 NO-POP
2 2 2 2 2 2 2 2
LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 2 LCD_RE 2 LCD_nWE
C199 VDD_IO1 NO-POP NO-POP NO-POP 1uF
C204
C198
C203
R279 R278
NO-POP 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC-1( GND ) VCC VCOMH VDDIO VSL NC-6 D7 D6 D5 D4 D3 D2 D1 D0 E/RDn R/Wn BS0 BS1 CSn D/Cn RESETn IREF GPIO1 GPIO0 NC-25 VDD VCI VSS NC-29 NC-30( GND )
OEL Display Module C195 10uF C205 4.7uF

This board uses a mirrored footprint for J19
0SD-2828GDEDF11
LCD POWER 13V

V13 V3.3 D6 L10 2.2uH MBR0520 U28 C193 1uF R96 1.6M 1% C192 10pF
5
C71 10uF
Vin
SW GND 4 EN FB
TPS61041
1 2
R97
C74 10uF,16V
3
180K
Z1
Z2
2 GPIO11_LCD_PWR R94 SPECTRUM DIGITAL INCORPORATED

A
1
Z3 Z4
10K Title: Page Contents: Size: B Date:

4 3 2
TMS320C5515 EVALUATION MODULE COLOR LCD INTERFACE DWG NO 512702-0001 Monday, February 01, 2010
1
A-21
A-22
Appendix B Mechanical Information
This appendix contains the mechanical information about the TMS320C5515 EVM produced by Spectrum Digital.
B-1
B-2
THIS DRAWING IS NOT TO SCALE
Printed in U.S.A., February 2010 512705-0001 Rev. A

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TMS320C5515 Evaluation Module (EVM) Technical Reference

DSP Development Systems

TMS320C5515 Evaluation Module (EVM) Technical Reference

512705-0001 Rev. A February 2010

Copyright 2010 Spectrum Digital, Inc.

Table 1: Hardware History Revision A B Prototype Release Production Release History

Table 2: Manual History Revision A History Production Release

Chapter 1 Introduction to the TMS320C5515 EVM

Spectrum Digital, Inc

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

C5515 Default Multiplexed Function

L13 P6 N6 P7 N7 N8 P9 N9 P10 N10

Spectrum Digital, Inc

N12 P13 N13 P14 N3 P4 N4 P5 N5

LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 LCD_EN_RDB LCD_CS0_E0 LCD_CS1_E1 LCD_RW_WRB LCD_RS

GP[28] GP[29] GP[30] GP[31] SPIO_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_CS3

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

Figure 1-2, EVM C5515 Memory Map

Spectrum Digital, Inc

TMS320C5515 EVM Technical Reference

Chapter 2 Physical Description

Spectrum Digital, Inc Topic

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

J9 J11 J14 J12 J15 SW4

Figure 2-1, TMS320C5515 EVM (Top)

Spectrum Digital, Inc

Figure 2-2, TMS320C5515 EVM (Bottom)

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

Headphones Out HDR4 Connector I

Spectrum Digital, Inc

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

Ground Right Headphone Left Headphone Figure 2-5, Headphone Connector

Figure 2-6, Top View of the J5 Connector

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

Figure 2-7, Top View of the J6 Connector

Spectrum Digital, Inc

TMS TDI Vcc TDO RTCK TCK EMU0

TRSTGND no pin (key) GND * GND GND EMU1

Figure 2-9, JTAG INTERFACE

Ground Right Line In Left Line In Figure 2-10, Stereo In 1 Jack

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

Ground Right Line In Left Line In Figure 2-11, Stereo In 2 Jack

TMS320C5515 EVM Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc