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EE669: VLSI Technology

Introduction to the Course

Anil Kottantharayil, Associate Professor, Department of EE, IIT Bombay

Device for controlling electric current

E. J. Lilienfeld US patent 1900018 28 Mar 1928 Did Lilienfeld ever make it?

C. T. Sah, Evolution of the transistor from concept to VLSI, Proc. IEEE, 76 (10), pp. 1280, 1988 2013 Monsoon EE669: Introduction; Anil Kottantharayil

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Point Contact Transistor: 16 Dec 1947

AT & T Bell Labs W. Brattain J. Bardeen

Gold foil

Nobel prize in 1956 Voltage gain : 15 Power gain: 1.3 @ 1 kHz

Polypropylene (3 cm)

Germanium bar Gold foil

AT & T Bell Lab archives.

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EE669: Introduction; Anil Kottantharayil

Type A Point Contact Transistor: 1948

W. G. Pfanns improved point contact transistor, AT & T Bell Labs, 1948.

Bo Jolek, History of semiconductor engineering, Springer, 2007. 2013 Monsoon EE669: Introduction; Anil Kottantharayil

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Grown bipolar junction transistors

Grown junction Bipolar Junction Transistors made by Morgan Sparks at AT & T Bell labs in 1950.
Bo Jolek, History of semiconductor engineering, Springer, 2007. 2013 Monsoon EE669: Introduction; Anil Kottantharayil

Mesa junction transistors

Lew Miller, Western Electric in 1958.

Bo Jolek, History of semiconductor engineering, Springer, 2007. 2013 Monsoon EE669: Introduction; Anil Kottantharayil

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Applications of Transistors Several that you already know And some that you probably did not know

In the early fifties it was quite fashionable for ladies in the Murray Hill neighborhood to use transistors as Bo Jolek, History of semiconductor engineering, Springer, 2007. colorful jewelry.

http://semiconductormuseum.com 2013 Monsoon EE669: Introduction; Anil Kottantharayil

Early Stage Transistors: features

Simple fabrication process by todays standard
you could make the point contact transistor of Brattain at home with not so sophisticated tools in about an hour with a rather short bill of materials

No two transistors worked the same way, if at all they worked low yield
The cut in the gold foil or spacing between whiskers are difficult to control point contact transistors Exposed semiconductor surfaces resulted in uncontrolled characteristics Processing not done in clean rooms large defect density

Pricy: In 1958, Fairchild sold 100 transistors to IBM for $ 150 a piece (inflation adjusted 2011 equivalent ~ $ 1050 per piece!)
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Planar Process for BJT Fabrication

N-type Si Oxidation

Base mask and oxide etch Base diffusion and oxidation

Emitter mask and oxide etch Emitter diffusion and oxidation

754m

Contact mask and oxide etch Metal deposition, mask and metal etch

Jean Hoerni, Fairchild Corporation, 1959, US patent 3064167.

Bo Jolek, History of semiconductor engineering, Springer, 2007. 2013 Monsoon EE669: Introduction; Anil Kottantharayil

Planar Process: the key difference from previous processes

Semiconductor surface is not directly exposed to ambient in a device obtained using the planar process lower leakage, higher breakdown voltage and better stability Large scale manufacturing of bipolar junction transistors with high yield possible using the planar process Precursor to integrated circuits
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Transistor assembly line of late 1950s

Bo Jolek, History of semiconductor engineering, Springer, 2007. 2013 Monsoon EE669: Introduction; Anil Kottantharayil

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Snapshot of the history

Si MOSFET 1-Transistor DRAM MOSFET Scaling theory

Bipolar Integrated Circuit CMOS transistor

VLSI era

1940
Electronic computer

1950

1960
IC based computer

1970

1980

1990

2000

Flash memory Microprocessor

Transistor based computer

Moores law

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Modern VLSI Circuits

metal6 via5 metal5 via4 metal4 via3 metal3 via2 metal2 via1 metal1 contact silicide
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30 nm
60 nm
Thomson et al., Intel technology journal, vol. 6, no. 2, 2002
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Modern VLSI Circuits (2) n-channel MOSFET

gate spacer
source

gate dielectric tOX W

drain

n+ poly

isolation

n+ p z

xj

n+

body

doping = NA
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package

Modern VLSI Circuits (3)

wire bonding

Al TaN oxide/nitride SiCN

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Fabrication Process of Modern MOSFET

p-type Si wafer (300 mm) oxidation (~1000C, O2) channel implant (75keV) oxide etch (wet in HF)
B+ p-Si

gate oxidation (SiO2) poly Si deposition

p-Si

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Fabrication Process of Modern MOSFET (2)

gate optical lithography
h

p-Si

p-Si As+

gate etch (anisotropic) resist removal S/D implant 1 (extensions)

p-Si

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Fabrication Process of Modern MOSFET (3)

spacer, Si3N4 (anisotropic etch)

S/D implant 2
As+

Ti/Co/Ni silicide

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Fabrication Process of Modern MOSFET (4)

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Moores Law

The complexity for the minimum component costs has increased at a rate of roughly a factor of two per year. the rate to remain constant for atleast 10 years.
Gorden E. Moore, Director, R&D Labs, Fairchild Corp. Electronics, 1965

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VLSI era

G. E. Moore, ISSCC 2003

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Driving Forces: Cost and Performance

~ Rs 250

~ Rs 0.00005

Expanding Moores law, ftp://download.intel.com/labs/eml/download/EML_opportunity.pdf 2013 Monsoon EE669: Introduction; Anil Kottantharayil

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Driving Forces: Cost, Performance and Social Impact

CNN

1946 - Electronic Numerical Integrator & Calculator ENIAC 2.4 m X 1 m X 30 m 30,000 kg 18,000 vacuum tubes 5,000 additions/sec
$ 500,000
Pennsylvania University Archives.

201X - A low-end IT device 0.02 m X 0.1 m X 0.15 m ~ 300 g > 1000,000,000 transistors ~ 1000,000,000 Hz Networked, better interface $ 100
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2013 Monsoon

EE669: Introduction; Anil Kottantharayil

Semiconductor Industry
Circuit design

Device design Integration Equipment manufacturers.

Lithography, ovens, etch tools, implanter, ..

Manufacturing

Test equipment
(material, electrical, )

System design

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International Technology Roadmap for Semiconductors (ITRS)

www.itrs.net
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International Technology Roadmap for Semiconductors (ITRS)

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EE669: Introduction; Anil Kottantharayil

ITRS 2009 edition www.itrs.net Process Integration, devices, and structures 26

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USD Billion

Global Semiconductor Industry

www.semi.org www.wsts.org

World GDP in 2010: USD 60000 Billion (source: CIA - USA) Semiconductor chip + equipment + materials: ~ 0.6 % of world GDP
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Centre of Excellence in Nanoelectronics

Started in 2006 as a 5-year joint project at IIT-B and IISc funded by DIT. Total funding of Rs 250 crore from DIT in two phases. IIT-B focuses on device oriented work Applied Materials Inc. (AMAT) donated equipment worth about Rs. 50 crore to IITB IITB internal funding of Rs. 20 crore Laboratory space of 35000 sq. ft. About 50 faculty members and 200 post-graduate students from various departments of IIT-B use the CEN facilities Several small and large projects funded by DST, ISRO, DRDO, .

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Examples of Equipment in CEN

Plasma&Implanter&

Double&Sided&Aligner&

E&B&Evaporation&

Furnaces&

20&nm&EB&Lithography&
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Dielectric&Sputter&System&
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PLD&
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Applied Materials (AMAT) Nanomanufacturing Laboratory

AMAT is a leading semiconductor / photovoltaic equipment manufacturer Named Laboratory set up with state-of-the-art tools worth Rs. 50 crores Several joint research projects between AMAT & IITB 30+ AMAT engineers/technicians stationed at IITB Donated equipment complements the CEN facilities

Gate&Stack&Centura&
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Etch&Centura&
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Endura&(PVD&&&PECVD)&
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Indian&Nanoelectronics&Users&Program&(INUP)&

National Centre of Photovoltaic Research and Education

NCPRE

Education

Research

Characterization, Modeling & Simulation

Si Solar Cells

New Materials & Devices

Solar PV Systems & Modules

5 year funding of Rs. 47.5 crore from MNRE Part of Jawaharlal Nehru National Solar Mission (JNNSM) launched in January 2010: 20 GW from solar by 2022 Strong Education + Research thrust Participation from several departments
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Research activities of my group

Graphene electronics
Flash memory Graphene gate electrode

c-Si Photovoltaics
Surface passivation of silicon Silicon nanowire solar cells

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Graphene floating gate memory

250
! V g s = 1V

200

-V g s = 2V -V g s = 3V -V g s = 4V -V g s = 5V

D rain -c o u p lin g reg io n

H o t-elec tro n in jec tio n reg io n

I D (A )

150 100 50 0

-V g s = 6V -V g s = 7V -V g s = 8V

L in earreg io n

V D S (V )

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Graphene as gate electrode 5.1

!

5.0

#Ig n o rin g #C h arg e

W F #(e V )

4.9 4.8 4.7 4.6 4.5

#C o rrec ted #fo r#C h arg es

4.4
No

#G r # 1 '3

Gr

# la y

e rs # 3 '5

Gr

s e rs yer # la y r # la )# G 5 > k #( h ic

Misra et al., IMW, 2012 Misra et al., Applied Physics Letters, 2012 Misra et al., ICEE, 2012 Misra et al., Electron Device Letters, 2013

!
!

Plasma grown oxide for c-Si surface passivation

Si

Sandeep SS et al., IEEE Electron Device Letters, 2013 Sandeep SS et al., EUPVSC 2013

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Pulse-DC sputter deposited Al2O3 for c-Si surface passivation

M. Bhaisare et al., IEEE J. Photovoltaics, 2013 M. Bhaisare et al., IEEE PVSC 2013

Si Nanowire Solar Cells

By etching (top down)

By CVD (bottom up)

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Bibliography
Bo Jolek, History of semiconductor engineering, Springer, 2007 W. Shockley, The path to the conception of the junction transistor, IEEE Transactions on Electron Devices, vol. 31, No. 11, 1984, pp. 1523 I. Ross, The invention of the transistor, Proceedings of the IEEE, vol. 86, No. 1, 1998, pp. 7. Jean Hoerni, Fairchild Corporation, 1959, US patent 3064167. Gorden Moore, "Cramming more components onto integrated circuits", Electronics, Volume 38, Number 8, April 19, 1965. Dennard et al., Design of ion-implanted MOSFET's with very small physical dimensions, IEEE Journal of Solid State Circuits, Vol. 9, No. 5, October 1974. The impact of Dennards scaling theory, IEEE Solid-State Circuits Society News, special issue, http://www.ieee.org/portal/cms_docs_societies/sscs/PrintEditions/200701.pdf J. Gertner, The idea factory, Bell labs and the great age of American innovation, The Penguin Press, 2012
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Reference books
J. D. Plummer, M. D. Deal, P. G. Griffin, Silicon VLSI Technology, Pearson Education, 2001 S. K. Ghandhi, VLSI Fabrication Principles Silicon and Gallium Arsenide, John Wiley and Sons, 1983. S. A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford University Press, 2001

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