EEE/CSE 120 Simulation Lab 2 Answer Sheet 4-Bit Full Adder, Multiplexer & Decoder

Name:____Genaro Romero______________________ Instructor:__________________________ Class Time:________________________ Date:________________________

Task 2-1: Design a Full Adder

Write down the canonical POS expressions for the Cout and SUM function of a full adder. Be sure to check the lab manual for more detailed information. :_____________________________________________ _____________________________________________________________________________________ _____________________________________________________________________________________ Cut and paste your LogicWorks circuit that implements your canonical SUM and Cout functions here:
0 1 A 0 1

1 Cout

B 0 1 Cin

Follow the testing procedures outlined in the laboratory manual on your circuit and record your results in Table 1. Table 1 B SUM 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1

Cin 0 0 0 0 1 1 1 1

A 0 0 1 1 0 0 1 1

Cout 0 0 0 1 0 1 1 1

Task 2-2: Build, Debug and Test a 1-Bit Full Adder

Cut and paste your LogicWorks 1-bit minimal form full-adder circuit here:

SUM

Cout

Cin

Test your minimal form full-adder circuit and record your results in Table 2. Cut and paste your LogicWorks 1-bit minimal form full-adder circuit testing set up.
0 SUM

A 0 1

0 1

B 0 1

0 Cout

Cin

Table 2 Cin 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1

Debug Checkm ark X X X X X X X X

Cut and paste your LogicWorks 1-bit full adder subcircuit here:

FA_1
A B Cin SUM Cout

Test your subcircuit and place a mark in the checkmark column of Table 2 next to values you tested. Cut and paste your LogicWorks 1-bit full-adder subcircuit testing set up.

1 0 1 0 1 0

FA_1
A B Cin SUM Cout

Task 2-3: Design, Build and Test a 4-Bit Full Adder

Cut and paste your LogicWorks 4-bit full-adder circuit here:

FA_1
A0 B0 Cin A B Cin SUM Cout Y0

FA_1
A1 B1 A B Cin SUM Cout Y1

FA_1
A2 B2 A B Cin SUM Cout Y2

FA_1
A3 B3 A B Cin SUM Cout Y3 Cout

Develop a test plan and record your results in Table 3 (Note: Do NOT test all input combinations. Table 3 may not need to be entirely filled in). Connect a hex keyboard to the inputs A and B as well as a hex display to SUM. It is left to you to decide what constitutes a sufficient test set. Give justification as to why completing your tests make it likely that the 4-bit full-adder circuit is operating correctly:___________________________________________________________________________ __

Cut and paste your LogicWorks 4-bit full-adder testing set up.

0 1

FA_1
A0 B0 Cin A B Cin 1 0 1 0 1 0 SUM Cout

0 Y0

FA_1
A1 B1 A B Cin 0 1 1 0 SUM Cout

0 Y1

FA_1
A2 B2 0 1 A B Cin SUM Cout

0 Y2

1 0

FA_1
A3 B3 1 0 A B Cin SUM Cout

0 Y3 Cout 0

Table 3 6

Debug

Cin 0 0 0 0 0 0 0 1 1 1 1 1 1 1

A (hex) A B C D E F 1 A B C D E F 1

B (hex) A B C D E F 1 A B C D E F 1

SUM (hex) 4 6 8 A C E 2 5 7 9 B D F 3

Cout 1 1 1 1 1 1 0 1 1 1 1 1 1 0

Checkmar k X X X X X X X X X X X X X X

Cut and paste your LogicWorks 4-bit full-adder subcircuit here:

FA_4
A3 A2 A1 A0 B3 B2 B1 B0 Cin Y3 Y2 Y1 Y0 Cout

Test your subcircuit and place a mark in the checkmark column of Table 3 next to values you used to verify your subcircuit. Cut and paste your LogicWorks 4-bit full-adder subcircuit testing set up.

0 4 8 C

1 5 9 D

2 6 A E

3 7 B F

FA_4
A3 A2 A1 A0 B3 B2 B1 B0 Cin +5V Y3 Y2 Y1 Y0 Cout 1

0 4 8 C

1 5 9 D

2 6 A E

3 7 B F

Task 2-4: Design, Build and Test a MUX

Cut and paste your LogicWorks 1-bit MUX circuit here:
A/~B B

Test your 1-bit MUX circuit and record your results in Table 4. Cut and paste your LogicWorks 1-bit MUX circuit testing set up.
1 0 A/~B B 1 Y A 1 0 1 0

Table 4 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A/~B 0 1 0 1 0 1 0 1 Y 0 1 0 1 0 0 1 1

Debug checkm ark X X X X X X X X

Cut and paste your LogicWorks 1-bit MUX subcircuit here:

MUX_1
A B A/~B Y

Test your 1-bit Mux subcircuit and place a mark in the checkmark column of Table 4 to indicate the values you checked. Cut and paste your LogicWorks 1-bit MUX subcircuit testing set up.

MUX_1
1 0 1 01 0 A B A/~B Y

Task 2-5: Build a 2-Input 4-Bit Multiplexer

Cut and paste your LogicWorks 4-bit MUX circuit here:

MUX_1
A/~B A0 B0 A B A/~B Y Y0

MUX_1
A1 B1 A B A/~B Y Y1

MUX_1
A2 B2 A B A/~B Y Y2

MUX_1
A3 B3 A B A/~B Y Y3

Test your MUX and record your results in Table 5. It is left to you to decide what test combination to use. Note all of Table 5 may not need to be filled in. Cut and paste your LogicWorks 4-bit MUX circuit testing set up.

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0 0 1 1 0 1 A0 A/~B

MUX_1
A B A/~B Y 1 Y0

B0

0 1 0 1

MUX_1
Y

A1 B1

A B A/~B

1 Y1

0 1

MUX_1
A B A/~B Y

0 1

B2

A2

1 Y2

0 1

0 1

MUX_1
A B A/~B Y

B3 B3

A3

1 Y3

Table 5 A (hex) A B C D E F 1 2 3 B (hex) A B C D E F 1 2 3 A/~B 1 1 1 1 1 0 0 0 0 Y (hex) 5 4 3 2 1 0 F E D Debug checkma rk X X X X X X X X X

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Cut and paste your LogicWorks 4-bit MUX subcircuit here:

MUX_4
A3 A2 A1 A0 B3 B2 B1 B0 A/~B

Y3 Y2 Y1 Y0

Test and verify your subcircuit is working properly using and place a mark in the checkmark column of Table 5 next to values you used to verify your subcircuit. Cut and paste your LogicWorks 4-bit MUX subcircuit testing set up.

MUX_4
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A3 A2 A1 A0 B3 B2 B1 B0 A/~B

Y3 Y2 Y1 Y0 1

Task 2-6: Build and Test a 1-to-2 Demultiplexer

Cut and paste your LogicWorks 1-bit , 1-to-2 demux circuit here:

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Y Y/~Z

Cut and paste your LogicWorks1-bit , 1-to-2 demux subcircuit here:

DEMUX_1
Y/~Z D Z Y

Test your 1-bit , 1-to-2 demux subcircuit and record the results in Table 6. Cut and paste your LogicWorks 1-to-2 demux subcircuit testing set up.

DEMUX_1
1 01 0 Y/~Z D Z Y

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Table 6 Y/~Z 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 Y 0 0 0 1 0 0 0 1 Z 0 1 0 0 0 1 0 0

Debug checkma rk Circuit X X X X X X X X

Debug checkma rk Subcricui t X X X X X X X X

Task 2-7: Repackage the 1-to-2 Demux as a 1-to-2 Decoder

Cut and paste your LogicWorks 1-to-2 decoder subcircuit here:

DECODER_1
A0 EN Y0 Y1

Test your 1-to-2 Decoder subcircuit and record your results in Table 7. Cut and paste your LogicWorks 1-to-2 decoder subcircuit testing set up.

DECODER_1
1 01 0 A0 EN Y0 Y1

0 0

EN 0 0 1 1 0 0 1

Table A0 0 1 0 1 0 1 0 14

7 Y0 0 1 0 0 0 1 0

Y1 0 0 0 1 0 0 0

Task 2-8: Build and Test a 2-to-4 Decoder

Cut and paste your LogicWorks 2-to-4 decoder circuit here:

EN

Y0

A0

Y1

A1

Y2

Y3

Test your 2-to-4 decoder circuit and record your results in Table 8. Cut and paste your LogicWorks 2-to4 decoder subcircuit testing set up.

DECODER_2
1 0 1 1 0 0 A1 A0 EN Y0 Y1 Y2 Y3

0 0 0 0

Table 8 EN 0 0 0 A1 0 0 1 A0 0 1 0 Y0 0 0 0 15 Y1 0 0 0 Y2 0 0 0 Y3 0 0 0

Debug checkma rk X X X

0 1 1 1 1

1 0 0 1 1

1 0 1 0 1

0 1 0 0 0

0 0 1 0 0

0 0 0 1 0

0 0 0 0 1

X X X X X

Cut and paste your LogicWorks 2-to-4 decoder subcircuit here:

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3

Test and verify your 2-to-4 decoder subcircuit and place a mark in the checkmark column of Table 8 for the values you test. Cut and paste your LogicWorks 2-4 decoder subcircuit testing set up.

0 1 0 1 1 0 0

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3 0 0 0

Task 2-9: Design, Build & Test a 4-to16 Decoder Using 2to-4 Decoders
Cut and paste your LogicWorks 4-to-16 decoder circuit, constructed from copies of the subcircuit developed in Task 2-7, here:

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DECODER_2
A1 A0 A1 A0 EN Y0 Y1 Y2 Y3 Y00 Y01 Y02 Y03

DECODER_2
A3 A2 EN A1 A0 EN Y0 Y1 Y2 Y3

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3 Y04 Y05 Y06 Y07

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3 Y08 Y09 Y10 Y11

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3 Y12 Y13 Y14 Y15

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Test your circuit, with EN set to 1, and record your results in Table 9. Cut and paste your LogicWorks 4-16 decoder circuit testing set up.
0 1

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3

0 Y01 Y03

0 Y00 0 Y02 0

A1

A0

0 1

DECODER_2
Y0 Y1 Y2 Y3

0 1

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3 0

Y04 0 Y06 Y05

A3 A2 EN

A1 A0 EN 0 0 1 1

0 Y07

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3

0 Y09 Y11 0 0

0 Y08

Y10

DECODER_2
A1 A0 EN Y0 Y1 Y2 Y3

Y12 0 Y13 Y15 0 0 0 Y14

Table 9 Y 0 1 0 0 0 0 Y 1 0 0 0 0 0 Y 2 0 0 0 0 0 Y 3 0 0 0 0 0 Y 4 0 1 0 0 0 Y 5 0 0 0 0 0 Y 6 0 0 0 0 0 Y 7 0 0 0 0 0 18 Y 8 0 0 1 0 0 Y1 0 0 0 0 0 0 Y1 1 0 0 0 0 1 Y1 2 0 0 0 1 0 Y1 3 0 0 0 0 0 Y1 4 0 0 0 0 0 Y1 5 0 0 0 0 0

Debug checkm ark Y9 0 0 0 0 0

A3 0 0 1 1 1

A2 0 1 0 1 0

A1 0 0 0 0 1

A0 0 0 0 0 1

X X X X X

Cut and paste your LogicWorks 4-to-16 Decoder subcircuit here:

DECODER_4
Y00 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15

A3 A2 A1 A0 EN

Test and verify that your subcircuit is working properly and place a mark in the checkmark column of Table 9 next to values that you tested. Cut and paste your LogicWorks 4-to-16 subcircuit testing set up.

DECODER_4
Y00 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 0

0 1

0 0

1 0

1 0

A3 A2 A1 A0 EN

1 0

Task 2-10: Backup Your Files

Did you backup your files to a NEW directory?_________YES___

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SIMULATION LAB 2: LAB REPORT GRADE SHEET

Name :

Instructor Assessment
Grading Criteria Template Neatness, Clarity, and Concision Description of Assigned Tasks, Work Performed & Outcomes Met a Full Adder Task 2-1: Design Task 2-2: Build, Debug and Test a 1-Bit Full Adder Task 2-3: Design, Build and Test a 4-Bit Full Adder Task 2-4: Design, Build and Test a MUX Task 2-5: Build a 2-Input 4-Bit Multiplexer Task 2-6: Build and Test a 1-to-2 Demultiplexer Task 2-7: Repackage the 1-to-2 Demux as a 1-to-2 Task 2-8: Build and Test a 2-to-4 Decoder Task 2-9: Design, Build & Test a 4-to-16 Decoder Self-Assessment Worksheet (The content of the selfMax Points Points Lost

5 10 10 11 10 10 12 10 12 12 (5 extra points) Points Lost Late Lab Lab Score

assessment worksheet will not be graded. Full credit is given for including the completed worksheet.)

Lab Score

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SELF-ASSESSMENT WORKSHEET
Put Xs in the table below indicating how strongly you agree or disagree that the outcomes of the assigned tasks were achieved. Use 5 to indicate that you strongly agree, 3 to indicate that you are 'neutral', and 1 to indicate that you strongly disagree. Use NA, Not Applicable, when the tasks you performed did not elicit this outcome. Credit will be given for including this worksheet with your lab report; however, your responses will not be graded. They are for your instructors information only. Table __: Self-Assessment of Outcomes for Simulation Lab 2: 4-Bit Full Adder, Multiplexer & Decoder. After completing the assigned tasks and report, I am able to:
A POS or SOP form of a full adder.

5 X X X X X X X

NA

A 4-bit full adder. A 2-to-1 multiplexer. A 4-bit, 2-to-1 multiplexer. A 1-to-2 decoder. A 2-to-4 decoder. A 4-to-16 decoder.

Write below any suggestions you have for improving this laboratory exercise so that the stated learning outcomes are achieved.

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