Clock gating is one of the power-saving techniques used on the Pentium 4processor.

To save power, clock gating refers to activating the clocks in a logicblock only when there is work to be done. From the earliest days of the Pentium 4 processor design, power consumption was a concern. The clock gating concept isn't a new one; however, the Pentium 4 processor used this technology to a large extent. Every unit on the chip has a power reduction plan, and almost every Functional Unit Block (FUB) contains clock gating logic.

Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree. Pruning the clock disables portions of the circuitry so that the flip-flops in them do not have to switch states. Switching states consumes power. When not being switched, the switching power consumption goes to zero, and only leakage currents are incurred.[1] Clock gating works by taking the enable conditions attached to registers, and uses them to gate the clocks. Therefore it is imperative that a design must contain these enable conditions in order to use and benefit from clock gating. This clock gating process can also save significant die area as well as power, since it removes large numbers of muxes and replaces them with clock gating logic. This clock gating logic is generally in the form of "Integrated clock gating" (ICG) cells. However, note that the clock gating logic will change the clock tree structure, since the clock gating logic will sit in the clock tree. Clock gating logic can be added into a design in a variety of ways: 1. Coded into the RTL code as enable conditions that can be automatically translated into clock gating logic by synthesis tools (fine grain clock gating). 2. Inserted into the design manually by the RTL designers (typically as module level clock gating) by instantiating library specific ICG (Integrated Clock Gating) cells to gate the clocks of specific modules or registers. 3. Semi-automatically inserted into the RTL by automated clock gating tools. These tools either insert ICG cells into the RTL, or add enable conditions into the RTL code. These typically also offer sequential clock gating optimisations. Note: Any RTL modifications to improve clock gating will result in functional changes to the design (since the registers will now hold different values) which need to be verified. Sequential clock gating is the process of extracting/propagating the enable conditions to the upstream/downstream sequential elements, so that additional registers can be clock gated. Although asynchronous circuits by definition do not have a "clock", the term perfect clock gating is used to illustrate how various clock gating techniques are simply approximations of the data-dependent behavior exhibited by asynchronous circuitry. As the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit: the circuit only generates logic transitions when it is actively computing.[2] Chip families such as OMAP3, with a cell phone heritage, support several forms of clock gating. At one end is the manual gating of clocks by software, where a driver enables or disables the various clocks used by a given idle controller. On the other end is automatic clock gating, where the hardware can be told to detect whether there's any work to do, and turn off a given clock if it is not needed. These forms interact with each other and may be part of the same enable tree. For example, an internal bridge or bus might use automatic gating so that it is gated off until the CPU or a DMA engine needs to use it, while several of the peripherals on that bus might be permanently gated off if they are unused on that board.
As consumers continue to demand more functionality in smaller, more energy efficient devices, power optimization rules a hardware designer's life. It typically takes multiple iterations over weeks of optimization to

achieve power goals and budgets. While power should be optimized at all stages of the design flow, many times it is only addressed after initial register transfer level (RTL) synthesis runs uncover inefficiencies. RTL clock gating is the most commonly used optimization technique for improving energy efficiency, but leads to the question of how well a design is clock gated. The traditional method of looking at the percentage of registers clock gated is not indicative of the energy efficiency because it does not take into account switching activity. The average clock-gating efficiency is a much better indicator of energy consumption because it measures of both the number of registers gated and the duration they are turned off. Dynamic Power Optimization at Multiple Design Stages A design's energy consumption is a function of the switching activity, which in turn is totally dependent on the system application and hardware implementation. Designers typically have little control over the application; video must be compressed at a given rate, packets routed within a given latency or instructions executed at a certain frequency. In contrast, there are multiple design techniques and tricks the designer has at his or her disposal when implementing the hardware. Clock gating is an accepted design technique for optimizing power, and can be applied at the system level, RTL and gate-level. The granularity of clock gating and the impact it has on overall energy consumption depends on the design stage. Although each design stage offers an opportunity to save power, higher levels of abstraction have greater impact on reducing power and lowering costs. Starting at the system-level, a CPU may have multiple sleep modes, each disabling specific blocks in the design. Moving down in abstraction, RTL clock gating shuts off unused computations while leaving other logic active for data processing. For example, turning off unused computations such as shift, multiple or add within an Arithmetic Logic Unit (ALU) based on the operator. Gate-level clock gating can provide a finer grain of control by not clocking a register if it is not changing states. As in the case of an output hold, the clock can be gated with the hold condition so that the register is not unnecessarily toggling. Figure 1 shows potential opportunities for saving power at different stages of design.