Pic12f629 675

M
PIC12F629/675 Data Sheet

8-Pin FLASH-Based 8-Bit CMOS Microcontrollers
2002 Microchip Technology Inc.
Preliminary
DS41190A
Note the following details of the code protection feature on PICmicro MCUs. The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
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Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Companys quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001 certified.
DS41190A - page ii
Preliminary
M
PIC12F629
PIC12F629/675
Pin Diagram
8-Pin PDIP, SOIC
VDD GP5/T1CKI/ OSC1/CLKIN GP4/T1G/ OSC2/CLKOUT GP3/MCLR/VPP 1 8 VSS GP0/CIN+/ICSPDAT GP1/CIN-/ICSPCLK GP2/T0CKI/ INT/COUT
8-Pin FLASH-Based 8-Bit CMOS Microcontroller

PIC12F675
Devices included in this Data Sheet:
High Performance RISC CPU:

Only 35 instructions to learn All single cycle instructions (200 ns), except for program branches which are two-cycle Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle Memory - 1024 x 14 words of FLASH Program Memory - 64 x 8 bytes of Data Memory (SRAM) - 128 x 8 bytes of EEPROM data memory Interrupt capability 16 special function hardware registers 8-level deep hardware stack Direct, Indirect, and Relative Addressing modes
PIC12F629
2 3 4
7 6 5
Special Microcontroller Features:

Low power Power-on Reset (POR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Low power Brown-out Detect (BOD) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Multiplexed MCLR pin Interrupt-on-pin change Individual programmable weak pull-ups Programmable code protection Power saving SLEEP mode Selectable oscillator options - RC: External RC oscillator - INTOSC: 4 MHz internal oscillator - EC: External Clock input - XT: Standard crystal/resonator - HS: High speed crystal/resonator - LP: Power saving, low frequency crystal In-Circuit Serial ProgrammingTM (ICSPTM) via two pins Four user programmable ID locations
Peripheral Features:
6 I/O pins with individual direction control High current sink/source for direct LED drive Analog comparator module with: - One analog comparator - Programmable on-chip comparator voltage reference (CVREF) module - Programmable input multiplexing from device inputs - Comparator output is externally accessible Analog-to-Digital Converter module (PIC12F675): - 10-bit resolution - Programmable 4-channel input - Voltage reference input Timer0: 8-bit timer/counter with 8-bit programmable prescaler Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator, if INTRC Oscillator mode selected 64 bytes of general purpose RAM
CMOS Technology:
Low power, high speed CMOS FLASH technology Fully static design Wide operating voltage range - PIC12F629/675 - 2.0V to 5.5V Industrial and Extended temperature range Low power consumption - < 1.0 mA @ 5.5V, 4.0 MHz - 20 A typical @ 2.0V, 32 kHz - < 1.0 A typical standby current @ 2.0V
* 8-bit, 8-pin devices protected by Microchips Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.
Preliminary
DS41190A-page 1
PIC12F629/675
Pin Diagrams
8-pin PDIP, SOIC
VDD GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/VPP 1 2 3 4 8 7 6 5 VSS GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT
PIC12F675
8-pin MLF-S
VSS GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT 8 7 6 5 PIC12F675 1 2 3 4
PIC12F629 1 2 3 4
VSS GP0/CIN+/ICSPDAT GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT 8 7 6 5
DS41190A-page 2
Preliminary
VDD GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/VPP
VDD GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/VPP
PIC12F629/675
Table of Contents
1.0 Device Overview. ......................................................................................................................................................................... 5 2.0 Memory Organization ....................... ............................................................................................................................................7 3.0 GPIO Port............................ .......................................................................................................................................................19 4.0 Timer0 Module ........................................................................................................................................................................... 25 5.0 Timer1 Module with Gate Control............................................................................................................................................... 28 6.0 Comparator Module.................................................................................................................................................................... 33 7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only)..................................................................................................... 39 8.0 Data EEPROM Memory. ............................................................................................................................................................ 47 9.0 Special Features of the CPU...................................................................................................................................................... 51 10.0 Instruction Set Summary ............................................................................................................................................................ 69 11.0 Development Support................................................................................................................................................................. 77 12.0 Electrical Specifications.............................................................................................................................................................. 83 13.0 Packaging Information.............................................................................................................................................................. 101 Appendix A: Data Sheet Revision History ....................................................................................................................................... 107 Appendix B: Device Differences...................................................................................................................................................... 107 Appendix C: Device Migrations ....................................................................................................................................................... 108 Appendix D: Migrating from other PICmicro Devices ...................................................................................................................... 108 Appendix E: Development Tool Version Requirements .................................................................................................................. 109 Index .................................................................................................................................................................................................. 111 On-Line Support ................................................................................................................................................................................ 115 Reader Response ............................................................................................................................................................................. 116 Product Identification System ........................................................................................................................................................... 117
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Errata
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Preliminary
DS41190A-page 3
PIC12F629/675
NOTES:
DS41190A-page 4
Preliminary
PIC12F629/675
1.0 DEVICE OVERVIEW
This document contains device specific information for the PIC12F629/675. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this Data Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC12F629 and PIC12F675 devices are covered by this Data Sheet. They are identical, except the PIC12F675 has a 10-bit A/D converter. They come in 8-pin PDIP, SOIC, and MLF-S packages. Figure 1-1 shows a block diagram of the PIC12F629/675 devices. Table 1-1 shows the Pinout Description.
FIGURE 1-1:
PIC12F629/675 BLOCK DIAGRAM

13 FLASH Program Memory 1K x 14 8 Level Stack (13-bit) Program Counter Data Bus 8 GP0/AN0/CIN+ GP1/AN1/CIN-/VREF GP2/AN2/T0CKI/INT/COUT GP3/MCLR/VPP GP4/AN3/T1G/OSC2/CLKOUT GP5/T1CKI/OSC1/CLKIN RAM Addr(1)
Program Bus
RAM File Registers 64 x 8 9
14
Instruction Reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR Reg Internal 4 MHz Oscillator Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT VDD, VSS 8 3 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8 W Reg STATUS Reg
MUX
ALU
10-bit A/D (PIC12F675 only)
Timer0
Timer1
CVREF
Comparator
EE Data Memory
Note 1: Higher order bits are from STATUS register.
Preliminary
DS41190A-page 5
PIC12F629/675
TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION
Function GP0 AN0 CIN+ ICSPDAT GP1 AN1 CINVREF ICSPCLK GP2 AN2 T0CKI INT COUT GP3/MCLR/VPP GP3 MCLR VPP GP4/AN3/T1G/OSC2/ CLKOUT GP4 AN3 T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN VSS VDD Input Type TTL AN AN TTL TTL AN AN AN ST ST AN ST ST CMOS TTL ST HV TTL AN ST XTAL CMOS TTL ST XTAL ST Power Power CMOS CMOS Output Type CMOS Description Bi-directional I/O w/ programmable pull-up and interrupt-on-change A/D Channel 0 input (PIC12F675 only) Comparator input Serial programming I/O Bi-directional I/O w/ programmable pull-up and interrupt-on-change A/D Channel 1 input (PIC12F675 only) Comparator input External voltage reference (PIC12F675 only) Serial programming clock Bi-directional I/O w/ programmable pull-up and interrupt-on-change A/D Channel 2 input (PIC12F675 only) TMR0 clock input External interrupt Comparator output Input port w/ interrupt-on-change Master Clear Programming voltage Bi-directional I/O w/ programmable pull-up and interrupt-on-change A/D Channel 3 input (PIC12F675 only) TMR1 gate Crystal/resonator FOSC/4 output Bi-directional I/O w/ programmable pull-up and interrupt-on-change TMR1 clock Crystal/resonator External clock input/RC oscillator connection Ground reference Positive supply Name GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/VREF/ ICSPCLK
CMOS CMOS
GP2/AN2/T0CKI/INT/COUT
CMOS
VSS VDD
DS41190A-page 6
Preliminary
PIC12F629/675
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
2.2
Data Memory Organization
The PIC12F629/675 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h - 03FFh) for the PIC12F629/675 devices are physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 1K x 14 space. The RESET vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose registers and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank. Register locations 20h-5Fh are General Purpose registers, implemented as static RAM and are mapped across both banks. All other RAM is unimplemented and returns 0 when read. RP0 (STATUS<5>) is the bank select bit. RP0 = 0 Bank 0 is selected RP0 = 1 Bank 1 is selected Note: The IRP and RP1 bits STATUS<7:6> are reserved and should always be maintained as 0s.
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC12F629/675

PC<12:0>
CALL, RETURN RETFIE, RETLW
2.2.1
13
GENERAL PURPOSE REGISTER FILE
Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector 000h
The register file is organized as 64 x 8 in the PIC12F629/675 devices. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4).
Interrupt Vector
0004 0005
On-chip Program Memory 03FFh 0400h
1FFFh
Preliminary
DS41190A-page 7
PIC12F629/675
2.2.2 SPECIAL FUNCTION REGISTERS FIGURE 2-2:
The Special Function registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function registers associated with the core are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
DATA MEMORY MAP OF THE PIC12F629/675

File Address File Address Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISIO 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
Indirect addr.(1) TMR0 PCL STATUS FSR GPIO
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
PCLATH INTCON PIR1 TMR1L TMR1H T1CON
PCLATH INTCON PIE1 PCON OSCCAL
WPU IOCB
CMCON
ADRESH(2) ADCON0(2)
VRCON EEDATA EEADR EECON1 EECON2(1) ADRESL(2) ANSEL(2)
General Purpose Registers 64 Bytes
accesses 20h-5Fh
5Fh 60h
DFh E0h
7Fh Bank 0 Bank 1
FFh
1: 2:
Unimplemented data memory locations, read as 0. Not a physical register. PIC12F675 only.
DS41190A-page 8
Preliminary
PIC12F629/675
TABLE 2-1:
Address Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF(1) TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H T1CON CMCON ADRESH(3) ADCON0(3) Addressing this Location uses Contents of FSR to Address Data Memory Timer0 Modules Register Program Counter's (PC) Least Significant Byte IRP(2) RP1(2) RP0 TO PD Z DC C
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
SPECIAL FUNCTION REGISTERS SUMMARY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Page
18,59 25 17 11 18 19 17 13 15 28 28 30 33 40 41,59
Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented Unimplemented GIE EEIF PEIE ADIF T0IE Write Buffer for Upper 5 bits of Program Counter INTE GPIE CMIF T0IF INTF GPIF TMR1IF GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
--xx xxxx

---0 0000 0000 0000 00-- 0--0
Unimplemented Holding Register for the Least Significant Byte of the 16-bit Timer1 Holding Register for the Most Significant Byte of the 16-bit Timer1 TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
xxxx xxxx xxxx xxxx -000 0000
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
COUT
CINV
CIS
CM2
CM1
CM0
-0-0 0000
Unimplemented Unimplemented Unimplemented Unimplemented Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result ADFM VCFG CHS1 CHS0 GO/DONE ADON

xxxx xxxx 00-- 0000
= unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as 0. 3: PIC12F675 only.
Legend:
Preliminary
DS41190A-page 9
PIC12F629/675
TABLE 2-1:
Address Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh WPU IOCB VRCON EEDATA EEADR EECON1 EECON2(1) ADRESL(3) ANSEL(3) PCON OSCCAL INDF(1) OPTION_REG PCL STATUS FSR TRISIO PCLATH INTCON PIE1 Addressing this Location uses Contents of FSR to Address Data Memory GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 1111 1111 0000 0000
SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Page
18,59 12,26 17 11 18 19 17 13 14 16 16 19 20 38 47 47 48 48 40 42,59
Program Counters (PC) Least Significant Byte IRP(2) RP1(2) RP0 TO PD Z DC C
0001 1xxx xxxx xxxx
Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented Unimplemented GIE EEIE PEIE ADIE T0IE Write Buffer for Upper 5 bits of Program Counter INTE GPIE CMIE T0IF INTF GPIF TMR1IE TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0
--11 1111

---0 0000 0000 0000 00-- 0--0
Unimplemented Unimplemented CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 POR BOD
---- --0x
1000 00--
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented VREN WPU5 IOCB5 WPU4 IOCB4 IOCB3 WPU2 IOCB2 WPU1 IOCB1 WPU0 IOCB0

--11 1111 --00 0000
VRR
VR3
VR2
VR1
VR0
0-0- 0000 0000 0000 -000 0000
Data EEPROM Data Register Data EEPROM Address Register WRERR WREN WR RD
---- x000 ---- ---xxxx xxxx
EEPROM Control Register 2 Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0
-000 1111
= unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as 0. 3: PIC12F675 only.
Legend:
DS41190A-page 10
Preliminary
PIC12F629/675
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains: the arithmetic status of the ALU the RESET status the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bits. For other instructions not affecting any STATUS bits, see the Instruction Set Summary. Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC12F629/675 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS STATUS REGISTER (ADDRESS: 03h OR 83h)

Reserved Reserved IRP bit 7 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7 bit 6 bit 5
IRP: This bit is reserved and should be maintained as 0 RP1: This bit is reserved and should be maintained as 0 RP0: Register Bank Select bit (used for direct addressing) 0 = Bank 0 (00h - 7Fh) 1 = Bank 1 (80h - FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) For borrow, the polarity is reversed. 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
Preliminary
DS41190A-page 11
PIC12F629/675
2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to 1 (OPTION<3>). See Section 4.4. The OPTION register is a readable and writable register, which contains various control bits to configure: TMR0/WDT prescaler External GP2/INT interrupt TMR0 Weak pull-ups on GPIO
REGISTER 2-2:
OPTION_REG OPTION REGISTER (ADDRESS: 81h)

R/W-1 GPPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the TIMER0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
DS41190A-page 12
Preliminary
PIC12F629/675
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO port change and external GP2/INT pin interrupts.
REGISTER 2-3:
INTCON INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)

R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 GPIE R/W-0 T0IF R/W-0 INTF R/W-0 GPIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt GPIE: Port Change Interrupt Enable bit 1 = Enables the GPIO port change interrupt 0 = Disables the GPIO port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit(1) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur GPIF: Port Change Interrupt Flag bit 1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software) 0 = None of the GP5:GP0 pins have changed state Note 1: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and should be initialized before clearing T0IF bit. Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS41190A-page 13
PIC12F629/675
2.2.2.4 PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
PIE1 PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)

R/W-0 EEIE bit 7 R/W-0 ADIE U-0
U-0
R/W-0 CMIE
U-0
U-0
R/W-0 TMR1IE bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only) 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt Unimplemented: Read as 0 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt Unimplemented: Read as 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
bit 6
bit 5-4 bit 3
bit 2-1 bit 0
DS41190A-page 14
Preliminary
PIC12F629/675
2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5:
PIR1 PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)

R/W-0 EEIF bit 7 R/W-0 ADIF U-0 U-0 R/W-0 CMIF U-0 U-0 R/W-0 TMR1IF bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only) 1 = The A/D conversion is complete (must be cleared in software) 0 = The A/D conversion is not complete Unimplemented: Read as 0 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed Unimplemented: Read as 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
bit 6
bit 5-4 bit 3
bit 2-1 bit 0
Preliminary
DS41190A-page 15
PIC12F629/675
2.2.2.6 PCON Register
The Power Control (PCON) register contains flag bits to differentiate between a: Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6:
PCON POWER CONTROL REGISTER (ADDRESS: 8Eh)

U-0 bit 7 U-0 U-0 U-0 U-0 U-0 R/W-0 POR R/W-x BOD bit 0
bit 7-2 bit 1
Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOD: Brown-out Detect Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
bit 0
2.2.2.7
OSCCAL Register
The Oscillator Calibration register (OSCCAL) is used to calibrate the internal 4 MHz oscillator. It contains 6 bits to adjust the frequency up or down to achieve 4 MHz. The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7:
OSCCAL OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)

R/W-1 CAL5 bit 7 R/W-0 CAL4 R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 U-0 U-0 bit 0
bit 7-2
CAL5:CAL0: 6-bit Signed Oscillator Calibration bits 111111 = Maximum frequency 100000 = Center frequency 000000 = Minimum frequency Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
bit 1-0
DS41190A-page 16
Preliminary
PIC12F629/675
2.3 PCL and PCLATH
2.3.2 STACK
The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any RESET, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC12F629/675 family has an 8 level deep x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no STATUS bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
FIGURE 2-3:
PCH 12 PC 5 8 7
LOADING OF PC IN DIFFERENT SITUATIONS

PCL 0 Instruction with PCL as Destination ALU result
PCLATH<4:0>
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0

GOTO, CALL
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note Implementing a Table Read" (AN556).
Preliminary
DS41190A-page 17
PIC12F629/675
2.4 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although STATUS bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-4.
EXAMPLE 2-1:
movlw movwf clrf incf btfss goto
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING PIC12F629/675

Indirect Addressing 0 IRP(1) 7 FSR Register 0
Direct Addressing RP1(1) RP0 6 From Opcode
Bank Select Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
Not Used
7Fh Bank 0 For memory map detail see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. Bank 1 Bank 2 Bank 3
1FFh
DS41190A-page 18
Preliminary
PIC12F629/675
3.0 GPIO PORT
There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Note: Additional information on I/O ports may be found in the PICmicro Mid-Range Reference Manual, (DS33023) The TRISIO register controls the direction of the GP pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISIO register are maintained set when using them as analog inputs.
EXAMPLE 3-1:
bcf clrf movlw movwf bsf movlw movwf bcf STATUS,RP0 GPIO 07h CMCON STATUS,RP0 0Ch TRISIO STATUS,RP0
INITIALIZING GPIO
;Bank 0 ;Init GPIO ;Set GP<2:0> to ;digital IO ;Bank 1 ;Set GP<3:2> as inputs ;and set GP<5:4,1:0> ;as outputs ;Bank 0
3.1
GPIO and the TRISIO Registers
GPIO is an 6-bit wide, bi-directional port. The corresponding data direction register is TRISIO. Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., put the contents of the output latch on the selected pin). The exception is GP3, which is input only and its TRIS bit will always read as 1. Example 3-1 shows how to initialize GPIO. Reading the GPIO register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. GP3 reads 0 when MCLREN = 1.
3.2
Additional Pin Functions
Every GPIO pin on the PIC12F629/675 has an interrupt-on-change option and every GPIO pin, except GP3, has a weak pull-up option. The next two sections describe these functions.
3.2.1
WEAK PULL-UP
Each of the GPIO pins, except GP3, has an individually configurable weak internal pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 3-1. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU bit (OPTION<7>).
REGISTER 3-1:
WPU WEAK PULL-UP REGISTER (ADDRESS: 95h)

U-0 bit 7 U-0 R/W-1 WPU5 R/W-1 WPU4 U-0 R/W-1 WPU2 R/W-1 WPU1 R/W-1 WPU0 bit 0
bit 7-6 bit 5-4
Unimplemented: Read as 0 WPU<5:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Unimplemented: Read as 0 WPU<2:0>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global GPPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
bit 3 bit 2-0
Preliminary
DS41190A-page 19
PIC12F629/675
3.2.2 INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an interrupt-on-change pin. Control bits IOCBx enable or disable the interrupt function for each pin. Refer to Register 3-2. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of GPIO. The mismatch outputs of the last read are OR'd together to set, or clear, the GP Port Change Interrupt flag bit (GPIF) in the INTCON register. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of GPIO. This will end the mismatch condition. Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF. Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the GPIF interrupt flag may not get set.
REGISTER 3-2:
IOCB INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)

U-0 bit 7 U-0 R/W-0 IOCB5 R/W-0 IOCB4 R/W-0 IOCB3 R/W-0 IOCB2 R/W-0 IOCB1 R/W-0 IOCB0 bit 0
bit 7-6 bit 5-0
Unimplemented: Read as 0 IOCB<5:0>: Interrupt-on-Change GPIO Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global interrupt enables (GIE and GPIE) must be enabled for individual interrupts to be recognized. Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
DS41190A-page 20
Preliminary
PIC12F629/675
3.3 Pin Descriptions and Diagrams
FIGURE 3-1:
Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet.
BLOCK DIAGRAM OF GP0 AND GP1 PINS

Analog Input Mode Q Q GPPU VDD Weak
Data Bus WR WPU RD WPU
D CK
3.3.1
GP0/AN0/CIN+
Figure 3-1 shows the diagram for this pin. The GP0 pin is configurable to function as one of the following: a general purpose I/O an analog input for the A/D (PIC12F675 only) an analog input to the comparator
D WR PORT CK Q Q I/O pin D WR TRIS RD TRIS RD PORT D WR IOCB RD IOCB CK Q Q Q EN Q D EN Interrupt-on-Change D CK Q Q Analog Input Mode VSS VDD
3.3.2
GP1/AN1/CIN-/VREF
Figure 3-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: as a general purpose I/O an analog input for the A/D (PIC12F675 only) an analog input to the comparator a voltage reference input for the A/D (PIC12F675 only)
RD PORT To Comparator To A/D Converter
Preliminary
DS41190A-page 21
PIC12F629/675
3.3.3 GP2/AN2/T0CKI/INT/COUT 3.3.4 GP3/MCLR/VPP
Figure 3-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: a general purpose I/O an analog input for the A/D (PIC12F675 only) a digital output from the comparator the clock input for TMR0 an external edge triggered interrupt Figure 3-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: a general purpose input as Master Clear Reset
FIGURE 3-3:
Data Bus RESET
BLOCK DIAGRAM OF GP3

MCLRE VSS MCLRE VSS
FIGURE 3-2:
Data Bus WR WPU RD WPU D CK Q Q

Analog Input Mode VDD Weak GPPU Analog Input Mode VDD WR IOCB RD IOCB RD TRIS RD PORT D CK
I/O pin
Q Q Q EN Q D EN D
COUT Enable D WR PORT CK Q Q COUT 1 0 D WR TRIS RD TRIS RD PORT D WR IOCB RD IOCB CK Q Q Q CK Q Q
Interrupt-on-Change RD PORT
I/O pin
VSS Analog Input Mode
D EN
D EN
Interrupt-on-Change
RD PORT
To TMR0 To INT To A/D Converter
DS41190A-page 22
Preliminary
PIC12F629/675
3.3.5 GP4/AN3/T1G/OSC2/CLKOUT 3.3.6 GP5/T1CKI/OSC1/CLKIN
Figure 3-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: a general purpose I/O an analog input for the A/D (PIC12F675 only) a TMR1 gate input a crystal/resonator connection a clock output Figure 3-5 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: a general purpose I/O a TMR1 clock input a crystal/resonator connection a clock input
FIGURE 3-5: FIGURE 3-4: BLOCK DIAGRAM OF GP4

Analog Input Mode Data Bus WR WPU RD WPU D CK Q Q GPPU Oscillator Circuit OSC1 CLKOUT Enable FOSC/4 D WR PORT CK Q Q CLKOUT Enable VSS D WR TRIS RD TRIS RD PORT D WR IOCB RD IOCB CK Q Q Q EN Q D EN D CK Q INTOSC/ EXTRC/EC1(2) Q CLKOUT Enable Analog Input Mode RD TRIS RD PORT D WR IOCB RD IOCB CK Q 1 0 I/O pin D WR TRIS CK Q Q VDD WR PORT D CK Q Q

INTOSC Mode
CLK Modes VDD Weak
Data Bus WR WPU RD WPU
TMR1LPEN D CK Q Q GPPU Oscillator Circuit OSC2 VDD VDD Weak
I/O pin
VSS INTOSC Mode (1)
Q Q
D EN
D EN
Interrupt-on-Change
Interrupt-on-Change
RD PORT RD PORT To TMR1 or CLKGEN
To TMR1 T1G To A/D Converter Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. Note 1: When using Timer1 with LP oscillator, the Schmitt Trigger is by-passed.
Preliminary
DS41190A-page 23
PIC12F629/675
TABLE 3-1:
Address
05h 0Bh/8Bh 19h 81h 85h 95h 96h 9Fh
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO

Name Bit 7
GIE GPPU
Bit 6
PEIE COUT INTEDG ADCS2
Bit 5
GP5 T0IE T0CS TRIS5 WPU5 IOCB5 ADCS1
Bit 4
GP4 INTE CINV T0SE TRIS4 WPU4 IOCB4 ADCS0
Bit 3
GP3 GPIE CIS PSA TRIS3 IOCB3 ANS3
Bit 2
GP2 T0IF CM2 PS2 TRIS2 WPU2 IOCB2 ANS2
Bit 1
GP1 INTF CM1 PS1 TRIS1 WPU1 IOCB1 ANS1
Bit 0
GP0 GPIF CM0 PS0 TRIS0 WPU0 IOCB0 ANS0
Value on: POR, BOR

--xx xxxx 0000 0000 -0-0 0000 1111 1111 --11 1111 --11 -111 --00 0000 -000 1111
Value on all other RESETS

--uu uuuu 0000 000u -0-0 0000 1111 1111 --11 1111 --11 -111 --00 0000 -000 1111
GPIO INTCON CMCON OPTION_REG TRISIO WPU IOCB ANSEL
Legend: x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by GPIO.
DS41190A-page 24
Preliminary
PIC12F629/675
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge. Note: Counter mode has specific external clock requirements. Additional information on these requirements is available in the Mid-Range Reference PICmicroTM Manual, (DS33023).
Figure 4-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Note: Additional information on the Timer0 module is available in the PICmicroTM MidRange Reference Manual, (DS33023).
4.2
Timer0 Interrupt
4.1
Timer0 Operation
Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module Interrupt Service Routine before reenabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut-off during SLEEP.
FIGURE 4-1:
CLKOUT (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Data Bus 0 1 1 SYNC 2 Cycles 0 0 8-bit Prescaler 1 8 Set Flag bit T0IF on Overflow PSA TMR0 8
T0CKI pin T0SE T0CS
PSA
PS0 - PS2 Watchdog Timer
1 WDT Time-out 0
WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
PSA
Preliminary
DS41190A-page 25
PIC12F629/675
4.3 Using Timer0 with an External Clock
plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom-
REGISTER 4-1:
OPTION_REG OPTION REGISTER (ADDRESS: 81h)

R/W-1 GPPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the TIMER0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
DS41190A-page 26
Preliminary
PIC12F629/675
4.4 Prescaler
EXAMPLE 4-1:
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as prescaler throughout this Data Sheet. The prescaler assignment is controlled in software by the control bit PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS2:PS0 bits (OPTION_REG<2:0>). The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer.
CHANGING PRESCALER (TIMER0WDT)

;Bank 0 ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1
bcf STATUS,RP0 clrwdt clrf TMR0 bsf STATUS,RP0
movlw b00101111 ;Required if desired movwf OPTION_REG ; PS2:PS0 is clrwdt ; 000 or 001 ; movlw b00101xxx ;Set postscaler to movwf OPTION_REG ; desired WDT rate bcf STATUS,RP0 ;Bank 0
4.4.1
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed on the fly during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 4-1) must be executed when changing the prescaler assignment from Timer0 to WDT.
To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 4-2. This precaution must be taken even if the WDT is disabled.
EXAMPLE 4-2:
clrwdt bsf movlw
CHANGING PRESCALER (WDTTIMER0)

;Clear WDT and ; postscaler ;Bank 1
STATUS,RP0
movwf bcf
bxxxx0xxx ;Select TMR0, ; prescale, and ; clock source OPTION_REG ; STATUS,RP0 ;Bank 0
TABLE 4-1:
Address 01h 0Bh/8Bh 81h 85h Legend:
REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other RESETS
TMR0 INTCON OPTION_REG TRISIO
Timer0 Module Register GIE GPPU PEIE INTEDG T0IE T0CS TRIS5 INTE T0SE TRIS4 GPIE PSA TRIS3 T0IF PS2 TRIS2 INTF PS1 TRIS1 GPIF PS0 TRIS0
xxxx xxxx uuuu uuuu 0000 0000 0000 000u 1111 1111 1111 1111 --11 1111 --11 1111
= Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
Preliminary
DS41190A-page 27
PIC12F629/675
5.0 TIMER1 MODULE WITH GATE CONTROL
The Timer1 Control register (T1CON), shown in Register 5-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. Note: Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
The PIC12F629/675 devices have a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt on overflow from FFFFh to 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input (T1G) Optional LP oscillator
FIGURE 5-1:
TIMER1 BLOCK DIAGRAM

TMR1ON TMR1GE TMR1ON TMR1GE T1G
Set Flag bit TMR1IF on Overflow TMR1 0 TMR1H TMR1L 1 LP Oscillator OSC1 FOSC/4 Internal Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS<1:0> TMR1CS T1SYNC
Synchronized Clock Input
Synchronize Detect SLEEP Input
OSC2 INTOSC w/o CLKOUT T1OSCEN LPEN
DS41190A-page 28
Preliminary
PIC12F629/675
5.1 Timer1 Modes of Operation 5.2 Timer1 Interrupt
Timer1 can operate in one of three modes: 16-bit timer with prescaler 16-bit synchronous counter 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter and Timer modules, the counter/timer clock can be gated by the T1G input. If an external clock oscillator is needed (and the microcontroller is using the INTRC w/o CLKOUT), Timer1 can use the LP oscillator as a clock source. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1<0>) is set. To enable the interrupt on rollover, you must set these bits: Timer1 interrupt Enable bit (PIE1<0>) PEIE bit (INTCON<6>) GIE bit (INTCON<7>). The interrupt is cleared by clearing the TMR1IF in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
5.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4, or 8 divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
FIGURE 5-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
Preliminary
DS41190A-page 29
PIC12F629/675
REGISTER 5-1: T1CON TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0 bit 7 bit 7 bit 6 Unimplemented: Read as 0 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if T1G pin is low 0 = Timer1 is on T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1OSO/T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN
bit 5-4
bit 3
bit 2
bit 1
bit 0
DS41190A-page 30
Preliminary
PIC12F629/675
5.4 Timer1 Operation in Asynchronous Counter Mode
The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the system clock is derived from the internal oscillator. As with the system LP oscillator, the user must provide a software time delay to ensure proper oscillator start-up. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 5.4.1). 5.4.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
TABLE 5-1:
Osc Type LP
Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PICmicro Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR

Freq C1 C2
32 kHz 33 pF 33 pF 100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF These values are for design guidance only. Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
5.6
Timer1 Operation During SLEEP
5.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator.
Timer1 can only operate during SLEEP when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To setup the timer to wake the device: Timer1 must be on (T1CON<0>) TMR1IE bit (PIE1<0>) must be set PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit (INTCON<7>) is set, the device will wake-up and jump to the Interrupt Service Routine on an overflow.
TABLE 5-2:
Address 0Bh/8Bh 0Ch 0Eh 0Fh 10h 8Ch Legend: Name INTCON PIR1 TMR1L TMR1H T1CON PIE1
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Bit 7 GIE EEIF Bit 6 PEIE ADIF Bit 5 T0IE Bit 4 INTE Bit 3 GPIE CMIF Bit 2 T0IF Bit 1 INTF Bit 0 GPIF Value on POR Value on all other RESETS
0000 0000 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
TMR1IF 00-- 0--0 00-- 0--0
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register EEIE ADIE CMIE
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu TMR1IE 00-- 0--0 00-- 0--0
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Preliminary
DS41190A-page 31
PIC12F629/675
NOTES:
DS41190A-page 32
Preliminary
PIC12F629/675
6.0 COMPARATOR MODULE
The PIC12F629/675 devices have one analog comparator. The inputs to the comparator are multiplexed with the GP0 and GP1 pins. There is an on-chip Comparator Voltage Reference that can also be applied to an input of the comparator. In addition, GP2 can be configured as the comparator output. The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator.
REGISTER 6-1:
CMCON COMPARATOR CONTROL REGISTER (ADDRESS: 19h)

U-0 bit 7 R-0 COUT U-0 R/W-0 CINV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0
bit 7 bit 6
Unimplemented: Read as 0 COUT: Comparator Output bit When CINV = 0: 1 = VIN+ > VIN 0 = VIN+ < VIN When CINV = 1: 0 = VIN+ > VIN 1 = VIN+ < VIN Unimplemented: Read as 0 CINV: Comparator Output Inversion bit 1 = Output inverted 0 = Output not inverted CIS: Comparator Input Switch bit When CM2:CM0 = 110 or 101: 1 = VIN connects to CIN+ 0 = VIN connects to CINCM2:CM0: Comparator Mode bits Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
bit 5 bit 4
bit 3
bit 2-0
Preliminary
DS41190A-page 33
PIC12F629/675
6.1 Comparator Operation
TABLE 6-1:
A single comparator is shown in Figure 6-1, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 6-1 represent the uncertainty due to input offsets and response time. Note: To use AN<3:0> as analog inputs, the appropriate bits must be programmed in the ANSEL register.
OUTPUT STATE VS. INPUT CONDITIONS

CINV 0 0 1 1 COUT 0 1 1 0
Input Conditions VIN- > VIN+ VIN- < VIN+ VIN- > VIN+ VIN- < VIN+
FIGURE 6-1:
VIN+ VIN
SINGLE COMPARATOR
+ Output
The polarity of the comparator output can be inverted by setting the CINV bit (CMCON<4>). Clearing CINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 6-1.
VINVIN+
Output
Note:
CINV bit (CMCON<4>) is clear.
DS41190A-page 34
Preliminary
PIC12F629/675
6.2 Comparator Configuration
There are eight modes of operation for the comparator. The CMCON register, shown in Register 6-1, is used to select the mode. Figure 6-2 shows the eight possible modes. The TRISIO register controls the data direction of the comparator pins for each mode. If the comparator mode is changed, the comparator output level may not be valid for a specified period of time. Refer to the specifications in Section 12.0. Note: Comparator interrupts should be disabled during a comparator mode change. Otherwise, a false interrupt may occur.
FIGURE 6-2:
CM2:CM0 = 000
COMPARATOR I/O OPERATING MODES

Comparator Off (Lowest power) CM2:CM0 = 111
Comparator Reset (POR Default Value - low power)
GP1/CINGP0/CIN+ GP2/COUT
A A D Off (Read as 0)
D D D Off (Read as 0)
Comparator without Output CM2:CM0 = 010
Comparator w/o Output and with Internal Reference CM2:CM0 = 100
A A D COUT
A D D From CVREF Module COUT
Comparator with Output and Internal Reference CM2:CM0 = 011
Multiplexed Input with Internal Reference and Output CM2:CM0 = 101
A D D From CVREF Module COUT
A A D From CVREF Module CIS = 0 CIS = 1 COUT
Comparator with Output CM2:CM0 = 001
Multiplexed Input with Internal Reference CM2:CM0 = 110
A A D COUT
A A D From CVREF Module CIS = 0 CIS = 1 COUT
A = Analog Input, ports always reads 0 D = Digital Input CIS = Comparator Input Switch (CMCON<3>)
Preliminary
DS41190A-page 35
PIC12F629/675
6.3 Analog Input Connection Considerations
range by more than 0.6V in either direction, one of the diodes is forward biased and a latchup may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
A simplified circuit for an analog input is shown in Figure 6-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this
FIGURE 6-3:
ANALOG INPUT MODE

VDD Rs < 10K AIN VT = 0.6V RIC
VA
CPIN 5 pF
VT = 0.6V
Leakage 500 nA
Legend:
CPIN VT ILEAKAGE RIC RS VA
Vss = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to Various Junctions = Interconnect Resistance = Source Impedance = Analog Voltage The TRISIO<2> bit functions as an output enable/ disable for the GP2 pin while the comparator is in an output mode. Note 1: When reading the GPIO register, all pins configured as analog inputs will read as a 0. Pins configured as digital inputs will convert an analog input according to the TTL input specification. 2: Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified.
6.4
Comparator Output
The comparator output, COUT, is read through the CMCON register. This bit is read only. The comparator output may also be directly output to the GP2 pin in three of the eight possible modes, as shown in Figure 6-2. When in one of these modes, the output on GP2 is asynchronous to the internal clock. Figure 6-4 shows the comparator output block diagram.
FIGURE 6-4:
MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM

GP0/CIN+
To GP2/T0CKI pin To Data Bus RD CMCON Q D EN CINV
GP1/CINCVREF
CM2:CM0
Set CMIF bit
D EN RD CMCON RESET
DS41190A-page 36
Preliminary
PIC12F629/675
6.5 Comparator Reference
The following equations determine the output voltages: VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x VDD / 32) The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The internal reference signal is used for four of the eight Comparator modes. The VRCON register, Register 6-2, controls the voltage reference module shown in Figure 6-5.
6.5.2
VOLTAGE REFERENCE ACCURACY/ERROR
6.5.1
CONFIGURING THE VOLTAGE REFERENCE
The voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range.
The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 6-5) keep CVREF from approaching VSS or VDD. The Voltage Reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 12.0.
FIGURE 6-5:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages 8R R R R R
VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input VRR
VR3:VR0
6.6
Comparator Response Time
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Table 12-4).
While the comparator is enabled during SLEEP, an interrupt will wake-up the device. If the device wakes up from SLEEP, the contents of the CMCON and VRCON registers are not affected.
6.8
Effects of a RESET
6.7
Operation During SLEEP
Both the comparator and voltage reference, if enabled before entering SLEEP mode, remain active during SLEEP. This results in higher SLEEP currents than shown in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To minimize power consumption while in SLEEP mode, turn off the comparator, CM2:CM0 = 111, and voltage reference, VRCON<7> = 0.
A device RESET forces the CMCON and VRCON registers to their RESET states. This forces the comparator module to be in the Comparator Reset mode, CM2:CM0 = 000 and the voltage reference to its off state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible.
Preliminary
DS41190A-page 37
PIC12F629/675
REGISTER 6-2: VRCON VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
R/W-0 VREN bit 7 bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain Unimplemented: Read as '0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as '0' VR3:VR0: CVREF value selection 0 VR [3:0] 15 When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown U-0 R/W-0 VRR R/W-0 R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
bit 6 bit 5
bit 4 bit 3-0
6.9
Comparator Interrupts
The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<6>, to determine the actual change that has occurred. The CMIF bit, PIR1<3>, is the comparator interrupt flag. This bit must be reset in software by clearing it to 0. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE1<3>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are cleared, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON. This will end the mismatch condition. Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared. Note: If a change in the CMCON register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR1<3>) interrupt flag may not get set.
TABLE 6-2:
Address 0Bh/8Bh 0Ch 19h 8Ch 85h 99h Legend:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Bit 7 GIE EEIF EEIE VREN Bit 6 PEIE ADIF COUT ADIE Bit 5 T0IE TRIS5 VRR Bit 4 INTE CINV TRIS4 Bit 3 GPIE CMIF CIS CMIE TRIS3 VR3 Bit 2 T0IF CM2 TRIS2 VR2 Bit 1 INTF CM1 TRIS1 VR1 Bit 0 GPIF Value on POR Value on all other RESETS
Name INTCON PIR1 CMCON PIE1 TRISIO VRCON
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0 CM0 -0-0 0000 -0-0 0000
TMR1IE 00-- 0--0 00-- 0--0 TRIS0 VR0 --11 1111 --11 1111 0-0- 0000 0-0- 0000
x = unknown, u = unchanged, - = unimplemented, read as 0. Shaded cells are not used by the comparator module.
DS41190A-page 38
Preliminary
PIC12F629/675
7.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE (PIC12F675 ONLY)
The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. Figure 7-1 shows the block diagram of the A/D on the PIC12F675.
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC12F675 has four analog inputs, multiplexed into one sample and hold circuit.
FIGURE 7-1:
A/D BLOCK DIAGRAM

VDD
VCFG = 0
VREF
VCFG = 1
GP0/AN0 GP1/AN1/VREF GP2/AN2 GP4/AN3 GO/DONE ADFM CHS1:CHS0 ADON ADRESH VSS 10 ADRESL ADC 10
7.1
A/D Configuration and Operation
7.1.3
VOLTAGE REFERENCE
There are two registers available to control the functionality of the A/D module: 1. 2. ADCON0 (Register 7-1) ANSEL (Register 7-2)
7.1.1
ANALOG PORT PINS
There are two options for the voltage reference to the A/D converter: either VDD is used, or an analog voltage applied to VREF is used. The VCFG bit (ADCON0<6>) controls the voltage reference selection. If VCFG is set, then the voltage on the VREF pin is the reference; otherwise, VDD is the reference.
The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO bits control the operation of the A/D port pins. Set the corresponding TRISIO bits to set the pin output driver to its high impedance state. Likewise, set the corresponding ANS bit to disable the digital input buffer. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
7.1.4
CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source of the conversion clock is software selectable via the ADCS bits (ANSEL<6:4>). There are seven possible clock options: FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal RC oscillator)
7.1.2
CHANNEL SELECTION
There are four analog channels on the PIC12F675, AN0 through AN3. The CHS1:CHS0 bits (ADCON0<3:2>) control which channel is connected to the sample and hold circuit.
For correct conversion, the A/D conversion clock (1/TAD) must be selected to ensure a minimum TAD of 1.6 s. Table 7-1 shows a few TAD calculations for selected frequencies.
Preliminary
DS41190A-page 39
PIC12F629/675
TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency A/D Clock Source (TAD)
Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 s 2 TOSC 4 TOSC 100 200 ns(2) 800 ns(2) 1.0 s(2) 3.2 s 8 TOSC 001 400 ns(2) 1.6 s 2.0 s 6.4 s (2) 16 TOSC 101 800 ns 3.2 s 4.0 s 12.8 s(3) (3) 32 TOSC 010 1.6 s 6.4 s 8.0 s 25.6 s(3) (3) (3) 64 TOSC 110 3.2 s 12.8 s 16.0 s 51.2 s(3) (1,4) (1,4) (1,4) A/D RC x11 2 - 6 s 2 - 6 s 2 - 6 s 2 - 6 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be performed during SLEEP.
7.1.5
STARTING A CONVERSION
The A/D conversion is initiated by setting the GO/DONE bit (ADCON0<1>). When the conversion is complete, the A/D module: Clears the GO/DONE bit Sets the ADIF flag (PIR1<6>) Generates an interrupt (if enabled). If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a 2 TAD delay is required before another acquisition can be initiated. Following the delay, an input acquisition is automatically started on the selected channel. Note: The GO/DONE bit should not be set in the same instruction that turns on the A/D.
7.1.6
CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left or right shifted. The ADFM bit (ADCON0<7>) controls the output format. Figure 7-2 shows the output formats.
FIGURE 7-2:
10-BIT A/D RESULT FORMAT

ADRESH ADRESL LSB bit 0 bit 7 bit 0
(ADFM = 0)
MSB bit 7
10-bit A/D Result (ADFM = 1) bit 7 MSB bit 0 bit 7
Unimplemented: Read as 0 LSB bit 0
Unimplemented: Read as 0
10-bit A/D Result
DS41190A-page 40
Preliminary
PIC12F629/675
REGISTER 7-1: ADCON0 A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD Unimplemented: Read as zero CHS1:CHS0: Analog Channel Select bits 00 = Channel 00 (AN0) 01 = Channel 01 (AN1) 10 = Channel 02 (AN2) 11 = Channel 03 (AN3) GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 VCFG U-0 U-0 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
bit 6
bit 5-4 bit 3-2
bit 1
bit 0
Preliminary
DS41190A-page 41
PIC12F629/675
REGISTER 7-2: ANSEL ANALOG SELECT REGISTER (ADDRESS: 9Fh)
U-0 bit 7 bit 7 bit 6-4 Unimplemented: Read as 0. ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 ANS3:ANS0: Analog Select bits (Between analog or digital function on pins AN<3:0>, respectively.) 0 = Digital I/O; pin is assigned to port or special function 1 = Analog input; pin is assigned as analog input(1) Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change. The corresponding TRISIO bit must be set to Input mode in order to allow external control of the voltage on the pin. Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
bit 3-0
DS41190A-page 42
Preliminary
PIC12F629/675
7.2
7.2.1
A/D Acquisition Requirements

RECOMMENDED SOURCE IMPEDANCE
7.2.2
SAMPLING TIME CALCULATION
The maximum recommended impedance for analog sources is 2.5 k. This value is calculated based on the maximum leakage current of the input pin. The leakage current is 100 nA max., and the analog input voltage cannot be varied by more than 1/4 LSb or 250 V due to leakage. This places a requirement on the input impedance of 250 V/100 nA = 2.5 k.
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 7-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), this sampling must be done before the conversion can be started. To calculate the minimum sampling time, Equation 7-1 may be used. This equation assumes that 1/4 LSb error is used (4096 steps for the A/D). The 1/4 LSb error is the maximum error allowed for the A/D to meet its specified resolution. The CHOLD is assumed to be 25 pF for the 10-bit A/D.
FIGURE 7-3:
ANALOG INPUT MODEL

VDD VT = 0.6 V RIC @ 1k Sampling Switch SS RSS
Rs
Port Pin
VA
CPIN 5 pF
VT = 0.6 V
ILEAKAGE 100 nA
CHOLD = 25 pF VSS
Legend CPIN = input capacitance = threshold voltage VT ILEAKAGE = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (RSS) (kW)
Preliminary
DS41190A-page 43
PIC12F629/675
EQUATION 7-1: A/D SAMPLING TIME
T C TC ------------------ ( R I C + R SS + R S ) ------------------ ( R I C + R S S + R S ) C H O LD C HO L D 1 V RE F V REF 1 ----------- = V REF 1 e V H OL D = V R EF ------------- = ( V R E F ) 1 e 4096 4096
1 T C = C HOLD ( 1k + R SS + R S )In ----------- 4096
Example 7-1 shows the calculation of the minimum time required to charge CHOLD. This calculation is based on the following system assumptions: CHOLD = 25 pF RS = 2.5 kW 1/4 LSb error VDD = 5V RSS = 10 k (worst case) Temp (system max.) = 50C
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 2.5 k. This is required to meet the pin leakage specification. 4: After a conversion has completed, you must wait 2 TAD time before sampling can begin again. During this time, the holding capacitor is not connected to the selected A/D input channel.
EXAMPLE 7-1:
CALCULATING THE MINIMUM REQUIRED SAMPLE TIME
TACQ
TACQ
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Offset 5 s + TC + [(Temp - 25C)(0.05 ms/C)] Holding Capacitor Charging Time (CHOLD) (RIC + RSS + RS) In (1/4096) -25 pF (1 k +10 k + 2.5 k) In (1/4096) -25 pF (13.5 k) In (1/4096) -0.338 (-9.704)s 3.3 s 5 s + 3.3 s + [(50C - 25C)(0.05 s / C)] 8.3 s + 1.25 s 9.55 s
TC TC TC TC TC TC TACQ
= = = = = = =
TACQ TAC
= =
The temperature coefficient is only required for temperatures > 25C.
DS41190A-page 44
Preliminary
PIC12F629/675
7.3 A/D Operation During SLEEP
The A/D converter module can operate during SLEEP. This requires the A/D clock source to be set to the internal RC oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/DONE bit is cleared, and the result is loaded into the ADRESH:ADRESL registers. If the A/D interrupt is enabled, the device awakens from SLEEP. If the A/D interrupt is not enabled, the A/D module is turned off, although the ADON bit remains set. When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion to be aborted, and the A/D module is turned off. The ADON bit remains set.
7.4
Effects of RESET
A device RESET forces all registers to their RESET state. Thus the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged.
TABLE 7-2:
Address 05h 0Ch 1Eh 1Fh 85h 8Ch 9Eh 9Fh Name GPIO PIR1
SUMMARY OF A/D REGISTERS

Bit 7 GIE EEIF ADFM EEIE Bit 6 PEIE ADIF VCFG ADIE ADCS2 Bit 5 GPIO5 T0IE TRIS5 ADCS1 Bit 4 GPIO4 INTE TRIS4 ADCS0 Bit 3 GPIO3 GPIE CMIF CHS1 TRIS3 CMIE ANS3 Bit 2 GPIO2 T0IF CHS0 TRIS2 ANS2 Bit 1 GPIO1 INTF GO TRIS1 ANS1 Bit 0 GPIO0 GPIF Value on: POR, BOR Value on all other RESETS
--xx xxxx --uu uuuu 0000 0000 0000 000u
0Bh, 8Bh INTCON
TMR1IF 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu 00-- 0000 00-- 0000 --11 1111 --11 1111 ADON TRIS0
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result ADCON0 TRISIO PIE1 ANSEL
TMR1IE 00-- 0--0 00-- 0--0 ANS0 -000 1111 -000 1111
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D converter module.
Preliminary
DS41190A-page 45
PIC12F629/675
NOTES:
DS41190A-page 46
Preliminary
PIC12F629/675
8.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: EECON1 EECON2 (not a physically implemented register) EEDATA EEADR The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip to chip. Please refer to AC Specifications for exact limits. When the data memory is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory. Additional information on the Data EEPROM is available in the PICmicro Mid-Range Reference Manual, (DS33023).
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC12F629/675 devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh.
REGISTER 8-1:
EEDAT EEPROM DATA REGISTER (ADDRESS: 9Ah)

R/W-0 EEDAT7 bit 7 R/W-0 EEDAT6 R/W-0 EEDAT5 R/W-0 EEDAT4 R/W-0 EEDAT3 R/W-0 R/W-0 R/W-0 EEDAT0 bit 0 EEDAT2 EEDAT1
bit 7-0
EEDATn: Byte value to write to or read from Data EEPROM Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
REGISTER 8-2:
EEADR EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)

U-0 bit 7 R/W-0 EADR6 R/W-0 EADR5 R/W-0 EADR4 R/W-0 EADR3 R/W-0 EADR2 R/W-0 EADR1 R/W-0 EADR0 bit 0
bit 7 bit 6-0
Unimplemented: Should be set to '0' EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
Preliminary
DS41190A-page 47
PIC12F629/675
8.1 EEADR
The EEADR register can address up to a maximum of 128 bytes of data EEPROM. Only seven of the eight bits in the register (EEADR<6:0>) are required. The MSb (bit 7) is ignored. The upper bit should always be 0 to remain upward compatible with devices that have more data EEPROM memory. of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, following RESET, the user can check the WRERR bit, clear it, and rewrite the location. The data and address will be cleared, therefore, the EEDATA and EEADR registers will need to be reinitialized. Interrupt flag bit EEIF in the PIR1 register is set when write is complete. This bit must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the Data EEPROM write sequence.
8.2
EECON1 AND EECON2 REGISTERS
EECON1 is the control register with four low order bits physically implemented. The upper four bits are nonimplemented and read as '0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion
REGISTER 8-3:
EECON1 EEPROM CONTROL REGISTER (ADDRESS: 9Ch)

U-0 bit 7 U-0 U-0 U-0 R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 7-4 bit 3
Unimplemented: Read as 0 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOD detect) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an EEPROM read Legend: S = Bit can only be set R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
bit 2
bit 1
bit 0
DS41190A-page 48
Preliminary
PIC12F629/675
8.3 READING THE EEPROM DATA MEMORY
After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit (PIR<7>) register must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>), as shown in Example 8-1. The data is available, in the very next cycle, in the EEDATA register. Therefore, it can be read in the next instruction. EEDATA holds this value until another read, or until it is written to by the user (during a write operation).
8.5
WRITE VERIFY
EXAMPLE 8-1:
bsf movlw movwf bsf movf
DATA EEPROM READ

;Bank 1 ; ;Address to read ;EE Read ;Move data to W
STATUS,RP0 CONFIG_ADDR EEADR EECON1,RD EEDATA,W
Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be verified (see Example 8-3) to the desired value to be written.
EXAMPLE 8-3:
bcf : bsf movf bsf
WRITE VERIFY
;Bank 0 ;Any code ;Bank 1 READ ;EEDATA not changed ;from previous write ;YES, Read the ;value written ;Is data the same ;No, handle error ;Yes, continue
STATUS,RP0 STATUS,RP0 EEDATA,W EECON1,RD
8.4
WRITING TO THE EEPROM DATA MEMORY
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 8-2.
xorwf EEDATA,W btfss STATUS,Z goto WRITE_ERR :
EXAMPLE 8-2:
bsf bsf bcf movlw movwf movlw movwf bsf bsf
DATA EEPROM WRITE

;Bank 1 ;Enable write ;Disable INTs ;Unlock write ; ; ; ;Start the write ;Enable INTS
STATUS,RP0 EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE
8.5.1
MAXIMIZING ENDURANCE
For applications that will exceed 10% of the minimum specified cell endurance (parameters D120, D120A, D130, and D130A), every location should be refreshed within intervals not exceeding 1/10 of this specified cell endurance. Please refer to AN790 (DS00790) for more details.
Required Sequence
8.6
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.
PROTECTION AGAINST SPURIOUS WRITE
There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: brown-out power glitch software malfunction
Preliminary
DS41190A-page 49
PIC12F629/675
8.7 DATA EEPROM OPERATION DURING CODE PROTECT
Data memory can be code protected by programming the CPD bit to 0. When the data memory is code protected, the CPU is able to read and write data to the Data EEPROM. It is recommended to code protect the program memory when code protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations to 0 will also help prevent data memory code protection from becoming breached.
TABLE 8-1:
Address 0Ch 9Ah 9Bh 9Ch 9Dh
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Name Bit 7 EEIF Bit 6 ADIF Bit 5 Bit 4 Bit 3 CMIF Bit 2 Bit 1 Bit 0 Value on Value on all Power-on other Reset RESETS
PIR1 EEDATA EEADR EECON1
TMR1IF 00-- 0--0 00-- 0--0 0000 0000 0000 0000 -000 0000 -000 0000
EEPROM Data Register EEPROM Address Register WRERR WREN WR RD
---- x000 ---- q000 ---- ---- ---- ----
EECON2(1) EEPROM Control Register 2
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not used by Data EEPROM module. Note 1: EECON2 is not a physical register.
DS41190A-page 50
Preliminary
PIC12F629/675
9.0 SPECIAL FEATURES OF THE CPU
The PIC12F629/675 has a Watchdog Timer that is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in RESET while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can provide at least a 72 ms RESET. With these three functions on-chip, most applications need no external RESET circuitry. The SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through: External RESET Watchdog Timer wake-up An interrupt Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 9-1).
Certain special circuits that deal with the needs of real time applications are what sets a microcontroller apart from other processors. The PIC12F629/675 family has a host of such features intended to: maximize system reliability minimize cost through elimination of external components provide power saving operating modes and offer code protection. These features are: Oscillator selection RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-Up Timer (OST) - Brown-out Reset (BOR) Interrupts Watchdog Timer (WDT) SLEEP Code protection ID Locations In-Circuit Serial Programming
Preliminary
DS41190A-page 51
PIC12F629/675
9.1 Configuration Bits
Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h - 3FFFh), which can be accessed only during programming. See PIC12F629/675 Programming Specification for more information. The configuration bits can be programmed (read as 0), or left unprogrammed (read as 1) to select various device configurations, as shown in Register 9-1. These bits are mapped in program memory location 2007h.
REGISTER 9-1:
R/P-1 R/P-1 BG1 bit 13 BG0 U-0
CONFIG CONFIGURATION WORD (ADDRESS: 2007h)

U-0 U-0 R/P-1 CPD R/P-1 CP R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 bit 0
bit 13-12
bit 11-9 bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
BG1:BG0: Bandgap Calibration bits(1) 00 = Lowest bandgap voltage 11 = Highest bandgap voltage Unimplemented: Read as 0 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program Memory code protection is disabled 0 = Program Memory code protection is enabled BODEN: Brown-out Detect Enable bit(4) 1 = BOD enabled 0 = BOD disabled MCLRE: GP3/MCLR pin function select(5) 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 110 = RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN 010 = HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 000 = LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device. 2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program EEPROM will be erased, including OSCCAL value, when the code protection is turned off. 4: Enabling Brown-out Reset does not automatically enable Power-Up Timer. 5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. Legend: P = Programmed using ICSP R = Readable bit -n = Value at POR
W = Writable bit 1 = bit is set
U = Unimplemented bit, read as 0 0 = bit is cleared x = bit is unknown
DS41190A-page 52
Preliminary
PIC12F629/675
9.2
9.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 9-2:
The PIC12F629/675 can be operated in eight different oscillator option modes. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: LP Low Power Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor (2 modes) INTOSC Internal Oscillator (2 modes) EC External Clock In Note: Additional information on oscillator configurations is available in the PICmicroTM MidRange Reference Manual, (DS33023).
EXTERNAL CLOCK INPUT OPERATION (HS, XT, EC, OR LP OSC CONFIGURATION)
Clock from External System
OSC1 PIC12F629/675
Open
OSC2(1)
Note 1: Functions as GP4 in EC osc mode.
TABLE 9-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS

Ranges Characterized:
Mode XT
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1(C1) 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
OSC2(C2) 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
9.2.2
CRYSTAL OSCILLATOR / CERAMIC RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (see Figure 9-1). The PIC12F629/675 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may yield a frequency outside of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (see Figure 9-2).
HS
FIGURE 9-1:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)

OSC1 To Internal Logic XTAL OSC2 RF(3) SLEEP
Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
TABLE 9-2:
Mode LP XT
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR

Freq OSC1(C1) 68 - 100 pF 15 - 30 pF 68 - 150 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF OSC2(C2) 68 - 100 pF 15 - 30 pF 150 - 200 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF
C1
(1)
32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 8 MHz 10 MHz 20 MHz
C2(1) Note 1: 2: 3:
RS(2)
PIC12F629/675
See Table 9-1 and Table 9-2 for recommended values of C1 and C2. A series resistor may be required for AT strip cut crystals. RF varies with the oscillator mode selected (Approx. value = 10 M).
HS
Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
Preliminary
DS41190A-page 53
PIC12F629/675
9.2.3 EXTERNAL CLOCK IN 9.2.5 INTERNAL 4 MHZ OSCILLATOR
For applications where a clock is already available elsewhere, users may directly drive the PIC12F629/675 provided that this external clock source meets the AC/ DC timing requirements listed in Section 12.0. Figure 9-2 below shows how an external clock circuit should be configured. When calibrated, the internal oscillator provides a fixed 4 MHz (nominal) system clock. See Electrical Specifications, Section 12.0, for information on variation over voltage and temperature.
9.2.5.1
Calibrating the Internal Oscillator
9.2.4
RC OSCILLATOR
For applications where precise timing is not a requirement, the RC oscillator option is available. The operation and functionality of the RC oscillator is dependent upon a number of variables. The RC oscillator frequency is a function of: Supply voltage Resistor (REXT) and capacitor (CEXT) values Operating temperature. The oscillator frequency will vary from unit to unit due to normal process parameter variation. The difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to account for the tolerance of the external R and C components. Figure 9-3 shows how the R/C combination is connected.
A calibration instruction is programmed into the last location of program memory. This instruction is a RETLW XX, where the literal is the calibration value. The literal is placed in the OSCCAL register to set the calibration of the internal oscillator. Example 9-1 demonstrates how to calibrate the internal oscillator. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing part.
EXAMPLE 9-1:
bsf call movwf bcf
CALIBRATING THE INTERNAL OSCILLATOR

;Bank 1 ;Get the cal value ;Calibrate ;Bank 0
STATUS, RP0 3FFh OSCCAL STATUS, RP0
FIGURE 9-3:
VDD
RC OSCILLATOR MODE
9.2.6
CLKOUT
PIC12F629/675 REXT GP5/OSC1/ CLKIN Internal Clock
The PIC12F629/675 devices can be configured to provide a clock out signal in the INTOSC and RC oscillator modes. When configured, the oscillator frequency divided by four (FOSC/4) is output on the GP4/OSC2/ CLKOUT pin. FOSC/4 can be used for test purposes or to synchronize other logic.
CEXT VSS FOSC/4 GP4/OSC2/CLKOUT
DS41190A-page 54
Preliminary
PIC12F629/675
9.3 RESET
The PIC12F629/675 differentiates between various kinds of RESET: a) b) c) d) e) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation) Brown-out Detect (BOD) They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different RESET situations as indicated in Table 9-4. These bits are used in software to determine the nature of the RESET. See Table 9-7 for a full description of RESET states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 9-4. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Table 12-4 in Electrical Specifications Section for pulse width specification.
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a RESET state on: Power-on Reset MCLR Reset WDT Reset MCLR Reset during SLEEP Brown-out Detect (BOD) Reset
FIGURE 9-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset
MCLR/ VPP pin WDT Module VDD Rise Detect VDD Brown-out Detect WDT
SLEEP
Time-out Reset
Power-on Reset S
BODEN OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKIN pin PWRT On-chip(1) RC OSC 10-bit Ripple Counter
Chip_Reset R Q
Enable PWRT Enable OST
See Table 9-3 for time-out situations.
Note
1:
This is a separate oscillator from the INTRC/EC oscillator.
Preliminary
DS41190A-page 55
PIC12F629/675
9.3.1
MCLR
9.3.3
POWER-UP TIMER (PWRT)
PIC12F629/675 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 9-5, is suggested.
The Power-up Timer provides a fixed 72 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should always be enabled when Brown-out Reset is enabled. The Power-Up Time delay will vary from chip to chip and due to: VDD variation Temperature variation Process variation. See DC parameters for details.
FIGURE 9-5:
VDD
RECOMMENDED MCLR CIRCUIT

PIC12F629/675
9.3.4
OSCILLATOR START-UP TIMER (OST)
R1 1 k (or greater) MCLR
The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
C1 0.1 f (optional, not critical)
9.3.5 9.3.2 POWER-ON RESET (POR)
BROWN-OUT DETECT (BOD)
The on-chip POR circuit holds the chip in RESET until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details. Note: The POR circuit does not produce an internal RESET when VDD declines.
The PIC12F629/675 members have on-chip Brown-out Detect circuitry. A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brownout Detect circuitry. If VDD falls below VBOR for greater than parameter (TBOR) in Table 12-4 (see Section 12.0). The brown-out situation will reset the chip. A RESET is not guaranteed to occur if VDD falls below VBOR for less than parameter (TBOR). On any RESET (Power-on, Brown-out, Watchdog, etc.), the chip will remain in RESET until VDD rises above BVDD (see Figure 9-6). The Power-up Timer will now be invoked, if enabled, and will keep the chip in RESET an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above BVDD, the Power-Up Timer will execute a 72 ms RESET. The Power-up Timer should always be enabled when Brown-out Detect is enabled. Figure 9-6 shows typical Brown-out situations.
When the device starts normal operation (exits the RESET condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For additional information, refer to Application Note AN607 Power-up Trouble Shooting.
DS41190A-page 56
Preliminary
PIC12F629/675
FIGURE 9-6:
VDD VBOR
BROWN-OUT SITUATIONS
Internal RESET
72 ms(1)
VDD VBOR
Internal RESET
<72 ms
72 ms(1)
VDD
VBOR
Internal RESET
72 ms(1)
Note 1: 72 ms delay only if PWRTE bit is programmed to 0.
9.3.6
TIME-OUT SEQUENCE
9.3.7
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired. Then, OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 9-7, Figure 9-8 and Figure 9-9 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 9-8). This is useful for testing purposes or to synchronize more than one PIC12F629/675 device operating in parallel. Table 9-6 shows the RESET conditions for some special registers, while Table 9-7 shows the RESET conditions for all the registers.
POWER CONTROL (PCON) STATUS REGISTER
The power control/status register, PCON (address 8Eh) has two bits. Bit0 is BOD (Brown-out). BOD is unknown on Poweron Reset. It must then be set by the user and checked on subsequent RESETS to see if BOD = 0, indicating that a brown-out has occurred. The BOD status bit is a dont care and is not necessarily predictable if the brown-out circuit is disabled (by setting BODEN bit = 0 in the Configuration word). Bit1 is POR (Power-on Reset). It is a 0 on Power-on Reset and unaffected otherwise. The user must write a 1 to this bit following a Power-on Reset. On a subsequent RESET, if POR is 0, it will indicate that a Poweron Reset must have occurred (i.e., VDD may have gone too low).
Preliminary
DS41190A-page 57
PIC12F629/675
TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up Oscillator Configuration PWRTE = 0 XT, HS, LP RC, EC, INTOSC TPWRT + 1024TOSC TPWRT PWRTE = 1 1024TOSC PWRTE = 0 TPWRT + 1024TOSC TPWRT PWRTE = 1 1024TOSC Brown-out Reset Wake-up from SLEEP 1024TOSC
TABLE 9-4:
POR 0 1 u u u u
STATUS/PCON BITS AND THEIR SIGNIFICANCE

BOD u 0 u u u u TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Detect WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP
Legend: u = unchanged, x = unknown
TABLE 9-5:
Address 03h 8Eh
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Bit 7 IRP Bit 6 RP1 Bit 5 RPO Bit 4 TO Bit 3 PD Bit 2 Z Bit 1 DC POR Bit 0 C BOD Value on POR Reset Value on all other RESETS(1)
Name STATUS PCON
0001 1xxx 000q quuu ---- --0x ---- --uq
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
TABLE 9-6:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Detect Interrupt Wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as 0. Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
DS41190A-page 58
Preliminary
PIC12F629/675
TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset Brown-out Detect(1) uuuu uuuu uuuu uuuu 0000 0000 000q quuu uuuu uuuu --uu uuuu ---0 0000 0000 000u 00-- 0--0 -uuu uuuu -0-0 0000 uuuu uuuu 00-- 0000 1111 1111 --11 1111 00-- 0--0 ---- --uu
(1,6) (4)
Register
Address
Wake-up from SLEEP through interrupt Wake-up from SLEEP through WDT time-out uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu ---u uuuu uuuu uuqq(2) qq-- q--q(2,5) -uuu uuuu -u-u uuuu uuuu uuuu uu-- uuuu uuuu uuuu --uu uuuu uu-- u--u ---- --uu uuuu uu-uuuu uuuu --uu uuuu u-u- uuuu uuuu uuuu -uuu uuuu ---- uuuu ---- ---uuuu uuuu -uuu uuuu
W INDF TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 T1CON CMCON ADRESH ADCON0 OPTION_REG TRISIO PIE1 PCON OSCCAL WPU IOCB VRCON EEDATA EEADR EECON1 EECON2 ADRESL ANSEL Legend: Note 1: 2: 3:
00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 0Ah/8Ah 0Bh/8Bh 0Ch 10h 19h 1Eh 1Fh 81h 85h 8Ch 8Eh 90h 95h 96h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xxxx ---0 0000 0000 0000 00-- 0--0 -000 0000 -0-0 0000 xxxx xxxx 00-- 0000 1111 1111 --11 1111 00-- 0--0 ---- --0x 1000 00---11 -111 --00 0000 0-0- 0000 0000 0000 -000 0000 ---- x000 ---- ---xxxx xxxx -000 1111
1000 00---11 -111 --00 0000 0-0- 0000 0000 0000 -000 0000 ---- q000 ---- ---uuuu uuuu -000 1111
u = unchanged, x = unknown, - = unimplemented bit, reads as 0, q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 9-6 for RESET value for specific condition. 5: If wake-up was due to data EEPROM write completing, bit 7 = 1; A/D conversion completing, bit 6 = 1; Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a wake-up will cause these bits to = u. 6: If RESET was due to brown-out, then bit 0 = 0. All other RESETS will cause bit 0 = u.
Preliminary
DS41190A-page 59
PIC12F629/675
FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 9-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 9-9:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
TPWRT PWRT Time-out
TOST
OST Time-out
Internal RESET
DS41190A-page 60
Preliminary
PIC12F629/675
FIGURE 9-10: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 9-12:
VDD R1 Q1 D R R1 MCLR C PIC12F629/675 Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that:
VDD x R1 R1 + R2 = 0.7V
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2

VDD
VDD
VDD
MCLR PIC12F629/675
R2
40k
Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: < 40 k is recommended to make sure that voltage drop across R does not violate the devices electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
2: Internal Brown-out Reset should be R1 disabled when using this=circuit. 0.7 V Vdd x R1 be adjusted for the 3: Resistors should + R2 characteristics of the transistor.
FIGURE 9-13:
VDD
FIGURE 9-11:
VDD 33k

VDD
VDD MCP809 RST Vss
Bypass Capacitor
VDD
MCLR PIC12F629/675
10k 40k
MCLR PIC12F629/675
Note 1: This circuit will activate RESET when VDD goes below (Vz + 0.7 V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit.
This brown-out protection circuit employs Microchip Technologys MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs with both "active high and active low" RESET pins. There are 7 different trip point selections to accommodate 5.0V and 3.0V systems.
Preliminary
DS41190A-page 61
PIC12F629/675
9.4

Interrupts
The PIC12F629/675 has 7 sources of interrupt: External Interrupt GP2/INT TMR0 Overflow Interrupt GPIO Change Interrupts Comparator Interrupt A/D Interrupt (PIC12F675 only) TMR1 Overflow Interrupt EEPROM Data Write Interrupt
Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid GP2/INT recursive interrupts. For external interrupt events, such as the INT pin, or GP port change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 9-15). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.
The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register and PIE register. GIE is cleared on RESET. The return from interrupt instruction, RETFIE, exits interrupt routine, as well as sets the GIE bit, which reenables unmasked interrupts. The following interrupt flags are contained in the INTCON register: INT pin interrupt GP port change interrupt TMR0 overflow interrupt. The peripheral interrupt flags are contained in the special register PIR1. The corresponding interrupt enable bit is contained in Special Register PIE1. The following interrupt flags are contained in the PIR register: EEPROM data write interrupt A/D interrupt Comparator interrupt Timer1 overflow interrupt
When an interrupt is serviced: The GIE is cleared to disable any further interrupt The return address is pushed onto the stack The PC is loaded with 0004h.
DS41190A-page 62
Preliminary
PIC12F629/675
FIGURE 9-14:
IOC-GP0 IOCB0 IOC-GP1 IOCB1 IOC-GP2 IOCB2 IOC-GP3 IOCB3 IOC-GP4 IOCB4 IOC-GP5 IOCB5 T0IF T0IE INTF INTE GPIF GPIE PEIF PEIE
(1)
INTERRUPT LOGIC
Wake-up (If in SLEEP mode)
TMR1IF TMR1IE CMIF CMIE ADIF ADIE EEIF EEIE Note 1: PIC12F675 only.
Interrupt to CPU
GIE
Preliminary
DS41190A-page 63
PIC12F629/675
9.4.1 GP2/INT INTERRUPT 9.4.3 GPIO INTERRUPT
External interrupt on GP2/INT pin is edge-triggered; either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before reenabling this interrupt. The GP2/INT interrupt can wake-up the processor from SLEEP if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.7 for details on SLEEP and Figure 9-17 for timing of wakeup from SLEEP through GP2/INT interrupt. An input change on GPIO change sets the GPIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing the GPIE (INTCON<3>) bit. Plus individual pins can be configured through the IOCB register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the GPIF interrupt flag may not get set.
9.4.4
COMPARATOR INTERRUPT
See Section 6.9 for description of comparator interrupt.
9.4.5 9.4.2 TMR0 INTERRUPT

An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 4.0.
A/D CONVERTER INTERRUPT
After a conversion is complete, the ADIF flag (PIR<6>) is set. The interrupt can be enabled/disabled by setting or clearing ADIE (PIE<6>). See Section 7.0 for operation of the A/D converter interrupt.
FIGURE 9-15:
Q1 OSC1 CLKOUT 3
INT PIN INTERRUPT TIMING

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
4 INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed 1 5 1 Interrupt Latency 2
PC
PC+1 Inst (PC+1) Inst (PC)
PC+1 Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Inst (PC) Inst (PC-1)
Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.
DS41190A-page 64
Preliminary
PIC12F629/675
TABLE 9-8:
Address Name
SUMMARY OF INTERRUPT REGISTERS

Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE Bit 4 INTE Bit 3 GPIE CMIF CMIE Bit 2 T0IF Bit 1 INTF Bit 0 GPIF Value on POR Reset Value on all other RESETS
0Bh, 8Bh INTCON 0Ch 8Ch PIR1 PIE1
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0 TMR1IE 00-- 0--0 00-- 0--0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not used by the Interrupt module.
9.5
Context Saving During Interrupts
9.6
Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, e.g., W register and STATUS register. This must be implemented in software. Example 9-2 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x20 in Bank 0 and it must also be defined at 0xA0 in Bank 1). The user register, STATUS_TEMP, must be defined in Bank 0. The Example 9-2: Stores the W register Stores the STATUS register in Bank 0 Executes the ISR code Restores the STATUS (and bank select bit register) Restores the W register
The Watchdog Timer is a free running, on-chip RC oscillator, which requires no external components. This RC oscillator is separate from the external RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example, by execution of a SLEEP instruction). During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the configuration bit WDTE as clear (Section 9.1).
9.6.1
WDT PERIOD
EXAMPLE 9-2:
MOVWF SWAPF BCF W_TEMP STATUS,W STATUS,RP0
SAVING THE STATUS AND W REGISTERS IN RAM

;copy W to temp register, could be in either bank ;swap status to be saved into W ;change to bank 0 regardless of current bank ;save status to bank 0 register
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out.
MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into W, sets bank to original state MOVWF STATUS ;move W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W
9.6.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT time-out occurs.
Preliminary
DS41190A-page 65
PIC12F629/675
FIGURE 9-16:
CLKOUT (= FOSC/4) 0 1 1 T0CKI pin T0SE T0CS 1 8 0 8-bit Prescaler 0 Set Flag bit T0IF on Overflow PSA SYNC 2 Cycles TMR0
WATCHDOG TIMER BLOCK DIAGRAM

Data Bus 8
PSA
PS0 - PS2 Watchdog Timer
1 WDT Time-Out 0
WDTE
PSA
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
TABLE 9-9:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other RESETS
81h 2007h
OPTION_REG GPPU INTEDG Config. bits CP
T0CS
T0SE
PSA
PS2 F0SC2
PS1 F0SC1
PS0 F0SC0
1111 1111 1111 1111 uuuu uuuu uuuu uuuu
BODEN MCLRE PWRTE WDTE
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
DS41190A-page 66
Preliminary
PIC12F629/675
9.7 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: WDT will be cleared but keeps running PD bit in the STATUS register is cleared TO bit is set Oscillator driver is turned off I/O ports maintain the status they had before SLEEP was executed (driving high, low, or hi-impedance). The first event will cause a device RESET. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. TO bit is cleared if WDT Wake-up occurred. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from SLEEP. The SLEEP instruction is completely executed.
For lowest current consumption in this mode, all I/O pins should be either at VDD, or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on chip pull-ups on GPIO should be considered. The MCLR pin must be at a logic high level (VIHMC). Note: It should be noted that a RESET generated by a WDT time-out does not drive MCLR pin low.
The WDT is cleared when the device wakes up from SLEEP, regardless of the source of wake-up.
9.7.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin Watchdog Timer Wake-up (if WDT was enabled) Interrupt from GP2/INT pin, GPIO change, or a peripheral interrupt.
FIGURE 9-17:
WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Inst(PC) = SLEEP Inst(PC - 1) Processor in SLEEP
Interrupt Latency (Note 2)
PC+1 Inst(PC + 1) SLEEP
PC+2
PC+2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy cycle
Dummy cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024TOSC (drawing not to scale). Approximately 1 s delay will be there for RC osc mode. GIE = 1 assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC osc modes, but shown here for timing reference.
Preliminary
DS41190A-page 67
PIC12F629/675
9.8 Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: The entire data EEPROM and FLASH program memory will be erased when the code protection is turned off. The INTRC calibration data is also erased. See PIC12F629/675 Programming Specification for more information. After RESET, to place the device into Programming/ Verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure 9-18.
9.9
ID Locations
FIGURE 9-18:
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Only the Least Significant 4 bits of the ID locations are used.
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION

To Normal Connections PIC12F629/675
External Connector Signals +5V 0V VPP CLK Data I/O
9.10
In-Circuit Serial Programming
VDD VSS GP3/MCLR/VPP GP0 GP1
The PIC12F629/675 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for: power ground programming voltage This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the GP0 and GP1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH (see Programming Specification). GP0 becomes the programming clock and GP1 becomes the programming data. Both GP0 and GP1 are Schmitt Trigger inputs in this mode.
VDD
To Normal Connections
DS41190A-page 68
Preliminary
PIC12F629/675
10.0 INSTRUCTION SET SUMMARY
The PIC12F629/675 instruction set is highly orthogonal and is comprised of three basic categories: Byte-oriented operations Bit-oriented operations Literal and control operations Each PIC12 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 10-1, while the various opcode fields are summarized in Table 10-1. Table 10-2 lists the instructions recognized by the MPASMTM assembler. A complete description of each instruction is also available in the PICmicro MidRange Reference Manual (DS33023). For byte-oriented instructions, f represents a file register designator and d represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is zero, the result is placed in the W register. If d is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, b represents a bit field designator, which selects the bit affected by the operation, while f represents the address of the file in which the bit is located. For literal and control operations, k represents an 8-bit or 11-bit constant, or literal value One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future products, do not use the OPTION and TRIS instructions. For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended result that the condition that sets the GPIF flag would be cleared.
TABLE 10-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS

Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
PC TO PD
FIGURE 10-1:
GENERAL FORMAT FOR INSTRUCTIONS

0
Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value
CALL and GOTO instructions only
All instruction examples use the format 0xhh to represent a hexadecimal number, where h signifies a hexadecimal digit.
7 k (literal)
10.1
READ-MODIFY-WRITE OPERATIONS
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator d. A read operation is performed on a register even if the instruction writes to that register.
13
11 OPCODE
10 k (literal)
k = 11-bit immediate value
Preliminary
DS41190A-page 69
PIC12F629/675
TABLE 10-2:
Mnemonic, Operands
PIC12F629/675 INSTRUCTION SET

14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1
01 01 01 01 11 11 10 00 10 11 11 00 11 00 00 11 11 00bb 01bb 10bb 11bb 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 bfff bfff bfff bfff kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk ffff ffff ffff ffff kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
1,2 1,2 3 3 C,DC,Z Z TO,PD Z
LITERAL AND CONTROL OPERATIONS
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro Mid-Range MCU Family Reference Manual (DS33023).
DS41190A-page 70
Preliminary
PIC12F629/675
10.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal k and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [label] BCF 0 f 127 0b7 0 (f<b>) None Bit 'b' in register 'f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [label] BSF 0 f 127 0b7 1 (f<b>) None Bit 'b' in register 'f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are ANDed with the eight-bit literal 'k'. The result is placed in the W register. k
BTFSS Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f<b>) = 1 None If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f<b>) = 0 None If bit 'b' in register 'f' is '1', the next instruction is executed. If bit 'b', in register 'f', is '0', the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.
Preliminary
DS41190A-page 71
PIC12F629/675
CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [label] CLRF 0 f 127 00h (f) 1Z Z The contents of register f are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register f are complemented. If d is 0, the result is stored in W. If d is 1, the result is stored back in register f. f,d
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f.
DS41190A-page 72
Preliminary
PIC12F629/675
DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register f are decremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead, making it a 2TCY instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead, making it a 2TCY instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are ORed with the eight-bit literal 'k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
Preliminary
DS41190A-page 73
PIC12F629/675
MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. NOP Syntax: Operands: Operation: Status Affected: Description: No Operation [ label ] None No operation None No operation. NOP
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight-bit literal k is loaded into W register. The dont cares will assemble as 0s. MOVLW k 0 k 255
RETFIE Syntax: Operands: Operation: Status Affected:
Return from Interrupt [ label ] None TOS PC, 1 GIE None RETFIE
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] (W) (f) None Move data from W register to register 'f'. MOVWF f 0 f 127
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
DS41190A-page 74
Preliminary
PIC12F629/675
RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF 0 f 127 d [0,1] See description below C The contents of register f are rotated one bit to the left through the Carry Flag. If d is 0, the result is placed in the W register. If d is 1, the result is stored back in register f.
C Register f
SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped.
f,d
Status Affected: Description:
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
SUBLW Syntax: Operands: Operation: Description:
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2s complement method) from the eight-bit literal 'k'. The result is placed in the W register.
Status Affected: C, DC, Z
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register f are rotated one bit to the right through the Carry Flag. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f.
C Register f
SUBWF Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) C, DC, Z Subtract (2s complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
Preliminary
DS41190A-page 75
PIC12F629/675
SWAPF Syntax: Operands: Operation: Status Affected: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register f are exchanged. If d is 0, the result is placed in the W register. If d is 1, the result is placed in register f. XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XORed with the eight-bit literal 'k'. The result is placed in the W register.
DS41190A-page 76
Preliminary
PIC12F629/675
11.0 DEVELOPMENT SUPPORT
The MPLAB IDE allows you to: Edit your source files (either assembly or C) One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro microcontrollers are supported with a full range of hardware and software development tools: Integrated Development Environment - MPLAB IDE Software Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian Simulators - MPLAB SIM Software Simulator Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPIC In-Circuit Emulator In-Circuit Debugger - MPLAB ICD Device Programmers - PRO MATE II Universal Device Programmer - PICSTART Plus Entry-Level Development Programmer Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ Demonstration Board
11.2
MPASM Assembler
The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCUs. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: Integration into MPLAB IDE projects. User-defined macros to streamline assembly code. Conditional assembly for multi-purpose source files. Directives that allow complete control over the assembly process.
11.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows-based application that contains: An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) A full-featured editor A project manager Customizable toolbar and key mapping A status bar On-line help
11.3
MPLAB C17 and MPLAB C18 C Compilers
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchips PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
Preliminary
DS41190A-page 77
PIC12F629/675
11.4 MPLINK Object Linker/ MPLIB Object Librarian 11.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: Easier linking because single libraries can be included instead of many smaller files. Helps keep code maintainable by grouping related modules together. Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted.
The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft Windows environment were chosen to best make these features available to you, the end user.
11.7
ICEPIC In-Circuit Emulator
11.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool.
The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.
DS41190A-page 78
Preliminary
PIC12F629/675
11.8 MPLAB ICD In-Circuit Debugger
Microchips In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchips In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime.
11.11 PICDEM 1 Low Cost PICmicro Demonstration Board

The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchips microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB.
11.9
PRO MATE II Universal Device Programmer
The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode.
11.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board

The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad.
11.10 PICSTART Plus Entry Level Development Programmer

The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
Preliminary
DS41190A-page 79
PIC12F629/675
11.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexor LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
11.14 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
11.15 KEELOQ Evaluation and Programming Tools

KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters.
DS41190A-page 80
Preliminary
24CXX/ 25CXX/ 93CXX
PIC14000
HCSXXX
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
PIC16F62X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
PIC18FXXX
MCRFXXX
MCP2510
TABLE 11-1:
MPLAB Integrated Development Environment
9 9
9 9
MPLAB C17 C Compiler
Software Tools
MPLAB C18 C Compiler
MPASMTM Assembler/ MPLINKTM Object Linker
Programmers Debugger Emulators
Demo Boards and Eval Kits
9 9 9
9 9 9
9 9
**
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
9 9
MPLAB ICE In-Circuit Emulator
ICEPICTM In-Circuit Emulator
9
* *
MPLAB ICD In-Circuit Debugger
9
**
PICSTART Plus Entry Level Development Programmer
9
**
PRO MATE II Universal Device Programmer
DEVELOPMENT TOOLS FROM MICROCHIP
Preliminary
9 9 9 9 9

PICDEMTM 1 Demonstration Board
PICDEMTM 14A Demonstration Board
KEELOQ Evaluation Kit
9 9
KEELOQ Transponder Kit
microIDTM Programmers Kit
9 9
125 kHz microIDTM Developers Kit
125 kHz Anticollision microIDTM Developers Kit
13.56 MHz Anticollision microIDTM Developers Kit
PIC12F629/675
DS41190A-page 81
MCP2510 CAN Developers Kit
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
PIC12F629/675
NOTES:
DS41190A-page 82
Preliminary
PIC12F629/675
12.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Ambient temperature under bias........................................................................................................... -40 to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ..................................................................................................... -0.3 to +6.5V Voltage on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ..................................................................................................................... 300 mA Maximum current into VDD pin ........................................................................................................................ 250 mA Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)......................................................................................................... 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by all GPIO ................................................................................................................ 125 mA Maximum current sourced all GPIO ................................................................................................................ 125 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS
Preliminary
DS41190A-page 83
PIC12F629/675
FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20
Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-2:
PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20
DS41190A-page 84
Preliminary
PIC12F629/675
FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0C TA +85C
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.2 2.0 0 4 8 10 12 16 20
FIGURE 12-4:
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0
PIC12F629/675 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
12 Frequency (MHz)
16
20
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
Preliminary
DS41190A-page 85
PIC12F629/675
12.1 DC Characteristics: PIC12F629/675-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min Typ Max Units Conditions FOSC < = 4 MHz: PIC12F629/675 with A/D off PIC12F675 with A/D on, 0C to 85C PIC12F675 with A/D on, -40C to 85C 4 MHZ < FOSC < = 10 MHz Device in SLEEP mode See section on Power-on Reset for details DC CHARACTERISTICS Param No. D001 D001A D001B D001C D001D D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Supply Current(2,3) Sym VDD Characteristic Supply Voltage 2.0 2.2 2.5 3.0 4.5 1.5* VSS 5.5 5.5 5.5 5.5 5.5 V V V V V V V
D004
SVDD
0.05*
V/ms See section on Power-on Reset for details
D005 D010 D011 D012 D013
VBOR IDD
2.0 0.4 20 0.9 5.2
2.0 48 4 15
V mA A mA mA XT, RC osc configurations FOSC = 4 MHz, VDD = 2.0V LP osc configuration FOSC = 32 kHz, VDD = 2.0V, WDT disabled XT, RC osc configurations FOSC = 4 MHz, VDD = 5.5V HS osc configuration FOSC = 20 MHz, VDD = 5.5V VDD = 2.0V, WDT disabled VDD = 5.5V, BOR enabled VDD = 2.0V, Comparator enabled VDD = 2.0V, A/D on, not converting VDD = 2.0V, Timer1 on, 32 kHz ext. drive VDD = 2.0V, CVREF enabled VDD = 2.0V, WDT enabled
IPD D020 D021 D022 D023 D024 D025 D026
Power Down Current(4) 0.9 1 TBD 153 18 A A A A A A A
TBD TBD TBD TBD TBD TBD 5 TBD
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. 3: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 4: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
DS41190A-page 86
Preliminary
PIC12F629/675
12.2 DC Characteristics: PIC12F629/675-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for industrial Min 4.5 1.5* Typ Max Units VSS 5.5 V V V Conditions -40C to +125C Device in SLEEP mode See section on Power-on Reset for details DC CHARACTERISTICS Param No. D002 D003 Sym Characteristic Supply Voltage RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Supply Current(2,3)
D001A VDD VDR VPOR
D004
SVDD
0.05*
V/ms See section on Power-on Reset for details
D005 D012 D013
VBOR IDD
2.0 0.9 5.2
4 15
V mA mA XT, RC osc configurations FOSC = 4 MHz, VDD = 5.5V HS osc configuration FOSC = 20 MHz, VDD = 5.5V VDD = 4.5V, WDT disabled VDD = 5.0V, BOR enabled VDD = 4.5V, Comparator enabled VDD = 4.5V, A/D on, not converting VDD = 4.5V, Timer1 on, 32 kHz ext. drive VDD = 4.5V, CVREF enabled VDD = 4.5V, WDT enabled
IPD D020 D021 D022 D023 D024 D025 D026
Power Down Current(4) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 12 TBD A A A A A A A
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. 3: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 4: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
Preliminary
DS41190A-page 87
PIC12F629/675
12.3 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions DC CHARACTERISTICS Param Sym No. VIL D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B D070 IPUR D060 D060A D060B D061 D063 IIL
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes) OSC1 (HS mode) Input High Voltage I/O ports with TTL buffer
VSS VSS VSS VSS VSS VSS
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD
V V V V V V
4.5V VDD 5.5V Otherwise Entire range (Note 1) (Note 1)
2.0 (0.25 VDD+0.8) with Schmitt Trigger buffer 0.8VDD MCLR, GP2/AN2/T0CKI/ 0.8VDD INT/COUT OSC1 (XT and LP modes) 1.6 OSC1 (HS mode) 0.7VDD OSC1 (RC mode) 0.9VDD GPIO Weak Pull-up Current 50* Input Leakage Current(3) I/O ports Analog inputs VREF MCLR(2) OSC1 Output Low Voltage I/O ports OSC2/CLKOUT Output High Voltage I/O ports OSC2/CLKOUT

VDD VDD VDD VDD VDD VDD VDD 400* 1 TBD TBD 5 5
V V V V V V A A A A A A
4.5 V VDD 5.5 V otherwise entire range
(Note 1) (Note 1) VDD = 5.0 V, VPIN = VSS Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V (Ind.) IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.) IOH = -3.0 mA, VDD = 4.5V (Ind.) IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.)
250

D080 D083
VOL
0.6 0.6
V V
D090 D092
VOH
VDD-0.7 VDD-0.7
V V
* These parameters are characterized but not tested. Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
DS41190A-page 88
Preliminary
PIC12F629/675
12.3 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Capacitive Loading Specs on Output Pins OSC2 pin Min Typ Max Units Conditions DC CHARACTERISTICS Param No.
Sym
D100
COSC2
15*
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101 D101A D101B D120 D120A D121
CIO CAN CVR ED ED VDRW
All I/O pins All analog input pins VREF Data EEPROM Memory Cell Endurance(1) Cell Endurance(1) VDD for read VDD for Erase/Write Erase/Write cycle time Program FLASH Memory Endurance(1) Endurance(1) VDD for read
100K 10K VMIN 4.5 10K 1000 VMIN
1M 100K 4 100K 10K
50* TBD TBD 5.5 5.5 8 5.5
pF pF pF E/W -40C TA +85C E/W +85C TA +125C V VMIN = Minimum operating voltage V ms E/W -40C TA +85C E/W +85C TA +125C V VMIN = Minimum operating voltage V ms
D122 D130 D130A D131 D132 D133
TDEW EP EP VPR
4.5 5.5 VPEW VDD for Erase/Write TPEW Erase/Write cycle time 2 4 * These parameters are characterized but not tested. Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: See Section 8.5.1 for additional information.
Preliminary
DS41190A-page 89
PIC12F629/675
12.4 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid Hi-impedance
FIGURE 12-5:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
Pin VSS
RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins for OSC2 output
DS41190A-page 90
Preliminary
PIC12F629/675
12.5 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED)
EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 12-6:
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 12-1:
Param No. Sym FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS

Characteristic External CLKIN Frequency(1) Min DC DC DC DC 5 TBD 0.1 1 Typ 4 250 Max 200 4 20 20 200 4 4 20 200 TBD 10,000 1,000 Units kHz MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns Conditions LP osc mode XT mode HS mode EC mode LP osc mode INTRC mode RC osc mode XT osc mode HS osc mode LP osc mode HS osc mode EC osc mode XT osc mode LP osc mode INTRC mode RC osc mode XT osc mode HS osc mode
Oscillator Frequency(1)
TOSC
External CLKIN Period(1)
Oscillator Period(1)
5 50 50 250 5 250 250 50
200 TCY DC ns TCY = 4/FOSC 2* s LP oscillator, TOSC L/H duty cycle 20* ns HS oscillator, TOSC L/H duty cycle 100 * ns XT oscillator, TOSC L/H duty cycle 4 TosR, External CLKIN Rise 50* ns LP oscillator TosF External CLKIN Fall 25* ns XT oscillator 15* ns HS oscillator * These parameters are characterized but not tested. Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 3 TosL, TosH
TCY
Instruction Cycle Time(1) External CLKIN (OSC1) High External CLKIN Low
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at min values with an external clock applied to OSC1 pin. When an external clock input is used, the max cycle time limit is DC (no clock) for all devices.
Preliminary
DS41190A-page 91
PIC12F629/675
TABLE 12-2: CALIBRATED INTERNAL RC FREQUENCIES
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (Industrial), -40C TA +125C (Extended) Operating Voltage VDD range is described in Section 12.1 and Section 12.2. Characteristic Internal Calibrated RC Frequency Internal Calibrated RC Frequency Min* 3.92 3.80 Typ(1) 4.00 4.00 Max* 4.08 4.20 Units Conditions AC Characteristics
Param No.
Sym
MHz VDD = 5.0V, +85C (Ind.) VDD = 5.0V, +125C (Ext.) MHz 2.5V VDD 5.5V -40C TA +85C (Ind.) -40C TA +125C (Ext.)
* These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41190A-page 92
Preliminary
PIC12F629/675
FIGURE 12-7: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 15 New Value 19 18 22 23 12 16 Q1 Q2 11 Q3
TABLE 12-3:
Param No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 *
CLKOUT AND I/O TIMING REQUIREMENTS

Sym TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time GPIO change INT high or low time Min TOSC + 200 ns 0 100 0 25 TCY Typ 75 75 35 35 50 10 10 Max 200 200 100 100 20 150 * 300 40 40 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
These parameters are characterized but not tested. Data in Typ column is at 5.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.
Preliminary
DS41190A-page 93
PIC12F629/675
FIGURE 12-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer Reset 34 I/O Pins 32 30
31 34
FIGURE 12-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD BVDD (Device in Brown-out Reset) (Device not in Brown-out Reset)
35
RESET (due to BOR)
72 ms time out(1)
Note 1: 72 ms delay only if PWRTE bit in configuration word is programmed to 0.
DS41190A-page 94
Preliminary
PIC12F629/675
TABLE 12-4:
Param No. 30 31
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Hysteresis Brown-out Reset Pulse Width Min 2 TBD 7* TBD 28* TBD 2.0 TBD 100* s VDD BVDD (D005) Typ TBD 18 TBD 1024TOSC 72 TBD Max TBD 33* TBD 132* TBD 2.0 2.1 Units s ms ms ms ms ms s V Conditions VDD = 5V, -40C to +85C Extended temperature VDD = 5V, -40C to +85C Extended temperature TOSC = OSC1 period VDD = 5V, -40C to +85C Extended Temperature
TMCL TWDT
32 33* 34
TOST TPWRT TIOZ BVDD
35
TBOR
* These parameters are characterized but not tested. Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Preliminary
DS41190A-page 95
PIC12F629/675
FIGURE 12-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 42 41
T1CKI 45 47 TMR0 or TMR1 46 48
TABLE 12-5:
Param No. 40* 41* 42* Sym TT0H TT0L TT0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 DC 2 TOSC* Synchronous, with Prescaler Asynchronous Typ Max Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Time Synchronous, No Prescaler
200* 7 TOSC*
ns ns ns ns ns ns ns ns kHz N = prescale value (1, 2, 4, 8)
46*
TT1L
T1CKI Low Time
Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
47*
TT1P
T1CKI Input Period
Synchronous
Asynchronous FT1 48 * Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
These parameters are characterized but not tested. Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41190A-page 96
Preliminary
PIC12F629/675
TABLE 12-6: COMPARATOR SPECIFICATIONS
Standard Operating Conditions -40C to +125C (unless otherwise stated) Min 0 +55* Typ 5.0 150 Max 10 VDD - 1.5 400* 10* Units mV V db ns s Comments Comparator Specifications Sym VOS VCM CMRR TRT Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1)
TMC2COV Comparator Mode Change to Output Valid
* These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD.
TABLE 12-7:
COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Standard Operating Conditions -40C to +125C (unless otherwise stated) Min Typ VDD/24* VDD/32 2k* Max 1/4* 1/2* 10* Units LSb LSb LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
Voltage Reference Specifications Sym Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time
(1)
* These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
Preliminary
DS41190A-page 97
PIC12F629/675
TABLE 12-8:
Param No. A01 A02 A03 A04 A05 A06 A07 A10 A21 A25 A30 Sym NR EABS EIL EDL EFS EOFF EGN VREF VAIN ZAIN
PIC12F675 A/D CONVERTER CHARACTERISTICS:

Characteristic Resolution Total Absolute Error* Integral Error Differential Error Full Scale Range Offset Error Gain Error Monotonicity Reference V High (VDD or VREF) Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current(2) Min 2.2* VSS VSS Typ guaranteed(3) Max 10 bits TBD TBD TBD 5.5* TBD TBD VDD VREF 2.5 Units bit LSb LSb LSb V LSb LSb V V k VREF = 3.0V VREF = 3.0V VSS VAIN VREF+ VREF = 3.0V VREF = 3.0V No missing codes to 10 bits VREF = 3.0V Conditions
A50
IREF
10
1000 10
A A
During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle.
These parameters are characterized but not tested. Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from External VREF or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS41190A-page 98
Preliminary
PIC12F629/675
FIGURE 12-11: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY 131 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLE 132 SAMPLING STOPPED 9 8 OLD_DATA 7 6 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0, GO 134 Q4
(TOSC/2)(1)
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 12-9:
Param No. 130 130 Sym TAD TAD
PIC12F675 A/D CONVERSION REQUIREMENTS

Characteristic A/D Clock Period A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min 1.6 3.0* 3.0* 2.0* Typ 6.0 4.0 11 Max 9.0* 6.0* Units s s s s TAD Conditions TOSC based, VREF 3.0V TOSC based, VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V Set GO bit to new data in A/D result register
131
TCNV
132
TACQ
(Note 2) 5*
11.5
s s The minimum time is the amplifier settling time. This may be used if the new input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096 V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
TOSC/2
* These parameters are characterized but not tested. Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 7.1 for minimum conditions.
Preliminary
DS41190A-page 99
PIC12F629/675
FIGURE 12-12: PIC12F675 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO 134 Q4 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLE 132 SAMPLING STOPPED 9 8 7 6 3 2 1 0 NEW_DATA 1 TCY DONE
(TOSC/2 + TCY)(1)
131
1 TCY
OLD_DATA
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)

Param No. 130 130 Sym TAD TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min 1.6 3.0* 3.0* 2.0* 131 TCNV Typ 6.0 4.0 11 Max 9.0* 6.0* Units s s s s TAD Conditions VREF 3.0V VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V
132
TACQ
(Note 2) 5*
11.5
s s The minimum time is the amplifier settling time. This may be used if the new input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
TOSC/2 + TCY
These parameters are characterized but not tested. Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 7.1 for minimum conditions.
DS41190A-page 100
Preliminary
PIC12F629/675
13.0
13.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (Skinny DIP) XXXXXXXX XXXXXNNN YYWW Example 12F629-I /017 0215
8-Lead SOIC XXXXXXXX XXXXYYWW NNN
Example 12F629-E /0215 017
8-Lead MLF-S XXXXXXX XXXXXXX XXYYWW NNN
Example 12F629 -E/021 0215 017
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week 01) Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
Preliminary
DS41190A-page 101
PIC12F629/675
13.2 Package Details
The following sections give the technical details of the packages.
8-Lead Plastic Dual In-line (P) 300 mil (PDIP)
E1
D 2 n 1
A2
L A1
B1 p eB B
Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
MIN
INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10
MAX
MIN
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010 (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
DS41190A-page 102
Preliminary
PIC12F629/675
8-Lead Plastic Small Outline (SN) Narrow, 150 mil (SOIC)
E E1
D 2 B n 1
45
c A A2
A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010 (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
Preliminary
DS41190A-page 103
PIC12F629/675
8-Lead Plastic Micro Leadframe Package (MF) 6x5 mm Body (MLF-S)
E E1 n L B p
R D1 D D2
2 TOP VIEW
EXPOSED METAL PADS E2 BOTTOM VIEW
PIN 1 ID
A2 A3 A
A1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Length Molded Package Length Exposed Pad Length Overall Width Molded Package Width Exposed Pad Width Lead Width Lead Length Tie Bar Width Mold Draft Angle Top *Controlling Parameter n p A A2 A1 A3 E E1 E2 D D1 D2 B L R .085 .014 .020 .152 .000 MIN
INCHES NOM 8 .050 BSC .033 .026 .0004 .008 REF. .194 BSC .184 BSC .158 .236 BSC .226 BSC .091 .016 .024 .014 12 .097 .019 .030 .163 .039 .031 .002 MAX MIN
MILLIMETERS* NOM 8 1.27 BSC 0.85 0.65 0.00 0.01 0.20 REF. 4.92 BSC 4.67 BSC 3.85 4.00 5.99 BSC 5.74 BSC 2.16 0.35 0.50 2.31 0.40 0.60 .356 12 2.46 0.47 0.75 4.15 1.00 0.80 0.05 MAX
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010 (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-113
DS41190A-page 104
Preliminary
PIC12F629/675
8-Lead Plastic Micro Leadframe Package (MF) 6x5 mm Body (MLF-S)
M SOLDER MASK
PACKAGE EDGE L
Units Pitch Pad Width Pad Length Pad to Solder Mask *Controlling Parameter Drawing No. C04-2113 Dimension Limits p B L M MIN .014 .020 .005
INCHES NOM .050 BSC .016 .024 .019 .030 .006 MAX MIN
MILLIMETERS* NOM 1.27 BSC 0.35 0.50 0.13 0.40 0.60 0.47 0.75 0.15 MAX
Preliminary
DS41190A-page 105
PIC12F629/675
NOTES:
DS41190A-page 106
Preliminary
PIC12F629/675
APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
APPENDIX B:
DEVICE DIFFERENCES
The differences between the PIC12F629/675 devices listed in this data sheet are shown in Table B-1.
TABLE B-1:
Feature A/D
DEVICE DIFFERENCES
PIC12F629 No PIC12F675 Yes
Preliminary
DS41190A-page 107
PIC12F629/675
APPENDIX C: DEVICE MIGRATIONS APPENDIX D:
This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable
MIGRATING FROM OTHER PICmicro DEVICES
This discusses some of the issues in migrating from other PICmicro devices to the PIC12F6XX family of devices.
D.1
PIC12C67X to PIC12F6XX
for availability
See Microchip website (www.microchip.com).
Note:
This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
DS41190A-page 108
Preliminary
PIC12F629/675
APPENDIX E: DEVELOPMENT TOOL VERSION REQUIREMENTS
This lists the minimum requirements (software/ firmware) of the specified development tool to support the devices listed in this data sheet. MPLAB IDE: MPLAB MPLAB SIMULATOR: ICE 3000: TBD TBD
PIC12F629/675 Processor Module: Part Number TBD PIC12F629/675 Device Adapter: Socket Part Number 8-pin SOIC TBD 8-pin PDIP TBD 8-pin MLF-S TBD MPLAB ICD: PRO MATE II: PICSTART Plus: MPASM
TM
TBD TBD TBD TBD
Assembler:
MPLAB C18 C Compiler: TBD
Note:
Please read all associated README.TXT files that are supplied with the development tools. These "read me" files will discuss product support and any known limitations.
Preliminary
DS41190A-page 109
PIC12F629/675
NOTES:
DS41190A-page 110
Preliminary
PIC12F629/675
INDEX A
A/D ...................................................................................... 39 Acquisition Requirements ........................................... 43 Block Diagram............................................................. 39 Configuration and Operation....................................... 39 Effects of a RESET ..................................................... 45 Internal Sampling Switch (Rss) Impedence ................ 43 Operation During SLEEP ............................................ 45 PIC12F675 Converter Characteristics ........................ 98 Sampling Time ............................................................ 44 Source Impedance...................................................... 43 Summary of Registers ................................................ 45 Absolute Maximum Ratings ................................................ 83 AC Characteristics Industrial and Extended .............................................. 91 Additional Pin Functions ..................................................... 19 Interrupt-on-Change.................................................... 20 Weak Pull-up............................................................... 19 Analog Input Connection Considerations............................ 36 Analog-to-Digital Converter. See A/D Assembler MPASM Assembler ..................................................... 77 Comparator......................................................................... 33 Associated Registers.................................................. 38 Configuration .............................................................. 35 Effects of a RESET..................................................... 37 I/O Operating Modes .................................................. 35 Interrupts .................................................................... 38 Operation.................................................................... 34 Operation During SLEEP............................................ 37 Output......................................................................... 36 Reference ................................................................... 37 Response Time........................................................... 37 Comparator Specifications.................................................. 97 Comparator Voltage Reference Specifications................... 97 Configuration Bits ............................................................... 52 Configuring the Voltage Reference..................................... 37 Crystal Operation................................................................ 53
D
Data EEPROM Memory Associated Registers/Bits ........................................... 50 Code Protection.......................................................... 50 EEADR Register......................................................... 47 EECON1 Register ...................................................... 47 EECON2 Register ...................................................... 47 EEDATA Register ....................................................... 47 Data Memory Organization................................................... 7 DC Characteristics Extended .................................................................... 87 Extended and Industrial.............................................. 88 Industrial ..................................................................... 86 Development Support ......................................................... 77 Development Tool Version Requirements ........................ 109 Device Differences............................................................ 107 Device Migrations ............................................................. 108 Device Overview................................................................... 5
B
Block Diagram TMR0/WDT Prescaler................................................. 25 Block Diagrams Analog Input Mode...................................................... 36 Comparator Output ..................................................... 36 Comparator Voltage Reference .................................. 37 GP0 and GP1 Pins...................................................... 21 GP2............................................................................. 22 GP3............................................................................. 22 GP4............................................................................. 23 GP5............................................................................. 23 On-Chip Reset Circuit ................................................. 55 RC Oscillator Mode..................................................... 54 Timer1 ......................................................................... 28 Watchdog Timer .......................................................... 66 Brown-out Associated Registers .................................................. 58 Brown-out Detect (BOD) ..................................................... 56 Brown-out Reset Timing and Characteristics...................... 94
E
EEPROM Data Memory Reading ...................................................................... 49 Spurious Write ............................................................ 49 Write Verify ................................................................. 49 Writing ........................................................................ 49 Electrical Specifications ...................................................... 83 Errata .................................................................................... 3
C
Calibrated Internal RC Frequencies.................................... 92 CLKOUT ............................................................................. 54 Code Examples Changing Prescaler .................................................... 27 Data EEPROM Read .................................................. 49 Data EEPROM Write .................................................. 49 Initializing GPIO .......................................................... 19 Saving STATUS and W Registers in RAM .................. 65 Write Verify.................................................................. 49 Code Protection .................................................................. 68
F
Firmware Instructions ......................................................... 69
G
General Purpose Register File ............................................. 7 GPIO Associated Registers.................................................. 24 GPIO Port ........................................................................... 19 GPIO, TRISIO Registers..................................................... 19
Preliminary
DS41190A-page 111
PIC12F629/675
I
ICEPIC In-Circuit Emulator ................................................. 78 ID Locations ........................................................................ 68 In-Circuit Serial Programming ............................................. 68 Indirect Addressing, INDF and FSR Registers.................... 18 Instruction Format ............................................................... 69 Instruction Set ..................................................................... 69 ADDLW ....................................................................... 71 ADDWF ....................................................................... 71 ANDLW ....................................................................... 71 ANDWF ....................................................................... 71 BCF ............................................................................. 71 BSF ............................................................................. 71 BTFSC ........................................................................ 71 BTFSS ........................................................................ 71 CALL ........................................................................... 72 CLRF........................................................................... 72 CLRW.......................................................................... 72 CLRWDT..................................................................... 72 COMF ......................................................................... 72 DECF .......................................................................... 72 DECFSZ...................................................................... 73 GOTO.......................................................................... 73 INCF............................................................................ 73 INCFSZ ....................................................................... 73 IORLW......................................................................... 73 IORWF ........................................................................ 73 MOVF.......................................................................... 74 MOVLW....................................................................... 74 MOVWF ...................................................................... 74 NOP ............................................................................ 74 RETFIE ....................................................................... 74 RETLW........................................................................ 74 RETURN ..................................................................... 75 RLF ............................................................................. 75 RRF............................................................................. 75 SLEEP ........................................................................ 75 SUBLW........................................................................ 75 SUBWF ....................................................................... 75 SWAPF ....................................................................... 76 XORLW ....................................................................... 76 XORWF....................................................................... 76 Summary Table ........................................................... 70 Internal 4 MHz Oscillator..................................................... 54 Internal Sampling Switch (Rss) Impedence ........................ 43 Interrupts ............................................................................. 62 A/D Converter ............................................................. 64 Comparator ................................................................. 64 Context Saving............................................................ 65 GP2/INT ...................................................................... 64 GPIO ........................................................................... 64 Summary of Registers ................................................ 65 TMR0 .......................................................................... 64
M
MCLR.................................................................................. 56 Memory Organization Data EEPROM Memory.............................................. 47 Migrating from other PICmicro Devices ............................ 108 MPLAB C17 and MPLAB C18 C Compilers ....................... 77 MPLAB ICD In-Circuit Debugger ........................................ 79 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE............................................ 78 MPLAB Integrated Development Environment Software .................................................. 77 MPLINK Object Linker/MPLIB Object Librarian .................. 78
O
OPCODE Field Descriptions............................................... 69 Oscillator Configurations..................................................... 53 Oscillator Start-up Timer (OST) .......................................... 56
P
Packaging ......................................................................... 101 Details....................................................................... 102 Marking ..................................................................... 101 PCL and PCLATH............................................................... 17 Computed GOTO........................................................ 17 Stack ........................................................................... 17 PICDEM 1 Low Cost PICmicro Demonstration Board.................................................... 79 PICDEM 17 Demonstration Board...................................... 80 PICDEM 2 Low Cost PIC16CXX Demonstration Board.................................................... 79 PICDEM 3 Low Cost PIC16CXXX Demonstration Board.................................................... 80 PICSTART Plus Entry Level Development Programmer.................................................................. 79 Pin Descriptions and Diagrams .......................................... 21 Pinout Descriptions PIC12F629 ................................................................... 6 PIC12F675 ................................................................... 6 Power Control/Status Register (PCON).............................. 57 Power-Down Mode (SLEEP) .............................................. 67 Power-on Reset (POR)....................................................... 56 Power-up Timer (PWRT) .................................................... 56 Prescaler............................................................................. 27 Switching Prescaler Assignment ................................ 27 PRO MATE II Universal Device Programmer ..................... 79 Program Memory Organization............................................. 7 Programming, Device Instructions ...................................... 69
K
KEELOQ Evaluation and Programming Tools ...................... 80
DS41190A-page 112
Preliminary
PIC12F629/675
R
RC Oscillator ....................................................................... 54 Read-Modify-Write Operations ........................................... 69 Registers ADCON0 (A/D Control) ............................................... 41 ANSEL (Analog Select)............................................... 42 CMCON (Comparator Control) ................................... 33 CONFIG (Configuration Word).................................... 52 EEADR (EEPROM Address) ...................................... 47 EECON1 (EEPROM Control)...................................... 48 EEDAT (EEPROM Data)............................................. 47 INTCON (Interrupt Control)......................................... 13 IOCB (Interrupt-on-Change GPIO) ............................. 20 Maps PIC12F629............................................................ 8 PIC12F675............................................................ 8 OPTION_REG (Option) ........................................ 12, 26 OSCCAL (Oscillator Calibration)................................. 16 PCON (Power Control) ............................................... 16 PIE1 (Peripheral Interrupt Enable 1)........................... 14 PIR1 (Peripheral Interrupt 1)....................................... 15 STATUS ...................................................................... 11 T1CON (Timer1 Control)............................................. 30 VRCON (Voltage Reference Control) ......................... 38 WPU (Weak Pull-up) ................................................... 19 RESET ................................................................................ 55 Revision History ................................................................ 107 Timer1 Associated Registers.................................................. 31 Asynchronous Counter Mode ..................................... 31 Reading and Writing ........................................... 31 Capacitor Selection .................................................... 31 Interrupt ...................................................................... 29 Modes of Operations .................................................. 29 Operation During SLEEP............................................ 31 Oscillator..................................................................... 31 Prescaler .................................................................... 29 Timer1 Module with Gate Control ....................................... 28 Timing Diagrams CLKOUT and I/O ........................................................ 93 External Clock ............................................................ 91 INT Pin Interrupt ......................................................... 64 PIC12F675 A/D Conversion (Normal Mode) .............. 99 PIC12F675 A/D Conversion Timing (SLEEP Mode).................................................... 100 RESET, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ............................................. 94 Time-out Sequence on Power-up (MCLR not Tied to VDD)/ Case 1 ................................................................ 60 Case 2 ................................................................ 60 Time-out Sequence on Power-up (MCLR Tied to VDD).............................................. 60 Timer0 and Timer1 External Clock ............................. 96 Timer1 Incrementing Edge ......................................... 29 Timing Parameter Symbology ............................................ 90
S
Software Simulator (MPLAB SIM)....................................... 78 Special Features of the CPU .............................................. 51 Special Function Registers ................................................... 8 Special Functions Registers Summary ................................. 9
V
Voltage Reference Accuracy/Error ..................................... 37
W
Watchdog Timer Summary of Registers ................................................ 66 Watchdog Timer (WDT)...................................................... 65 WWW, On-Line Support ....................................................... 3
T
Time-out Sequence............................................................. 57 Timer0 ................................................................................. 25 Associated Registers .................................................. 27 External Clock............................................................. 26 Interrupt....................................................................... 25 Operation .................................................................... 25 T0CKI.......................................................................... 26
Preliminary
DS41190A-page 113
PIC12F629/675
NOTES:
DS41190A-page 114
Preliminary
PIC12F629/675
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world.
013001
Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, Users Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips Device Errata Job Postings Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products Conferences for products, Development Systems, technical information and more Listing of seminars and events
Preliminary
DS41190A-page 115
PIC12F629/675
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC12F629/675 Questions: 1. What are the best features of this document? Y N Literature Number: DS41190A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS41190A-page 116
Preliminary
PIC12F629/675
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b)
Device PIC12F6XX: Standard VDD range 2.0V to 5.5V PIC12F6XXT VDD range 2.0V to 5.5V (Tape and Reel) -40C to +85C -40C to +125C PDIP SOIC (Gull Wing, 150 mil body) MLF-S PIC12F629 - E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301. PIC12F675 - I/SO = Industrial Temp., SOIC package, 20 MHz.
Temperature Range
I E
= =
Package
P SN MF
= = =
Pattern
3-Digit Pattern Code for QTP (blank otherwise).
Sales and Support

Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Preliminary
DS41190A-page117
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
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03/01/02
DS41190A-page 118
Preliminary

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PIC12F629/675 Data Sheet

2002 Microchip Technology Inc.

2002 Microchip Technology Inc.

8-Pin FLASH-Based 8-Bit CMOS Microcontroller

Devices included in this Data Sheet:

High Performance RISC CPU:

Special Microcontroller Features:

2002 Microchip Technology Inc.

VSS GP0/CIN+/ICSPDAT GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT 8 7 6 5

VDD GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/VPP

VDD GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/VPP

2002 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

2002 Microchip Technology Inc.

2002 Microchip Technology Inc.

PIC12F629/675 BLOCK DIAGRAM

RAM File Registers 64 x 8 9

Instruction Reg Direct Addr 7

Addr MUX 8 Indirect Addr

10-bit A/D (PIC12F675 only)

Note 1: Higher order bits are from STATUS register.

2002 Microchip Technology Inc.

2002 Microchip Technology Inc.

Data Memory Organization

PROGRAM MEMORY MAP AND STACK FOR THE PIC12F629/675

CALL, RETURN RETFIE, RETLW

GENERAL PURPOSE REGISTER FILE

Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector 000h

On-chip Program Memory 03FFh 0400h

2002 Microchip Technology Inc.

DATA MEMORY MAP OF THE PIC12F629/675

Indirect addr.(1) TMR0 PCL STATUS FSR GPIO

PCLATH INTCON PIR1 TMR1L TMR1H T1CON

PCLATH INTCON PIE1 PCON OSCCAL

VRCON EEDATA EEADR EECON1 EECON2(1) ADRESL(2) ANSEL(2)

General Purpose Registers 64 Bytes

7Fh Bank 0 Bank 1

2002 Microchip Technology Inc.

SPECIAL FUNCTION REGISTERS SUMMARY

xxxx xxxx xxxx xxxx -000 0000

Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

2002 Microchip Technology Inc.

SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)

18,59 12,26 17 11 18 19 17 13 14 16 16 19 20 38 47 47 48 48 40 42,59

Program Counters (PC) Least Significant Byte IRP(2) RP1(2) RP0 TO PD Z DC C

0001 1xxx xxxx xxxx

0-0- 0000 0000 0000 -000 0000

---- x000 ---- ---xxxx xxxx

2002 Microchip Technology Inc.

STATUS STATUS REGISTER (ADDRESS: 03h OR 83h)

bit 7 bit 6 bit 5

2002 Microchip Technology Inc.

OPTION_REG OPTION REGISTER (ADDRESS: 81h)

2002 Microchip Technology Inc.