TDM Pulse Code Modulation

Transmitter and Receiver

Trainer ST2103 and ST2104

Learning Material
Ver.1.2

An ISO 9001 : 2008 company

94, Electronic Complex, Pardesipura

Indore - 452 010 India
Tel : 91-731 4211100
Fax : 91-731-2555643
e mail : info@[Link]
Websites: [Link]
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ST2103 & ST2104

TDM Pulse Code Modulation Transmitter and Receiver Trainer

ST2103 and ST2104
Table of Contents
1.

Safety Instructions

2.

Introduction to trainers ST2103 & ST2104

3.

TDM PCM ST2103s Features

4.

TDM PCM ST2103s Technical Specifications

5.

ST2104s Features

10

6.

ST2104s Technical Specifications

10

7.

Theory

11

I.

Pulse Modulation Techniques

13

II.

Theory of sampling

15

III.

Nyquists Theorem

16

IV.

Sampling Techniques

17

Sample and hold circuit

21

Important Parameters of Sample & Hold Circuit

24

Pulse modulation system

28

Time division multiplexing

31

PN sequence generator

34

X.

A/D conversion

39

XI.

D/A conversion

41

Digital Communication system

43

XIII.

Digital transmission

45

XIV.

Codes employed in ST2103 & ST2104

42

V.
VI.
VII.
VIII.
IX.

XII.

8.

Experiments

46

Experiment 1
Study of Error Check Codes

52

Experiment 2
Study of Analog to Digital Conversion

56

Experiment 3
Study of Control Signals and their Timings

60

Experiment 4
Study of Time Division Multiplexing

64

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Experiment 5
Study of Pseudo Random Sync Code Generator

66

Experiment 6
Study of Three Modes of Transmission

70

Experiment 7
Computer Communication using RS232 interface via
ST2103 & ST2104

80

Experiment 8
Multi point to multipoint communication using RS232
interface via ST2103 & ST2104

83

Experiment 9
Point to multipoint communication using RS232 interface
via ST2103 & ST2104

86

9.

Switched Faults

98

10.

Setting up the Receivers clock regeneration circuit

90

11.

Frequently Asked Questions

91

12.

Warranty

98

13.

List of Accessories

98

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Safety Instructions
Read the following safety instructions carefully before operating the instrument. To
avoid any personal injury or damage to the instrument or any product connected to it.
Do not operate the instrument if suspect any damage to it.
The instrument should be serviced by qualified personnel only.
For your safety:
Use proper Mains cord

: Use only the mains cord designed for this instrument.

Ensure that the mains cord is suitable for your
country.

Ground the Instrument

: This instrument is grounded through the protective

earth conductor of the mains cord. To avoid electric
shock the grounding conductor must be connected to
the earth ground. Before making connections to the
input terminals, ensure that the instrument is properly
grounded.

Observe Terminal Ratings : To avoid fire or shock hazards, observe all ratings and
marks on the instrument.
Use only the proper Fuse

: Use the fuse type and rating specified for this

instrument.

Use in proper Atmosphere : Please refer to operating conditions given in the

manual.
1.

Do not operate in wet / damp conditions.

2.

Do not operate in an explosive atmosphere.

3.

Keep the product dust free, clean and dry.

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Introduction
The ST2103 & 2104, TDM PCM transmitter & receiver trainer demonstrates the
basic scheme used to transmit an information signal using coding technique. It covers
very basic concepts like role of sample Amplifier, Analog to digital conversion,
Pseudo random synchro code generator, Digital to analog conversion, Pseudo random
synchro code detector of sampling pulse while transmitting a signal. It also
demonstrates signal recovery using low pass filters of different orders.
Know your ST2103 trainer better:
Function Generator Section:
It consists of two types of wave form generator:
DC level: With the help of DC level amplitude of dc signal can be varied from
minimum to maximum.
Sine wave generator: It generates 1 KHz & 2 KHz sine waves whose frequency can
be varied and the results of changing frequency can be analyzed for TDM PCM
transmitter and receiver.
Transmitter timing logic section:
It comprises of slow, fast modes & transmitter clock with timing logic which provides
necessary timing function for various section of the trainer for synchronization
purpose.
Pseudo random synchro code generator section:
This section can be used for transmitting data in secure manner.
Sampling & Analog to digital converter section:
This section provides two input channels for applying input signals and provides
multiplexed output with sampling of signals. Sampled signals are applied to the
analog to digital converter & applied to error check code generator and fed to shift
register for transmitting the signals by multiplexing it with Pseudo random synchro
code.
Know your ST2104 trainer better: It comprises of following sections.
Clock regeneration circuit: It receives the clock transmitted from transmitter and
again generates the same clock pulses for receiving process.
Pseudo random synchro code detector:
This section can be used for receiving data in secure manner.
Sampling & Digital to Analog converter section:
This section receives the multiplexed data from receiver section and applied to error
check code detector and then applied to digital to analog converter to get the analog
signals which are sampled and applied to low pass filter for generation of analog
signals

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Low pass filter section: It is used for reconstruction of received signals.

The manual explains a detailed working of the trainer with the help of complete
theory and set of nine experiments. The experimentation alone with its conclusion and
resulting waveforms are covered in the manual.

ST2103

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ST2103 & ST2104

ST2104

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ST2103 & ST2104

ST2103:

Features

Crystal Controlled Clock.

On-board Sine wave generator (Synchronized).

2 TDM Analog Channels.

PCM Transmitter.

Fast & Slow modes for real time operation and data flow examination.

Error check code options (odd-even parity, Hamming Code).

4 Switched faults allow different Error Check Options.

PC-PC Communication via RS232 interface.

Technical Specifications
Crystal Frequency

12 MHz

On Board Analog Signal

1 KHz, 2 KHz (sine wave synchronized to

sampling pulse Adjustable amplitude and
separate variable DC level)

Input Channels

Two

Multiplexing

Time Division Multiplexing

Modulation

Pulse Code Modulation

Sync Signal

Pseudo random sync code generator

Error Check Code

'Off'-Odd - Even - Hamming

Operating Mode

Fast: 240 KHz / channel (approximately)

Slow: 1Hz/ channel (approximately)

PC -PC communication

Using 2 channels via RS232

Port

9 Pin D type connector - 2Nos

Baud Rate

Selectable from 300 to 2400

Test Points

49 in numbers

Interconnections

2 mm Sockets

Power Supply

230 V 10%, 50 Hz

Power Consumption

4 VA (approximately)

Dimensions (mm)

W 420 x H100 x D255

Weight

2.5 Kgs. (approximately)

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ST2104:

Features

Input accepts two channel multiplexed data.

On board De-multiplexed PCM Receiver.

On board Low Pass Filter.

Fast & Slow modes for real time operation and data flow examination.

On board PLL for clock regeneration.

On board sync code detector.

Error check code options.

Odd or Even Parity-Single bit error detection.

Hamming code single bit error detection and correction.

4 Switched faults allow different error check code option.

PC-PC Communication via RS232 interface.

Technical Specifications
Input Channel

Time Division Multiplexed Serial Input

Demodulation

Pulse code Demodulation

Clock Regeneration

By phase Locked loop

Operating Speeds

Fast 240 KHz/Channel, Slow 1Hz/ Channel

Error Detection (Single bit) :

'Off'-Odd- Even parity& Hamming code

Error Correction

Hamming code

PC- PC communication

using 2 channels via RS232

Port

9 pin D type connector-2 Nos

Baud rate

selectable from 300 to 2400

Test Points

56 in numbers

Interconnections

4 mm sockets

Power Requirement

230V +/- 10%, 50Hz, 4VA

Dimensions (mm)

W420 x H100 x D255

Weight

2.5 Kgs. (approximately)

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Pulse Modulation Techniques

Pulse Code Modulation (PCM) is an extension of PAM wherein each analogue
sample value is quantized into a discrete value for representation as a digital code
word.
Thus, as shown below, a PAM system can be converted into a PCM system by adding
a suitable analogue-to-digital (A/D) converter at the source and a digital-to-analogue
(D/A) converter at the destination.
PCM is a true digital process as compared to PAM. In PCM the speech signal is
converted from analogue to digital form.
PCM is standardized for telephony by the ITU-T (International Telecommunications
Union - Telecoms, a branch of the UN), in a series of recommendations called the G
series. For example the ITU-T recommendations for out-of-band signal rejection in
PCM voice coders require that 14 dB of attenuation is provided at 4 KHz. Also, the
ITU-T transmission quality specification for telephony terminals requires that the
frequency response of the handset microphone has a sharp roll-off from 3.4 KHz.
In quantization the levels are assigned a binary codeword. All sample values falling
between two quantization levels are considered to be located at the centre of the
quantization interval. In this manner the quantization process introduces a certain
amount of error or distortion into the signal samples. This error known as quantization
noise is minimized by establishing a large number of small quantization intervals. Of
course, as the number of quantization intervals increase, so must the number or bits
increase to uniquely identify the quantization intervals. For example, if an analogue
voltage level is to be converted to a digital system with 8 discrete levels or
quantization steps three bits are required. In the ITU-T version there are 256
quantization steps, 128 positive and 128 negative, requiring 8 bits. A positive level is
represented by having bit 8 (MSB) at 0, and for a negative level the MSB is 1.
Pulse code modulation, more popularly known as PCM is the most widely used
digital modulation system. It is a widely known fact that the analog modulation
systems are most prone to the noise present in the channel and receiver. As we will
see further that the digital modulation systems are far less sensitive to noise as
compared to analog modulation. The basis of digital modulation systems lies on pulse
modulation i.e. a particular characteristic of the pulse is varied in accordance with the
information signal.
In Pulse Modulation, analog message is transmitted in discrete time. First of all,
sampling of the message signal should be performed. Considering the sampling
process, the sampled signal appears as a train of samples which is a form of PAM
(Pulse Amplitude Modulation) signal. When M levels are used to quantize this signal,
this modulation is called M-PAM. If those pulses were converted to digital numbers,
then the train of numbers so generated would be called as Pulse Code Modulated

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PCM signal. In PCM, modulation process is executed in three steps:

1.

Sampling

2.

Quantizing

3.

Coding

These steps are shown in Figure 1 with a block diagram:

Figure 1

PCM block Diagram

Figure 2
In PCM, the information signal x(t) is first sampled with the appropriate sampling
frequency (sampling frequency fs 2highest frequency of the information signal (fx)
), then the sampled levels are quantized to appropriate quantization levels. In the last
step, each quanta level is demonstrated by a two-code word, that is by a finite number
of {0,1} sequence. After this step, the signal is called as PCM wave.

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Pulse Code Modulation

Steps in Pulse Code Modulation:
Sampling:
The signals which are required to be transmitted as information is known as
information signal and in the case of voice communication this will be a continuously
changing signal containing speech information. The aim of the kit is to transmit the
signals in digital form and is to reproduce this information signal in analog form at the
receiving end of the communication system with the help of sampling and
reconstruction trainer.
In the exercises to follow, you will simulate audio signal by a 1 KHz test signal
provided On-board. The repetitive, non-changing waveform does not contain
information. Provided the frequency of the test-signal lies within the frequency range
which an information signal will occupy, a test signal of this type can be extremely
helpful in system analysis and testing.
The voice signals are limited to the range 300 Hz to 3.4 KHz, a 1 KHz frequency fits
conveniently in this range and can be used to demonstrate and test many techniques
used in communication system.
Theory of sampling:
The signals we use in the real world, such as our voice, are called "analog" signals.
To process these signals for digital communication, we need to convert analog signals
to "digital" form. While an analog signal is continuous in both time and amplitude, a
digital signal is discrete in both time and amplitude. To convert continuous time
signal to discrete time signal, a process is used called as sampling. The value of the
signal is measured at certain intervals in time. Each measurement is referred to as a
sample.
Principle of sampling:
Consider an analogue signal x(t) that can be viewed as a continuous function of time,
as shown in figure 3. We can represent this signal as a discrete time signal by using
values of x(t) at intervals of nTs to form x(nTs) as shown in figure 3. We are
"grabbing" points from the function x(t) at regular intervals of time, Ts, called the
sampling period.

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Basic Sampling Process

Figure 3

Sampling of signal at sampling interval (period) Ts

Figure 4
Figure 4 depicts the sampling of a signal at regular interval (period) t=nTs where n is
an integer. The sampling signal is a regular sequence of narrow pulses (t) of
amplitude [Link] 5 shows the sampled output of narrow pulses (t) at regular
interval of time.

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Sampled Output of narrow pulses (t)

Figure 5
The time distance Ts is called sampling interval or sampling period, fs=1/Ts is called
as sampling frequency (Hz or samples/sec), also called sampling rate.
The Sampling Theorem:
The Sampling Theorem states that a signal can be exactly reproduced if it is sampled
at a frequency Fs, where Fs is greater than twice the maximum frequency F max in the
signal.

Fs > 2 Fmax
The frequency 2 Fmax is called the Nyquist sampling rate. Half of this value, Fmax, is
sometimes called the Nyquist frequency.
The sampling theorem is considered to have been articulated by Nyquist in 1928 and
mathematically proven by Shannon in 1949. Some books use the term "Nyquist
Sampling Theorem", and others use "Shannon Sampling Theorem". They are in fact
the same sampling theorem.
The sampling theorem clearly states what the sampling rate should be for a given
range of frequencies. In practice, however, the range of frequencies needed to
faithfully record an analog signal is not always known beforehand. Nevertheless,
engineers often can define the frequency range of interest. As a result, analog filters
are sometimes used to remove frequency components outside the frequency range of
interest before the signal is sampled.
For example, the human ear can detect sound across the frequency range of 20 Hz to
20 KHz. According to the sampling theorem, one should sample sound signals at least
at 40 KHz in order for the reconstructed sound signal to be acceptable to the human
ear. Components higher than 20 KHz cannot be detected, but they can still pollute the
sampled signal through aliasing. Therefore, frequency components above 20 KHz are
removed from the sound signal before sampling by a band-pass or low-pass analog
filter.

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Nyquist Criterion
As shown-in the figure 6 the lowest sampling frequency that can be used without the
sidebands overlapping is twice the highest frequency component present in the
information signal. If we reduce this sampling frequency even further, the sidebands
and the information signal will overlap and we cannot recover the information signal
simply by low pass filtering. This phenomenon is known as fold-over distortion or
aliasing.

Nyquist Criterion (Sampling Theorem)

Figure 6
The Nyquist criteria states that a continuous signal band limited to Fm Hz can be
completely represented by and reconstructed from the samples taken at a rate greater
than or equal to 2Fm samples/second.
This minimum sampling frequency is called as Nyquist Rate i.e. for faithful
reproduction of information signal fs > 2 fm.
For audio signals the highest frequency component is 3.4 KHz.
So,

Sampling Frequency

2 fm
2 x 3.4 KHz
6.8 KHz

Practically, the sampling frequency is kept slightly more than the required rate. In
telephony the standard sampling rate is 8 KHz. Sample quantifies the instantaneous
value of the analog signal point at sampling point to obtain pulse amplitude output.

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Nyquists Uniform Sampling Theorem for Low pass Signal:

Part - I If a signal x(t) does not contain any frequency component beyond W Hz, then
the signal is completely described by its instantaneous uniform samples with sampling
interval (or period ) of Ts < 1/(2W) sec.
Part II The signal x(t) can be accurately reconstructed (recovered) from the set of
uniform instantaneous samples by passing the samples sequentially through an ideal
(brick-wall) low pass filter with bandwidth B, where W B < fs W and fs = 1/(Ts).
As the samples are generated at equal (same) interval (Ts) of time, the process of
sampling is called uniform sampling. Uniform sampling, as compared to any nonuniform sampling, is more extensively used in time-invariant systems as the theory of
uniform sampling (either instantaneous or otherwise) is well developed and the
techniques are easier to implement in practical systems.

Sampling Techniques
There are three types of sampling techniques as under:
1.

Ideal sampling or Instantaneous sampling or Impulse sampling

2.

Natural sampling

4.

Flat top sampling

1.

Ideal sampling or Instantaneous sampling or Impulse sampling:

For the proof of sampling theorem we use ideal or impulse sampling.

The concept of instantaneous sampling is more of a mathematical abstraction as no
practical sampling device can actually generate truly instantaneous samples (a
sampling pulse should have non-zero energy). However, this is not a deterrent in
using the theory of instantaneous sampling, as a fairly close approximation of
instantaneous sampling is sufficient for most practical systems. To contain our
discussion on Nyquists theorems, we will introduce some mathematical expressions.
If x(t) represents a continuous-time signal, the equivalent set of instantaneous uniform
samples {x(nTs)} may be represented as:
{x(nTs)} = x(t).(t- nTs)
where x(nTs) = x(t) =nTs , (t) is a unit pulse singularity function and n is an
integer

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Ideal sampling process

Figure 7(a)

Figure 7(b)
2.

Natural sampling:

In the analogue-to-digital conversion process an analogue waveform is sampled to

form a series of pulses whose amplitude is the amplitude of the sampled waveform at
the time the sample was taken. In natural sampling the pulse amplitude takes the
shape of the analogue waveform for the period of the sampling pulse as shown in
figure 8.

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Figure 8
3.

Flat Top sampling:

After an analogue waveform is sampled in the analogue-to-digital conversion process,

the continuous analogue waveform is converted into a series of pulses whose
amplitude is equal to the amplitude of the analogue signal at the start of the sampling
process. Since the sampled pulses have uniform amplitude, the process is called flat
top sampling as shown in figure 9.

Figure 9
Note that due to the flat-top pulses, the spectrum of the sampled signal is distorted.
The narrower the pulse width, the less distortion.
The original signal may be obtained by using a low-pass filter with a characteristic
which inverts the distortion.
Quantization:
In quantization the levels are assigned a binary codeword. All sample values falling
between two quantization levels are considered to be located at the centre of the
quantization interval. In this manner the quantization process introduces a certain
amount of error or distortion into the signal samples. This error known as quantization
noise is minimized by establishing a large number of small quantization intervals. Of
course, as the number of quantization intervals increase, so must the number or bits
increase to uniquely identify the quantization intervals. For example, if an analogue
voltage level is to be converted to a digital system with 8 discrete levels or
quantization steps three bits are required. In the ITU-T version there are 256
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quantization steps, 128 positive and 128 negative, requiring 8 bits. A positive level is
represented by having bit 8 (MSB) at 0 and for a negative level the MSB is 1.
This is the process of setting the sample amplitude, which can be continuously
variable to a discrete value. Look at Uniform Quantization first, where the discrete
values are evenly spaced.
Uniform Quantization
We assume that the amplitude of the signal m(t) is confined to the range (-mp, +mp ).
This range (2mp) is divided into L levels, each of step size , given by
= 2 mp / L

Output

A sample amplitude value is approximated by the midpoint of the interval in which it

lies. The input/output characteristic of a uniform quantizer is shown figure 10.

-m p

+m p

In p u t

Figure 10
The conventional, practical digital-to-analog converter (DAC) does not output a
sequence of impulses (such that, if ideally low-pass filtered, result in the original
signal before sampling) but instead output a sequence of piecewise constant values or
rectangular pulses. This means that there is an inherent effect of the zero-order hold
on the effective frequency response of the DAC resulting in a mild roll-off of gain at
the higher frequencies (a 3.9224 dB loss at the Nyquist frequency). This zero-order
hold effect is a consequence of the hold action of the DAC and is not due to the
sample and hold that might precede a conventional ADC as is often misunderstood.
The DAC can also suffer errors from jitter, noise, slewing, and non-linear mapping of
input value to output voltage.

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Sample & Hold circuit

In electronics, a sample and hold circuit is used to interface real-world signals, by
changing analogue signals to a subsequent system. The purpose of this circuit is to
hold the analogue value steady for a short time while the converter or other following
system performs some operation that takes a little time.
Sampling mode:
In this mode, the switch is in the closed position and the capacitor charges to the
instantaneous input voltage.
Hold mode:
In this mode, the switch is in the open position. The capacitor is now disconnected
from the input. As there is no path for the capacitor to discharge, it will hold the
voltage on it just before opening the switch. The capacitor will hold this voltage till
the next sampling instant.

Sample and Hold Waveform

Figure 11
Now, from figure 11 the area under the curve (which is equivalent to the signal
power) is greater and so the filter output amplitude and quality of reproduced signal is
improved.
In most circuits, a capacitor is used to store the analogue voltage and an electronic
switch or gate is used to alternately connect and disconnect the capacitor from the
analogue input. The rate at which this switch is operated is the sampling rate of the
system.
In a sample and hold circuit the switch opens for a very short duration. The sample
and hold circuit integrates for a short duration charge into a capacitor.

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The 'hold' facility can be provided by a capacitor, when the switch connects the
capacitor to PAM output it charges to the instantaneous value.
A buffered sample and hold circuit consists of unit gain buffer preceding and
succeeding the charging capacitor. The high input impedance of the preceding buffer
prevents the loading of the message source and also ensures that the capacitor charges
by a constant rate irrespective of the source impedance see figure 12(a).

Sample Hold Circuit

Figure 12(a)
The high input impedance of the succeeding buffer prevents the charging from the
capacitor due to loading and hence the capacitor can hold the charge for infinite time,
at least theoretically. However, small leakage current through the capacitor dielectric
into '+'ve input of second buffer is always present which causes gradual charge loss.
The rate of change of voltage with respect to time dv / dt is called as droop rate and is
important parameter in sample and Hold circuit design. The sample and hold
waveform is shown in figure 12(b).

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Sample and hold wave form

Figure 12(b)

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Important Parameters of Sample & Hold Circuit

1.

Aperture time:

The aperture time is defined as the delay time between the beginnings of the hold
command to the time the capacitor voltage ceases to follow the information signal.
Hence the hold value is different from the true sample value. The aperture time cannot
be reducing to zero because on application of finite time taken by a switch to close &
open on application of the hold signal. Therefore a small value of aperture time is
sought after.

Timing Diagram for Sample and Hold Circuit

Figure 13
2.

Acquisition Time:

In sample mode, it takes finite time for the capacitor to charge to the information
signal value depending on the RC time constant. This is called as the acquisition time.
The acquisition time is dependent on the current flowing from the input buffer
through switch and hence on RC time constant. The maximum acquisition time occurs
when the capacitor voltage has to change by the full amplitude of the information
signal.

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3.

Droop Rate:

As it has been discussed earlier, the presence of leakage current through capacitor
dielectric to +ve input of succeeding buffer causes charge loss of capacitor. Hence the
voltage level at the output falls with in time. This rate of change of voltage with
respect to time dv/dt is known as droop rate. Over value of droop rate is desirable as
the circuit should be able to maintain the sample at a relatively constant level until the
next sample.
4.

Feed Through:

At high frequencies, the stray capacitance within the switch causes some of the input
signal to appear at the output during the hold state (switch open). The fraction of input
signal appearing at the output of sample and hold circuit is called feed through.
The sample and hold feature provides both problem and benefit will be seen
afterwards.
Each binary word defines a particular narrow range of amplitude level. The sampled
value is then approximated to the nearest amplitude level. The sample is then assigned
a code corresponding to the amplitude level, which is then transmitted.
This process is called as Quantization & it is generally carried out by the A/D
converter.

Quantization & Encoding of a sampled signal

Figure 14

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The PCM code generated after Quantization process:

010 101 111 111 110 010 001 010 010
There are two important problems associated with quantization.
a.

Quantization noise :

As we have seen the signal is approximated to the nearest level (step). Since the levels
are discrete where as the signal is continuous, the discrepancy creeps in.
The difference between the analog signal value & its approximated one (quantized
one) is random & unpredictable. This is a sort of unwanted, unpredictable, random
signal which accompanies the information signal and is termed as 'Quantization
noise'.
Quantization noise can be reduced by increasing the number of levels, hence reducing
the approximation. But it can never be eliminated. Increasing the number of levels to
reduce quantization noise has the effect of increasing the number of bits. But nothing
comes without price. Increasing the number of bits to represent a sample increases the
system's bandwidth requirement.
b.

Finite sampling time of A/D converter :

Another problem associated with

finite time to convert the analog
requires that the value at its input,
But in practice, the duration of
converter's sampling time.

quantization is that the A/D Converter requires

information to digital data. The A/D Converter
remain unchanged till the conversion is complete.
sampled pulse is much smaller than the A/D

Bit step Analog to digital converter

Figure 15
This problem can be overcome by using a sample & hold circuit prior to A/D
converter output. The sample & hold circuitry holds the sample value till the next
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sample. The encoding method described above is called as uniform encoding i.e. the
quantization levels are uniform for all the amplitude range. But this method of
encoding has disadvantages of its own. The quantization noise plays havoc with the
low level signals because the % approximation compared to the signal amplitude is
very high. This causes a great amount of distortion at the receiver for low level
signals. Also the quieter part of music or speech could become severely distorted &
would make them unpleasant to listen.
To overcome this problem, a non-uniform encoding scheme is used. Here the
quantization levels are clear together for low level than they are for the high levels.
This has an effect of compression on the extreme ends of the signal. The input/output
characteristics for compression signal passed through a comparator network 'prior to
compression (See figure 16). This process is called compression.

An input output characteristic providing compression

Figure 16
The opposite effect is utilized at the receiver to undo the effect of compression, is
termed as expanding. The two processes are combined are known as compounding
this feature is not provided on trainer but you should be aware of its existence. Some
error correcting codes & synchronization can also be transmitted along with the
information signal.
At receiver, the data is decoded by the D/A converter; the recovered samples are
filtered & reconstructed to provide the original waveform.
Various channels can be multiplexed in time domain i.e. the information data from
various sources are sequentially transmitted over the same transmission medium e.g.
Let us assume a 3 channel PCM system. The system samples 0-2 samples sequentially
providing 3 samples to be converted to 3 "n" bit words. These three n bit words forms
the basis of a frame. The frame contains these three n bit words also contains some
synchronization & reference positioning information.

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On more complex multi-channel systems, control & routing information have to be

included. This information is termed as signaling information. If all these information
can not be fitted in a single frame, a separate channel is used for signaling &
synchronization information.
In Europe, a 30 channel PCM System is followed which is specified by CCITT
(International Radio Consultative Committee). Besides these channels, two separate
channels are used for signaling & synchronization information. Here the multi frame
consists of 16 frames.
Multi Frame:
When the number of bits in allocated channels is insufficient to cope with the
synchronization & signaling information then it is spread on defined channels over a
number of frames. This sequence of frames is known as a Multi Frames.

Pulse Modulation System

1.

Pulse Amplitude Modulation (PAM) :

In pulse amplitude modulation system the amplitude of the pulse is varied in
accordance with the instantaneous level of the modulating signal. Now days, the
PAM system is not generally used, but it forms the first stage of the other types
of pulse modulation.

2.

Pulse Width Modulation (PWM) :

In PWM system the width of the pulse is varied in accordance with the
instantaneous level of the modulating signal.

3.

Pulse Position Modulation (PPM) :

In PPM System, the position of the pulse relative to the zero reference level is
varied in accordance with the instantaneous level of the modulating signal.

4.

Pulse Code Modulation (PCM) :

In PCM System the amplitude of the sampled waveform at definite time
intervals is represented as a binary code. The first three techniques of the above
described systems are not truly digital but in fact are analog in nature. The very
fact that the variation of a particular pulse parameter is continuous rather than
being in the discrete steps makes the system analog in nature.
The Waveforms related to pulse modulation is shown in figure 17.

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Figure 17
As a result of this, the PAM signals are vulnerable to noise & dispersion of the pulse.
The channel introduces noise on the signal from various sources. Also the receiver is
not noise free.
The pulses also suffer attenuation & dispersion as they pass through the channel. The
primary line constants (L, C, G, & R) limit the velocity at which a particular
frequency can travel. The result is different frequency travel at different velocities in
the medium. Therefore some frequency component of the square wave arrives later as
compared to the other. This causes widening of the pulse width. The phenomenon is
called 'dispersion. The combined effect of attenuation, dispersion & noise is so large
that the pulse is impaired & introduced at the receiver as shown in figure 18.

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Pulse Train distortion due to Channel Characteristics

Figure 18

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Time Division Multiplexing:

Time division multiplexing is the process of combining the samples from different
information signals, in time domain so that they can be transmitted over the common
channel. The fact utilized in TDM technique is that there are large intervals between
the message samples. The samples from the other sources can be placed within these
time intervals. Thus every sample is separated from other in time domain. The time
division multiplexing system can be simulated by two rotating switches, one at
transmitter and the other at receiver. (See figure 19) The two wipers rotate and
establish electrical contact with one channel at a time.

Principle operation of TDM-PCM system

Figure 19
Time division multiplexing is a technique of transmitting more than one information
on the same channel. As can be noticed from the figure 20 below the samples consists
of short pulses followed by another pulse after a long time interval. This no-activity
time intervals can be used to include samples from the other channels as well. This
means that several information signals can be transmitted over a single channel by
sending samples from different information sources at different moments in time. This
technique is known as time division multiplexing or TDM. TDM is widely used in
digital communication systems to increase the efficiency of the transmitting medium.
TDM can be achieved by electronically switching the samples such that they inter
leave sequentially at a correct instant in time without mutual interference. The basic 4
channel TDM is shown in figure 21
The switches S1 & S2 are rotating in the shown direction in a synchronized manner,
where S1 is sampling channel to the transmission media. The timing of the two
switches is very important to ensure that the samples of one channel are received only
by the corresponding channel at the receiver. This synchronization between S1 & S2
must be established by some means for reliable communication. One such method is
to send synchronization code (information) along itself to the transmitter all the time.
In practice, the switches S1 & S2 are simulated electronically.
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Pulse Amplitude Modulated wave with large time Intervals between samples
Figure 20
Benefits of TDM :
1.
2.

3.

TDM is all about cost: fewer wires and simpler receivers are used to transmit
data from multiple sources to multiple destinations.
TDM also uses less bandwidth than Frequency-Division Multiplexing (FDM)
signals, unless the bit rate is increased, which will subsequently increase the
necessary bandwidth of the transmission.
An asset of TDM is its flexibility. The scheme allows for variation in the
number of signals being sent along the line, and constantly adjusts the time
intervals to make optimum use of the available bandwidth. The Internet is a
classic example of a communications network in which the volume of traffic can
change drastically from hour to hour.

On ST2103, the sequence of operation is synchronized to the transmitter clock TX.

Clock (TP3). The time occupied by each clock pulse is called a Bit. The sequence of
operation is repeated after every 15 bits. The complete cycle of 15 bits is called timing
frame. The start of the timing frame is denoted by the [Link] signal (TP4) which goes
high during the bit time 0. The various bits reserved for the data appearing in the
middle of each transmitter clock cycle is shown in figure the figure 12 shows the
complete timing frame

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Principle of 4-Channel TDM System

Figure 21
Pseudo-random Noise (PN) sequence:
A Pseudo-random Noise (PN) sequence is a sequence of binary numbers, e.g. 1,
which appears to be random; but is in fact perfectly deterministic. The sequence
appears to be random in the sense that the binary values and groups or runs of the
same binary value occur in the sequence in the same proportion they would if the
sequence were being generated based on a fair "coin tossing" experiment. In the
experiment, each head could result in one binary value and a tail the other value. The
PN sequence appears to have been generated from such an experiment. A software or
hardware device designed to produce a PN sequence is called a PN generator.
Pseudo random noise sequences or PN sequences are known sequences that exhibit
the properties or characteristics of random sequences. They can be used to logically
isolate users on the same frequency channel. They can also be used to perform
scrambling as well as spreading and dispreading functions.
The reason we need to use PN sequences is that if the code sequences were
deterministic, then everybody could access the channel. If code sequences were truly
random on the other hand, then nobody, including the intended receiver, would be
able to access the channel. Thus using pseudo random sequences make the signal look
like random noise to everybody except to the transmitter and the intended receiver.

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PN Sequences and Generators

A PN generator is typically made of N cascaded flip-flop circuits and a specially
selected feedback arrangement as shown below.

Figure 22
The flip-flop circuits when used in the cascaded manner is called a shift register, since
each clock pulse applied to the flip-flops causes the contents of each flip-flop to be
shifted to the right. The feedback connections provide the input to the left-most flipflop. With N binary stages, the largest number of different patterns the shift register
can have is 2N. However, the all-binary-zero state is not allowed because it would
cause all remaining states of the shift register and its outputs to be binary zero. The
all-binary-ones state does not cause a similar problem of repeated binary ones
provided the number of flip-flops input to the module 2 adder is even. The period of
the PN sequence is therefore 2N-1, but IS-95 introduces an extra binary zero to
achieve a period of 2N, where N equals 15.
Starting with the register in state 001 as shown, the next 7 states are 100, 010, 101,
110, 111, 011, and then 001 again and the states continue to repeat. The output taken
from the right-most flip-flop is 1001011 and then repeats. With the three stage shift
register shown, the period is 2 3-1 or 7. The PN sequence in general has 2N/2 binary
ones and [2N/2]-1 binary zeros. As an example, note that the PN sequence 1001011 of
period 2 3-1 contains 4 binary ones and 3 binary zeros. Furthermore, the numbers of
times the binary ones and zeros repeat in groups or runs also appear in the same
proportion they would if the PN sequence were actually generated by a coin tossing
experiment. The flip-flops which should be tapped-off and fed into the module 2
adder are determined by an advanced algebra which has identified certain binary
polynomials called primitive irreducible or unfactorable polynomials. Such
polynomials are used to specify the feedback taps. For example, IS-95 specifies the
in-phase PN generator shall be built based on the characteristic polynomial
PI(x) = x15 + x13 + x9 + x8 + x7 + x5 + 1
Now visualize a 15 stage shift register with the right-most stage numbered zero and
the successive stages to the left numbered 1, 2, 3 etc., until the left-most stage is
numbered 14. Then the exponents less than 15 in Eq. (1) tell us that stages 0, 5, 7, 8,
9, and 13 should be tapped and summed in a module 2 adder. The output of the adder

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is then input to the left-most stage. The shift register PN sequence generator is shown
below.

Figure 23
PN Sequences also referred to as PN Codes sequences can be generated with a n-stage
Linear Shift Register where:
1.

Appropriate taps are connected to a Modulo 2 adder;

2.

A seed pattern (other than an all-zeros state) is continuously shifted through the
Linear Shift Register, triggered by a clock.

Figure 24

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The output of the Modulo 2 adder is used to drive the input of the shift register.
Let us conduct the following experiment and draw some useful conclusions from its
results:
1.

Connect Tap #1 and Tap #3 to the input of the Modulo-2 adder.

2.

Drive the Linear Shift register with a clock.

The resulting States of the Shift Register for various clocks are:

Clock

Binary codes

001

100

110

111

011

101

010

001

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The output sequence 1 0 0 1 1 1 0 . (a) Repeats itself after 7 shifts and is referred to
as a PN Sequence or PN Code.

Figure 25
Bit 0: This bit is reserved for the synchronization of information generated by the
Pseudo random sync code generator block more about its operation in the later
section. When the Pseudo Random Sync Code is switched 'Off' a '0' is transmitted.
Bit 1 to 7: These carry a 7 bit data word corresponding to the last sample taken from
the analog channel CH 0. Remember that the trainer transmits the lowest significant
bit (LSB) first. This time interval during which the coded information regarding the
analog information is transmitted is called the time slot. Since the present time slot
corresponds to channel 0 it is known as time slot 0.
Bit 8 to 14: This time slot termed time slot 1 contains the 7 bit word corresponding to
the last sample taken of analog channel1. As with channel 0 the least significant bit is
transmitted first. The receiver requires two signals for its correct operation & reliable
communication, namely.
a. Receiver clock operating at the same frequency as that of the ST2103 clock.
b. Synchronization signal, which allows the receiver to synchronizes its
clock/operation with the transmitters clock operation. All these requirements can
be achieved by transmitting two essential information signals :
I. A Transmit clock signal.
II. A Frame synchronization signal.
The simplest method is to transmit the synchronization information & the clock over a
separate transmission link. This results in a simplest receiver. It is used in data
communication LAN (Local Area Network) & in telemetry systems. However it is a
waste of media & is not economical for long distance communications.

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The ST2103 provides these two signals at TX. Clock output (TP3) & [Link] output
(TP4). In this mode the Pseudo random sync code generator & detector (on ST2104)
are switched 'Off'.
The second technique is to transmit the synchronization code along with transmitted
data to be sufficiently different from the information samples.
The ST2103 involves the use of a pseudo-random sync code generator. These codes
are bit streams of '0's & '1's whose occurrence is detected by some rules. The Pseudo Random Sync Code gets its name from the fact that the occurrence of '0's & '1 's in the
stream is random for a portion of sequence i.e. there is equal probability of occurrence
of '0' and '1 '. This portion of sequence is 15 bit long on ST2103.
On the receiver the pseudo-random sync code detector recognizes the Pseudo random
code & use it to identify, which incoming data bit is associated with which transmitter
time slot The advantage of this technique is that if the synchronization is temporarily
lost, due to noise corruption, it can be re-established as the signal clears. Hence there
is minimal loss of transmitted information. Also this technique also reduces the
separate link required for the synchronization signal of transmission.
Mode 1 : Mode 1 is TDM system of three transmission links between transmitter &
receiver. They are information, TX clock & [Link] (synchronization) signal links.
The Pseudo random sync code generator & Detector are switched 'Off' in this case.
Mode 2 : Mode 2 is TDM system of two transmission links between transmitter &
receiver. These are information & TX clock signal links. The synchronization is
established by sync codes transmitted along with the data stream. No need to say that
the pseudo random sync generator & detector are switched On.
Mode 3 : Mode 3 is TDM system of one link between transmitter & receiver, namely
the link carrying information. Synchronization is again established by the sync codes.
The clock signal is regenerated by the phase locked loop (PLL) circuit at the receiver
from the transition of the information data bits.

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A/D Conversion
The PCM Transmitter samples the analog input, time division multiplex and many
such channels, quantizes it & code it by analog to digital conversion. As it is known,
the binary number system consists of binary digits '0' and '1'. The group of n bits is
called as word and is used to distinguish one code from the other. The range of
decimal numbers represented by such n bits code is equal to 2n (including 0) e.g. If we
take an 8 bit word, the number or different codes possible is equal to 28 = 256 i.e. we
have 0 to 255 code levels available.

SAR Analog to digital converter

Figure 26
This range can be used to indicate any range of voltage. The process of allocating the
binary values to each sample taken in PAM system is known as quantization. Every
binary number indicates one level. Since binary value changes in discrete steps & is
not continuous like analog waveform, some distortion creeps in at the time of value
assignment; this is discussed in forth coming parts. The range of binary values used is
the design feature of the system & depends upon the amplitude range of the signal and
the accuracy of the conversion to be achieved.
Most systems use an 8 bit word length which is practically found most suitable to
cover the sufficient range & provide the accuracy needed for speech signals. As with
all engineering processes, quantization produces its own problems & an engineering
compromise is then called for. The two major problems associated with quantization
are :
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1) One major problem associated with quantization is due to the discrete nature of
binary numbers which are used to represent continuously variable analog
waveform, It is not possible to represent all the analog values (which are infinite
in number) by limited binary words e.g. if in the figure 27, the analog value lies in
between the two voltages represented by 0011 & 0100 binary words, what will
happen?

Figure 27
In such cases the system allocates a binary number closest to the sample value. This
leads to distortion of the information signal & the approximation is random for
different voltage levels. Hence it is known as quantization noise. Quantization noise
can be reduced by increasing the number of bits used to represent a sample. But it can
never be eliminated. Increasing the number of bits in a word has an effect of
increasing the number of quantization levels.
2) The second problem is associated with the finite time taken by the A/D Converter
to complete the translation from analog to binary code. An A/D Converter
requires that the sample value should remain unchanged till the conversion is
complete, but usually the duration of the sample pulse is much smaller than the
conversion time. This problem can be overcome by using a sample and hold
circuit prior to A/D input. The sample and hold circuit holds the sample value for
the A/D Conversion time. The quantization & Coding process is carried by the
A/D Converter. On ST2103 the A/D converter used is AD670. It is an 8 bit A/D
converter. The A/D conversions are controlled by R/W, CS, & CE pins. The R/W
pin directs the converter to read or start a conversion. The CE & CS pins are tied
to logic 0. The Status pin goes High indicating that a conversion is in process. At
the end of the conversion the Status pin goes Low. On ST2103 the R/W pin is
named as SC (TP7) and pin after inversion is named as EC (TP8). This EC is used
to latch the valid data into D-type Flip-Flops (see circuit description in operating
manual). Only 7 most significant bits out of 8 data outputs are used on ST2103.
The LSB (D0) is ignored.

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D/A Conversion
A digital-to-analog converter, or simply DAC, is a semiconductor device that is
used to convert a digital code into an analog signal. Digital-to-analog conversion is
the primary means by which digital equipment such as computer-based systems are
able to translate digital data into real-world signals that are more understandable to or
useable by humans, such as music, speech, pictures, video, and the like. It also allows
digital control of machines, equipment, household appliances, and the like.
A typical digital-to-analog converter outputs an analog signal, which is usually
voltage or current that is proportional to the value of the digital code provided to its
inputs. Most DAC's have several digital input pins to receive all the bits of its input
digital code in parallel (at the same time). Some DAC's, however, are designed to
receive the input digital data in serial form (one bit at a time), so these only have a
single digital input pin.
A simple DAC may be implemented using an op-amp circuit known as a summer, so
named because its output voltage is the sum of its input voltages. Each of its inputs
uses a resistor of different binary weight, such that if R0=R, then R1=R/2, R2=R/4,
R3=R/8,.., RN-1=R/(2N-1). The output of a summer circuit with N bits is:
Vo = -VR (Rf / R) (SN-12N-1 + SN-22 N-2+...+S020)
Where VR is the voltage to which the bit is connected when the digital input is '1'. A
digital input is '0' if the bit is connected to 0V (ground). A 4-bit summer circuit is
shown in Figure 28.

An Op Amp Summer Circuit Used as a DAC

Figure 28

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One problem with this circuit is the wide range of resistor values needed to build a
DAC with a high number of digital inputs. Putting thin-film resistors that come in a
wide range of values (e.g., from a few ks to several Ms) on a single semiconductor
chip can be very difficult, especially if high accuracy and stability are required.
A better-designed and more commonly-used circuit for digital-to-analog conversion is
known as the R-2R ladder DAC, a 4-bit version of which is shown in Fig. 29. It
consists of a network of resistors with only two values, R and 2R. The input SN to bit
N is '1' if it is connected to a voltage VR and '0' if it is grounded. Thevenin's Theorem
may be applied to prove that the output Vo of an R-2R ladder DAC with N bits is:
Vo = VR/2 N (SN-12N-1 + SN-22 N-2+...+S02 0).
Thus, the output of the R-2R ladder in Figure 2 is Vo = VR/24 (S323+S222+S121+S020)
or Vo = VR (S3 / 2 + S2 / 4 + S1 / 8 + S0 / 16) . In effect, contribution of each bit to the
analog output is proportional to its binary weight.

A 4-bit R-2R Ladder DAC

Figure 29

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Digital Communication System

Digital communication systems are less sensitive to noise as compared to their analog
counter part. This fact mostly makes the digital communication systems very popular.
Although the digital communication systems are mostly unaffected by noise, still
there is a probability that the bits are recognized wrongly at the receiver due to noise.
One important parameter which measures the unsuccessful recognition of data bits is
BER (bit error rate). A probability of bit error Pbe-(or BER as it is usually referred)
10 means that, on an average, 1 bit in every 1,00,000 will be in error, For acceptable
quality speech signals the BER/ Pbe should not be more than 10 while some data
transmission systems may require values of Pbe = 10 or less.
Advantages of digital modulation system:
a.

Noise & Distortion :

Pulse which becomes distorted by the addition of noise can be reshaped at the
regenerators installed at pre-determined intervals along the link. Thus within
certain threshold the error will not creep in.

b.

Multiplexing :
The information once sampled & coded can be multiplexed in time domain, i.e.
the coded information from different sources can be sent, one after another, if it
can be re-routed to the corresponding channels at the receiver.
The information is coded in binary form, the source of information / sample,
becomes unimportant. Therefore many different sources such as telephone,
facsimile, telegraphy and video cap are transmitted over same channel &
circuitry.

c.

Store & forward (S & F) facility :

That information which has been binary coded in digital format can be easily
stored in the computer or memory elements, & information can be forwarded at
the desired time. It is required at the time of channel congestion. The message
can be stored in memory. Once the channel becomes clear, the message can be
forwarded to the called party.

d.

Encryption & security :

The digital devices today are capable of high grade encryption. The data can not
be correctly interpreted if the receiver has no proper decoder. Hence the digital
communication can be highly secured.

e.

Power requirement :
To transmit the digital data over the same channel requires less signal power
than that would be required for same performance of the receiver for analog
systems.

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Disadvantages of digital modulation communication system:

a.

Band with requirement :

The digital communication systems need very large bandwidth as compared to
its analog counter part.

b.

Complexity :
The digital transmitter & receivers is the complex due to the requirement of
highly reliable timing information. This adds to complexity as well as to the cost
of the communications system. With the advent of new technology, the digital
circuits / IC's are becoming more and cheaper still prices are slightly at the
higher side. But the advantage offered by the digital techniques far over weighs
this consideration.

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Digital Transmission
There are two methods for sending digital data over a distance, namely
a.

Parallel transmission

b.

Serial transmission

In short distance communication like inside terminal equipment or two computer

terminals located near each other, the signals are passed in parallel, format over
parallel wires. Thus the signal in the form of a word is passed. This mode is faster.
For long distances, even more than few feets, this is uneconomical & inefficient way
of transmission. It is a wasteful of transmission media as each bit requires a separate
link. Therefore the digital signals are transmitted serially over a single link.
The two important parameters in serial signaling are
1.

The modulation rate or the signaling rate (in Baud) &

2.

data transmission rate or bit rate (in Bits per second)

The signaling rate or modulation rate is defined as the maximum rate at which the
signal is switched between signaling rate (or number of symbols transmitted per
second).
The other way of defining modulation rate is that it is the reciprocal of the shortest
time for which the signal remains in any state. The modulation rate is measured in
Baud which is equal to one unit signal element per second. See figure 30.

Figure 30
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From figure 30 it is clear that

S = 1 / T 1 Baud
e.g. if the shortest pulse duration is 5 ms, then the modulation rate is
S = 1 / 5 x 10 -3 = 200 Baud.
The data transmission rate is defined as the rate at which the data is transmitted over a
channel. Its unit is Bits / second (also written as bps). The data transmission rate is
calculated as
Bit rate = (1 / T1) x log 2 L bits / second.
Where T 1 is the duration of unit signal element and L is the number of levels or the
signaling states. The two terms are often confused in computing because of the use of
binary (0 or 1 state) system.
Signaling rate S = 1 / T 1 Baud
While the data transmission rate is
Bit rate = 1 / T 1 log 2 2 = 1 / T 1 bits second
If we use 4 state signaling the data transmission rate becomes
Bit rate = 1 / T 1 log 24 = 1 / T 1 x 2 = 2 (1/T 1) = 2 (signaling rate)
i.e. it is twice the signaling (modulating rate)
Bit rate = 1/T 1 log 2 4 = 2/T1 log 22 = 2/T 1 bits/second
In this case the Bit rate is twice the modulation rate. Similarly, the data on out board
is transmitted serially by loading it into the shift register.
The ST2103 uses two 4 bits parallel to serial converter (shift Register). They are
arranged as shown in figure 31. Each shift register can shift only 4 bits and make it a
7 bit register.
The operation of the shift register is shown in figure 32.
As you can notice from figure 30 what ever is on parallel inputs (A, B, C, D) is
reflected as parallel outputs (QA, QB, QC, QD). When S/L is low & there is a
positive (rising) edge of clock pulse. When S/L is high the subsequent shifting occurs
on each positive edge of clock pulse.

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The ST2103's A/D Converter outputs data in parallel format which is change into
serial format by the shift register. This is known as parallel to serial conversion.

Shift Register Organization

Figure 31

Figure 32
Reasons for induced errors in digital system:
a.
Impulse Noise :
It can be defined as a high noise level occurring for a very short time, producing
noise spikes superimposed upon the signal waveform. The source of impulse noise
may be lightning strike or sudden heavy current flow through a system or
electromagnetic radiation etc.
b.

Transmission medium characteristics :

As it has been mentioned earlier, the characteristic of the transmission medium causes
attenuation and dispersion, leading to the indecision pulse level recognition. This can
lead to errors.

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c.

Late Switching :

The late switching by some aging devices or due to loss of synchronization leads to
change in average level & this causes errors to permit us to detect the errors caused by
noise in some cases & to be able to correct them, the method of coding the signal is
adopted.
Coding accomplishes its purpose by deliberate introduction of redundancy in the
message. Their degree of success depends upon the redundancy which they introduce
e.g. Consider that we are transmitting information by means of binary PCM. Then we
transmit a stream of binary digits 0's or 1's. Our main concern is that we do not
confuse a 0 for a 1 or a '1' for a '0'. Suppose that when a '0' is to be transmitted we
transmit 000 & we transmit 111 to represent a digit 1. The other two 0's or 1's add no
information to the message & hence are redundant.
Suppose that the signal to noise ratio on the channel is such that we can be nearly
certain that not more than one error will be made in triplet. Then, if we received 001,
010, or 100, we would actually be certain that the transmitted data was actually 0.
Similarly, if we received 011, 101, or 110 we would be rather certain that the message
was actually 111. Thus the redundancy, deliberately introduced has enabled us to
detect and even correct the error.
But the introduction of redundancy can't guarantee that an error will either be
detectable or correctable. As noise is unpredictable, there is always a finite possibility
that those two errors may occur. In this case we will know that the error has occurred,
but we will be inclined to read a '0' as a '1' & a '1' as a '0'.
Even There is an over possibility, however small, that all the three bits are in error. In
this case, not only we will misread the digits but we would not even suspect that an
error has been made. Thus we conclude that while coding allows us a great deal of
detection & correction it generally cannot detect or correct all errors. Detection of
errors allows the system to request re-transmission of data. But it does not really solve
the problem. However it does offer the system ability to record and evaluate system
error rate.
A better solution would be to introduce a method of error detection and correction.
The correction is done automatically by receiver. The degree of success depends upon
the redundancy which they introduce.
It is clear that if the redundant message is to be transmitted at the same rate as the
original binary signal, we shall have to transmit more no of bits in time TS otherwise
allocated to a single bit. And it is an established fact that the increase in bit rate may
increase the error rate. Hence the required increased bit rate will undo some of the
advantage that will accrue from redundancy coding. However coding yields a very
worthwhile net advantage. The price to be paid is increased hardware complexity both
for transmitter & receiver where encoding & decoding is affected respectively.
Many different types of codes have been developed and are in use. The commonly
used are as:

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Codes employed in ST2103 & ST2104

a)

Parity Coding :

It is the simplest method of error coding. Parity is a method of encoding such that the
number of 1's in a codeword is either even or odd Signal parity is established as
follows. Each word is examined to determine whether it contains an odd or even
number of '1' bits.
If even parity is to be established (known as Even parity), a '1' bit is added to each
word containing odd '1' and a '0' bit is added to each word containing even '1 'so the
result is that all the code words contain an even number of 1 bits after encoding.
Similarly, the parity coding can ensure that the total number of '1's in the encoded
word is odd. In such number of '1's in the encoded word is odd. In such cases it is
called as odd parity.
Continuing with the example of even parity, after transmission, each code word is
examined to see if it contains an even number of 1 bits. If it does not, the presence of
an error is indicated. If it does, the parity bit remains and the data is passed to the
user.
Note that single bit parity code can detect single errors only and it cannot provide
error correction because there is no way of knowing which bit is in error.
It is for this reason that parity coding is normally only used on transmission systems
where the probability of error occurring is deemed to be low.
b)

Hamming Coding :

Hamming coding, decode each word at the transmitter into a new code by stuffing the
word with extra redundant bits. As the name suggests, the redundant bits do not
convey information but also provides a method of allowing the receiver to decide
when an error has occurred & which bit is in error since the system is binary, the bit
in error is easily corrected.
Three bit hamming code provides single bit error detection and correction.
The ST2103 & ST2104 involves the use of 7 bit word. Therefore only four bits are
used for transmitting data if hamming code is selected. The format becomes.
D6

D5

D4

D3

C2

C1

C0

Where C2, C1 & C0 are Hamming Code Bits

The Hamming code was invented by R.W. Hamming. It uses three redundant bits, as
opposed to the single redundant bit needed by simple parity checking. But it provides
a facility of single bit error detection & correction.

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Code Generation on Trainer

The code on this trainer is generated by addicting parity check bit to each group as
shown below :
Group 1

D6, D5, D4

Parity Bit - C2

Group 2

D6, D5, D3

Parity Bit - C1

Group 3

D6, D4, D3

Parity Bit C0

The Groups & Parity bit forms an even parity check group. If an error occurs in any of
the digits, the parity is lost & can be detected at receiver e.g. Let us encode binary
value D6, D5, D4, D3 of '1101'
Group 1
Group 2
Group 3

D6

D5

D4

C2

D6

D5

D3

C1

D6

D4

D3

C0

So, the data word after coding will be

D6

D5

D4

D3

C2

C1

C0

At the receiver, the four digits representing a particular quantized value are taken in as
three groups. The Error Detection/ Correction Logic carries out even parity checks on
the three groups.
Group 1

D6

D5

D4

C2

Group 2

D6

D5

D3

C1

Group 3

D6

D4

D3

C0

If none of them fails, then no error has occurred in transmission & all bit values are
valid. Suppose, a case, where the following parity check was carried out & the listed
groups failed.
Group 1
Group 2
Group 3

D6

D5

D4

C2

D6

D5

D3

C1

D6

D4

D3

C0

Failed
Failed
Passed

If we suppose only a signal bit corruption, the passing of Group 3 means that all D6,
D4, D3 & C0 are valid.
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In the above two groups the only common element except D6, is D5. As D6 is
received correctly clear from Group 3 the only bit which can be in error is Bit 5 i.e.
D5. Since the corrupted bit has been detected, the receiver can now make changes in
D5 to convert it to other possible value i.e. '0'. Thus the data word is corrected to
0001010. The receiver now discards the redundant check bits (C2, C1 & C0) and
passes the valid data (0001) to the input of D/a converter table given below gives the
location of possible single bit errors.
Parity Check Results on ST2104
Group-l

Group-2

Group-3

Location of

D6 D5 D4 C2

D6 D5 D3 C1

D6 D3 C0

Error

PASS

PASS

PASS

No Error

PASS

PASS

FAIL

C0

PASS

PASS

PASS

C1

PASS

PASS

FAIL

D3

PASS

PASS

PASS

C2

PASS

PASS

FAIL

D4

PASS

PASS

PASS

D5

PASS

PASS

FAIL

D6

Recommended testing instruments needed for experiments in this work book

1.

Oscilloscope 20 MHz, Dual Trace, ALT Trigger with bandwidth

2.

Oscilloscope Probes X1 X10 etc.

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Experiment 1
Objective: Study of Error Check Codes
Equipment required:
1.

ST2103 & ST 2104 trainer with power supply cord

2.

Oscilloscope with connecting probe

3.

Connection cords

Procedure:
A.

Initial set up for trainer ST2103:

Mode Switch Position

: FAST position

Function generator setting:

B.

1.

DC l & DC 2 amplitude controls

: fully clockwise direction.

1 KHz & 2 KHz signal levels

: 10 V peak -peak.

Pseudo random sync code generator switch

: ON position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 Position ('Off'

All switched faults

: Off position.

Initial set up for trainer ST2104:

Mode Switch Position

: FAST position

Pseudo random sync code generator switch

: ON position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 positions ('Off'

All switched faults

: Off position.

Pulse generator delay adjusts control

: fully clockwise position.

Make the following connections on ST2103 (See Figure 1.1) :

a)

DC l Output to CH 0 input (TP 10).

b)

CH 0 Input (TP10) to CH 1 input (TP12).

This ensures that the two channels contain the same information.
2.

3.

Make the following connections on ST2104 (See figure 1.1) :

a)

PCM data input (TP1) to clock regeneration circuit input (TP3).

b)

Output of clock regeneration circuit (TP8) to RX clock input (TP46).

Make the following connections between ST2103 & ST2104 see Figure.1.1.
a)

PCM output (TP44) of ST2103 to PCM data input (TP1) of ST2104.

b)

Connect the grounds of both the trainers.

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4.

Turn On the power supply and oscilloscope. Ensure that the frequency of the
VCO in the receiver clock regeneration circuit has been correctly adjusted

5.

Connect

6.

a)

Channel 1 of oscilloscope to (TP10) on ST2103.

b)

Channel 2 of oscilloscope to (TP33) on ST2104.

c)

Vary DC l and note that the data is transferred correctly between the two
trainers. You can verify that the data in the A/D converter Block of
ST2103 is always the same as the data in D/A converter Block of ST2104
also the output voltage of TP33 of ST2104 should be same as the input
voltage at TP10 of ST2103 for all DC input levels.

Select even parity with error check code selector switches A & B at A=0 & B=1
position, on both the trainers. Set up various codes from A/D Converter's output
LEDs some containing even no of l's & some odd. Check the error check code
generator output of ST2103. Data latch output (TP16 to 22) on ST2104 & D / A
Converter input (TP23 to 29) on ST2104. Notice the number of '1's in the
transmitted data streams. Is it ever Odd?
Note: ST2103 uses the least significant bit (LSB) of the 7 bit word to transmit
the parity bit. Its value is changed to achieve the correct parity for each word.

7.

Compare the output of the data latch led (TP16 to 22) with input to the D/A
Converter LED in each case. Once the error detection logic has decided whether
an error has occurred, it must pass the received code to the D/A converter. But
since D0 bit was used as parity bit, it is always forced to a '0'. Notice that the
quantized values on output of A/D Converter is not necessary but same to be
applied to D/ A Converter receiver end due to the action of error detection logic.

8.

Set up the error check selector A & B switches to A = 1 & B = 0 position on

both trainers to select the odd parity mode carry out steps 8 & 9 again, but odd
parity selected this time.

9.

Carry out the same experiment with 1 KHz sine wave applied at CH 0 & CH1
Input of ST2103. Adjust the 1 KHz amplitude level fully clock wise.

Conclusion:
If the frequency of the VCO in the receiver clock regeneration circuit has been
correctly adjusted in that case the data in A/D converter Block of ST2103 is always
same as data in D/A converter Block of ST2104, also the output voltage of TP33 of
ST2104 should be same as the input voltage at TP10 of ST2103 for all DC input
levels.

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Questions:
1.

What do you understands by error check codes?

2.

List various types of error check codes?

3.

What are parity check codes?

4.

What is hamming codes?

5.

What do you understand by even and odd parity?

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Figure 1.1
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Experiment 2
Objective: Study of Analog to Digital Conversion
Equipment required:
1.

ST2103 trainer with power supply cord

2.

Oscilloscope with connecting probe

3.

Connection cords

Connection Diagram:

Figure 2.1

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Figure 2.2
Procedure:
A.

Initial set up for trainer ST2103:

Mode Switch Position

: FAST position

Function generator setting:

1.

DC l & DC 2 amplitude controls

: fully clockwise direction.

1 KHz & 2 KHz signal levels

: 10 V peak -peak.

Pseudo random sync code generator switch

: OFF position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 Position ('Off'

All switched faults

: OFF position.

Connect on ST2103 : as shown in figure 2.1

a.

DC l output to CH 0 input

b.

DC 2 output to CH 1 input

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2.

Turn On the power. With the help of digital voltmeter / oscilloscope, adjust
the DC l amplitude control until the DC 1 output measures 0V: The accuracy
should be within +/-20mV. Turn the DC 2 amplitude control, fully counter
clockwise.

3.

Observe the output on the A/D converter block LEDs (D0 to D6). The LEDs
represent the state of the binary PCM word allocated to the PAM sample being
processed.
An illuminated LED represent a '1' state, while non illuminated LED indicates a
'0' state. D6 is the MSB & D0 is the LSB. The LED output looks as follows.
D6

D5

D4

D3

D2

D1

D0

This output is the digital representation of 0V input to CH 0

4.

Adjust the DC1 amplitude control clockwise to increase the amplitude &
anticlockwise to decrease it. Try varying the DC input from + 5V to - 5V in
steps of 1V. Take care that the input value is within the specified range of +/20mV. Observe that the output for +5V is as follows :
D6

D5

D4

D3

D2

D1

D0

Where for the negative values it is less than 1000000 for -5V the output is as
follows
D6

D5

D4

D3

D2

D1

D0

This is obtained at the approximately full anti-clockwise position of the DC

Control.
5.

Turn the DC 1 control fully anti-clockwise and repeat the above procedure by
varying DC 2 control. Check that the digital code for the set voltage value is
identical to that of the DC 1 setting.
Once again take the precaution of maintaining the set input within +/- 20mV
range of the specified voltage.

6.

Switch 'Off' the trainer. Disconnect the DC 1 & DC 2 supply from CH 0 & CH
1. Connect ~1 KHz signal to CH 0 & 2 KHz signal to CH 1 input as shown in
figure 2.2.

7.

Trigger the dual trace oscilloscope externally by the CH 1 signal available at

TP12. Observe the signal at CH 0 & CH 1 sample output (TP5) with reference
to the SC Signal (TP7) on the second trace. Give a special attention to the phase
relation between the two signals.

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8.

Now connect the oscilloscope channel 1 to CH 1 sample (TP6) sketch the three
waveforms with utmost importance to the relationship between the three
waveforms.

9.

Connect oscilloscope channel 1 input to SC test points (TP7) & oscilloscope

channel 2 input to EC test point (TP8).
Observe the phase relation between the two SC & EC test point. Notice that EC
goes high at the end of conversion & remains latched until next SC Pulse.
Conclusion:
The proper selection of voltage as input gives the proper output in the form of
binary words.
Questions:

1.

Explain the operation of basic sample and hold circuit.

2.

Define following performance parameters of D/A converters:

a) Resolution
b) Accuracy
b) Conversion time

3.

State the advantages and applications of sample and hold circuits.

4.

Explain the following with reference of ADC:

a) Conversion time
b) Accuracy
c) Resolution time
d) Quantization time

5.

Define start of conversion and end of conversion.

6.

What are the types of ADC?

7.

What is the difference between direct ADC and integrating type ADC?

8.

Explain the function of the successive approximation ADC converter.

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Experiment 3
Objective : Study of Control Signals and their Timings
Equipment required:
1.

ST2103 trainer with power supply cord

2.

Oscilloscope with connecting probe

3.

Connection cords

Connection Diagram:

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Procedure:
A.

Initial set up for trainer ST2103:

Mode Switch Position

: FAST position

Function generator setting:

1.

2.

DC l & DC 2 amplitude controls

: fully clockwise direction.

1 KHz & 2 KHz signal levels

: 10 V peak -peak.

Pseudo random sync code generator switch

: OFF position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 Position ('Off'

All switched faults

: OFF position.

Make the following connections as shown in figure 3.1:

I.

DC 1

TO

CH 0

II.

DC 2

TO

CH 1

Turn On the power supply and oscilloscope.

Adjust the DC1 amplitude control such that the voltage measured at TP10 (CH
0) with the help of DMM / oscilloscope is + 3 Volts.
Adjust the DC 2 amplitude control so that the voltage at TP12 (CH 1) is 2 V.

3.

The LED outputs of A/D Converter & shift register are a combination of the two
input voltages. Also since the trainer is working in fast mode, it is impossible to
detect the code.

4.

As stated earlier, the two channels are sampled at different time. Approximately,
after 10 seconds, when the system has settled down to slow mode, observe the
LEDs of A/D converter Block. Notice that a particular combination of LEDs is
lit in the A/D converter Block for approximately 7 seconds.
These LEDs represent the latched output from the A/D Converter for every
sample of CH 0 & CH 1 Channels. Note the output of the A/D Converter,
Note: You may find the A/D Converter's output may not be identical every time
you switch the circuit from fast to slow mode for the same DC Control setting.
This is due to the slight change in voltage at Sample / Hold circuit at the time of
switching. However the change in code will only be 1 Bit.

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5.

The parallel data from the A/D Converter is then loaded in the shift register
which converts in serial output. Connect the oscilloscope at following points :
a)

Oscilloscope channel 1 to TX. clock output (TP3)

b)

Oscilloscope channel 2 to S/L test point (TP9)

c)

External trigger to TX. to output (TP4)

You may have to adjust the oscilloscope trigger levels to obtain a stable display.
6.

Observe the interdependence of S/L, TX clock output and the shift register
outputs as shown by their respective LEDs. Record the waveforms. The timing
diagram for the process is shown in figure 3.2.

Conclusion:
As the controlling signals are properly synchronized the output of the two input
waveforms are also synchronized.
Questions:
1.

What is control and timing signals?

2.

Which type of Analog to digital converter is generally preferred in

communication system?

3.

What is the function of shift register?

4.

What is the function of error check code generator?

5.

Why system clock is required for processing of signals?

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System Timing Diagram for ST2103

Figure 3.2

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Experiment 4
Objective: Study of Time Division Multiplexing
Equipment required:
1.

ST2103 trainer with power supply cord

2.

Oscilloscope with connecting probe

3.

Connection cords

Connection Diagram:

Procedure:
A.

Initial set up for trainer ST2103:

Mode Switch Position

: FAST position

Function generator setting:

DC l & DC 2 amplitude controls

: fully clockwise direction.

1 KHz & 2 KHz signal levels

: 10 V peak -peak.

Pseudo random sync code generator switch

: OFF position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 Position ('Off'

All switched faults

: OFF position.

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1.

Connect the 1 KHz output to CH 0

2.

Turn ON the power supply and oscilloscope. Check that the PAM output of 1
KHz sine wave is available at TP15 of the ST2103.

3.

Connect channel 1 of the oscilloscope to TP10 & channel 2 of the oscilloscope

to TP15. Observe the timing & phase relation between the sampling signal
TP10 & the sampled waveform at TP15.

4.

Turn 'Off' the power supply. Now connect also the 2 KHz supply to CH 1.

5.

Connect channel 1 of the oscilloscope to TP12 & channel 2 of the oscilloscope

to TP15.

6.

Observe & explain the timing relation between the signals at TP10, 5, 6, 12&15.

Conclusion:
By observing the two signals in a multiplexed form provides the actual waveforms
which are time multiplexed.
Questions:
1.

Define the term TDM?

2.

Draw the block diagram of Time division multiplexing.

3.

Why input and output clock pulses are kept synchronized?

4.

What do you understand by guard time?

5.

List advantages and disadvantages of TDM.

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Experiment 5
Objective: Study of Pseudo Random Sync Code Generator
Equipment required:
1.

ST2103 & ST 2104 trainer with power supply cord

2.

Oscilloscope with connecting probe

3.

Connection cords

Connection diagram:

Figure 5.1

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Figure 5.2
Procedure:
A.

Initial set up for trainer ST2103:

Mode Switch Position

: FAST position

Function generator setting:

B.

1.

DC l & DC 2 amplitude controls

: fully clockwise direction.

1 KHz & 2 KHz signal levels

: 10 V peak -peak.

Pseudo random sync code generator switch

: ON position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 Position ('Off'

All switched faults

: Off position.

Initial set up for trainer ST2104:

Mode Switch Position

: FAST position

Pseudo random sync code generator switch

: OFF position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 positions ('Off'

All switched faults

: Off position.

Pulse generator delay adjusts control

: fully clockwise position.

Make following connection on board of ST2103 :as shown in figure 5.1

1 KHz

To

CH 0 Input

2 KHz

To

CH 1 Input

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2.

Make the following connections between ST2103 & ST2104.

ST2103

ST2104

TX. Clock output TP3

RX clock input TP46

TX. To output TP4

RX sync input TP47

PCM output TP44

PCM input TP1

3.

Display channel CH 0 Input (TP10) on oscilloscope channel 1 & use it to

trigger the oscilloscope. Display the ST2103 PCM output (TP44) on channel 2
of the oscilloscope.

4.

Vary the amplitude of the 1 KHz & 2 KHz sine wave signal & note that the
transmitted data changes.

5.

Also observe the two input signals TP10 & TP12 of ST2103 with the received
sine wave samples TP32 & 35 of ST2104 and at the respective low pass filter
outputs CH 0 & CH 1 (TP33 & 36) of ST2104.

6.

Vary the amplitude of ~1 KHz & ~2 KHz signals at the ST2103. Observe how
the output at receiver changes. Set a value of 4Vpp for channel 0. Note what the
output voltage of the received signal is.

7.

Turn Off the power. Rearrange the connections between ST2103 & ST2104
as follows as shown in figure 5.2
ST2103

8.

ST2104

TX. Clock output

RX clock input

PCM output

PCM input

Connect
Channel 1 of the oscilloscope to TP12 on ST2103.
Channel 2 of the oscilloscope to TP36 on ST2104.

9.

Turn On the power and oscilloscope. Notice the waveforms & confirm that
they are different.

10.

Vary the setting of ~2 KHz signal & observe the waveform at TP36. Explain
the reason behind the mismatch.

11.

Turn 'Off' the power. Connect [Link] output from ST2103 to RX sync input on
ST2104.
Turn On the power. Now notice the two waveforms again. Do you notice any
change? Why it has happened?

12.

Now you must have observed the importance of synchronization. But now the
synchronization has been established because of the separate link between
ST2103 & ST2104.

13.

Turn 'Off' the power Remove the link between [Link] & [Link]. Turn On
the trainer. Observe the two mismatched waveforms. Now turn On the pseudo

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random sync code generator on ST2103. Do you notice any change in the
observed waveform at TP36 on ST2104.
14.

Turn the pseudo random sync code detector on ST2104 ON. Notice the changes
observed waveform at TP36 of ST2104.

15.

To be able to perceive the pattern of the sync code generated, connect the
oscilloscope probes to TP4 ([Link] output & TP42) (Pseudo random sync code
generator output).
Notice the sync coded output for a high level occurrence at the TX to output. If
necessary switch the two trainers to slow mode.

16.

Notice the sync Bit counter LED, in pseudo random sync code detector Block
of ST2104 is On in FAST Mode. This is an indication that the receiver has
identified the transmitted bit time 0 & is using it for all its timing operations.
This also confirms that the two are in 'Frame Synchronization'.
Observe the [Link] (TP4) output signal on ST2103 & [Link] (TP48) output
signal on ST2104. They should be identical when frame synchronization has
been achieved.

17.

Switch 'Off' the pseudo random sync code generator. Notice that the sync bit
counter LED goes 'Off' indicating that the synchronization has been lost. Notice
at the same time that the sync error counter led goes On. Note the LED
indication may be faint. There fore observe carefully. This goes to show that
synchronization has been lost.

Conclusion:
With the help of pseudo random sync code generator the signals transmitted are
received in secure fashion at the output port.
Questions:
1.

How PN sequence is generated?

2.

Draw the block diagram of PN sequence generator.

3.

Why Ex or gate is used to generate PN sequence?

4.

What do you understand by shift register?

5.

Explain the working principle of shift register.

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Experiment 6
Objective : Study of Three Modes of Transmission
Equipment required:
1.

ST2103 & ST2104 trainer with power supply cord

2.

Oscilloscope with connecting probe

3.

Connection cords

Procedure:
A.

Initial set up for trainer ST2103:

Mode Switch Position

: FAST position

Function generator setting:

B.

1.

DC l & DC 2 amplitude controls

: fully clockwise direction.

1 KHz & 2 KHz signal levels

: 10 V peak -peak.

Pseudo random sync code generator switch

: ON position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 Position ('Off'

All switched faults

: Off position.

Initial set up for trainer ST2104:

Mode Switch Position

: FAST position

Pseudo random sync code generator switch

: OFF position

Error check code selector switches A & B

Mode).

: A = 0 & B =0 positions ('Off'

All switched faults

: Off position.

Pulse generator delay adjusts control

: fully clockwise position.

Make connections as shown in figure 6.1.

a. Connection on ST2103 :
I. ~ KHz Signal to CH 0 Input.
II. ~2 KHz Signal to CH 1 Input.
b. Between ST2103 & ST2104
ST2103

2.

ST2104

TX. Clock output

RX. Clock input

[Link] output

RX sync input

PCM output

PCM data input

Turn On the power supply and oscilloscope. Observe that the 1 KHz sine

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wave input appears at TP10 (CH 0 Input) & 2 KHz sine wave input appears at
TP12 (CH 1 Input).
3.

Connect
Channel 1 of oscilloscope to CH 0 Input (TP10)
Channel 2 of oscilloscope to PCM output (TP44)
Trigger the oscilloscope with CH 0 input. Observe the two waveforms. Vary the
ST2103's ~1 KHZ and ~2 KHz controls (which vary the amplitude of the two
sine waves) and note how the transmitter data changes.

4.

Set the amplitude of each sine wave to 8Vpp.

Display CH 0 (TP33) & CH 1 (TP36) of ST2104 on two channels of the
oscilloscope. Notice that the two outputs are identical to that transmitter by the
transmitter. Observe the receiver channel output with the corresponding
transmitter channel input on a dual trace oscilloscope. The output may get
flattened at peaks if the input sinusoidal signal voltage exceeds 10Vpp. This is
because the input exceeds the dynamic range of the A/D Converter. Vary the
amplitude of the input signal observe that the same changes are reflected at the
receiver.

5.

Turn 'Off' the trainer. Make following connection on ST2103 :

a. DC.1 to CH 0
b. CH 0 to CH 1

6.

Turn On the power. Vary the DC.1 control. Observe on the oscilloscope at
TP10. The amplitude should vary between -5 to + 5V. Variation of the input
voltage from -5V to +5V will cause the output of A/D Converter to vary from
00 Hex to 7F Hex. The A/D converter 7 Bit word output can be monitored on
LEDs provided in the A/D converter block.
Observe that the D/A Converter LED contain the same data for a particular set
of input amplitude. Notice the output waveform at CH 0 (TP33) or CH 1 (TP36)
of ST2104.

7.

The sequence of operation on ST2103 is fully synchronized to the TX. Clock

signal. This clock signal can be monitored at TP3. Each clock cycle is known as
time slot. The operations of the trainer repeat after 15 time slots. These 15 time
slots are collectively called 'Timing Frame'. The start of the timing frame or Bit
0 is indicated by high level at [Link] output (TP4). The data appears at the
output logic block at the start of each time slot. The output logic block adds a
half time slot delay to it. Thus the output (TP44) of output logic block contains
transitions halfway through each time slot. The information appearing at the
middle of the time slots is as follows.
BIT 0: This carries the synchronization information (sync. code). The Pseudo
random sync code generator outputs a single bit in this time slot. Since the
length of the code is 15 bits, the Sync code repeats after 15 timing frames. At

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this instance the pseudo random sync code generator is 'Off', a '0' is transmitted
in this time slot.
BIT 1 to 7: These bits carry the 7 Bit data word of the last sample taken from
the channel o. Notice that the least significant bit (LSB) is transmitted first.
BIT 8 to 14: These bits carry the 7 bit data word of the last sample taken from
channel 1. In this case also the least significant bit is transmitted first.
Observe the PCM output (TP44) with respect to the input signal to output logic
block (TP43) & with TX. Clock signal (TP3).

Figure 6.1
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8.

As it has been discussed earlier, for correct operation the receiver needs to be
clocked" at the same rate as the transmitter & it should be able to decide which
time slot is for which information transmit TX clock & [Link] signals on
separate links. TX clock signals clocks the receiver at the same rate where as
the TX. TO signal helps the receiver to identify the time slot 0.

9.

The three wire connections can be reduced to two wires by developing the
ST2103's ability to transmit the synchronization information along the data.
Similarly, the receiver must be able to detect & distinguish these sync bits from
the normal information bits.
This ability is imparted by the Pseudo random sync code generator & detector
present on ST2103 & receiver trainer respectively. The pseudo random sync
code is a sequence of 15 bits generated by the pseudo random sync code
generator.
0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 .............................................................. Repeating.
One bit of this sequence is transmitted in every frame at time slot 0. The
receiver detects it & uses it to decide which time slot is for which frame.

10.

The above mode is termed as 'connecting Mode 2'. The ST2103 / Receiver can
be configured in this mode as shown in figure 6.2.
a. Switch the boards to FAST mode.
b. Remove the link connecting [Link] (TP 4) & RX sync (TP 47).
c. Switch On the pseudo random sync code generator on ST2103.
d. Switch On the pseudo random sync code detector on ST2104.
e. Connect DC 1 to CH 0 & CH 0 to CH 1

11.

Vary DC 1 and note that the LEDs on the A/D converter block on ST2103 &
D.A. converter of ST2104 always carries the same code.
Also observe that the sync bit counter led in the pseudo random sync code
detector block is On. This signifies that the receiver knows the transmitted
time slot & can identify them. We say that the receiver is 'Frame Synchronized'
to the transmitter. Once the transmitter & receiver is frame synchronized, the
[Link] & [Link] signals are identical. You can observe the two waveform at
TP4 of ST2103 & at TP48 of ST2104 respectively.

12.

Switch 'Off' the pseudo random sync code generator. Notice that the A/D
converter block output observed on LEDs is not similar to the D/ A Converter
Block input. We say that the receiver has lost the frame synchronization. The
Receiver indicates this by turning 'Off' the sync bit counter led in pseudo
random sync code detector block.

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Figure 6.2

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13.

If you desire to examine the timing of data flow & control signal in detail,
switch the ST2103 & receiver into slow mode.

14.

The number of connecting links can be reduced further to one by configuring

the ST2103 & receiver in connecting Mode 3. The only connecting link
between transmitter & receiver is the data/information link. The receiver
establishes the synchronization from pseudo random sync code transmitted
along with the P.C.M. data. In this case it has to regenerate the clock signal as
well. The receiver does this by on board phase locked loop circuit which
regenerates the clock from the transitions of the data bit who timing with
respect to the clock signals is fixed.

15.

Configure the ST2103 & receiver as shown in figure 6.3 and ensure the
following statements :
a. Both trainers are switched in FAST Mode.
b. Link between TX clock (TP3) & RX clock (TP46) has been removed.
c. PCM data input (TP1) on ST2104 is connected to the input (TP3) of phase
locked loop circuit on the same trainer.
d. The phase locked loop output (TP8) is connected to the RX clock input
(TP46) on the ST2104.

16.

Before operating in connecting Mode 3 it may be necessary to trim the voltage

controlled oscillator (VCO) frequency, so that the regenerated clock remains in
synchronization with the incoming data even when few transitions occur. (This
happens when there is a long stream of '0's to '1's in the. NRZ (L) waveform).
Follow the procedures given below to trim the VCO frequency:
a. Turn the DC1 control in the function generator block on ST2103 fully
clockwise.
b. Slowly, turn the VCO frequency adjust control on ST2104 until the sync bit
counter led in the pseudo random sync code detector Block turns On.
c. Repeat the above steps till position of the control is found such that the sync
bit counter led remains On for both fully clock wise & anticlockwise
positions of the DC1 Control.

17.

At the ST2103, remove the CH 0 & CH 1 inputs & connect.

a. ~ 1 k Signal to CH 0 input.
b. ~ 2 KHz Signal to CH 1 input.
Note: Turn 'Off' the power when new connections are made or disconnected.
Adjust the outputs of the two generators to 8Vpp by the amplitude controls
provided in the Function generator block. You can observe the two signals at
TP10 & 12).

18.

Observe the ST2104 analog outputs (TP33 & 36). Verify that the two outputs
are identical to that applied at the transmitter's inputs.

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19.

The trainers have on board error check generator & detector (on ST2103 &
ST2104 respectively). This provides an opportunity to detect & if possible to
correct the erroneous trainer data. The Error check code generator replaces some
least significant bits of the 7 Bit word with some error check bits. The following
error check options are available on board :

1.

'Off' : The error check generator is 'Off' when this mode is selected by switching
the A & B switches in the error check code generator block in ST2103 in A = 0
& B = 0 position.
No error check code is inserted in the 7 Bit word. The word format is
D6

D5

D3

D2

D1

D0

Where D6-D0 are the A/D Converters latched outputs.

2.

Even Parity: This option is selected by placing A & B switches in the error
check code generator block in ST2103. In A = 0 & B=1 position. The least
significant bit of the 7 bit word is replaced by a single parity bit.
The word format is :
D6

D5

D4

D3

D2

D1

C0

Where C0 is the parity check bit which is chosen such that the total no of '1's in
the 7 bit word are even. If the error check code detector in ST2104 is also
configured in this mode, it can detect the error in the transmitted data, but it
cannot tell which bit is in error. It indicates 'the error by switching On of the
Parity Error LED.
3.

Odd Parity: This option is selected by placing the A & B switches in the error
check generator block in A = l & B = 0 position. The least significant bit of the
7 - Bit word is replaced by a single parity bit.
The word format is.
D6

D5

D4

D3

D2

D1

C0

Where C0 is the parity check bit such that the total no of '1's in the 7 bit word
are odd.
If the error check code detector in ST2104 is also included in this mode, it can
detect the error in the transmitted data, but cannot tell which bit is in error. It
indicates the error by switching On of the parity error LED.
4.

Hamming Code: This option is selected when the A & B switches in the Error
check code generator on ST2103 are placed in A=1 & B=1 position.
In this case the three check bits replace the three least significant bits of the
7 bit word. The word format is :
D6

D5

D4

D3

C2

C1

C0

Where C2, C1 & C0 are the Hamming check bits. If the Error Check Code
Detector in ST2104 is switched into same .mode, it can detect the error & even
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connect the erroneous transmitted data bit (only single). It indicates the
erroneous bit by lighting the corresponding LED in hamming code error block.
Illustration of various check codes are given in steps 22nd to 29th:
22.

Connect the ST2104's CH 0 (TP33) & CH 1 output (TP36) to the two channels
of the oscilloscope. Now introduce the switched fault '2' in the trainer system by
switching On the pole 2 of switched faults Block. This fault forces the D6 bit
(MSB) of the transmitted 7 bit word to be always '1' even when there must have
been a '0'. Notice the distortion in the output in the output sine waves at the
ST2104's CH 0 (TP33) & CH 1 (TP36) outputs.

23.

Switch 'Off' the fault. Introduce even parity error check code option on both the
trainers by switching the A & B switches in the corresponding block to A=0 &
B=1 position.

24.

Observe the two output waveforms at ST2104's CH 0 (TP33) & CH 1 (TP36)

outputs are distortion less & also observe the LEDs in the error check code
detector block are 'Off'.

25.

Switch On fault '2' again.

Observe that the parity error indicator LED in error check code detector glows
i.e. the receiver has detected the error in transmitted data but is not in a position
to locate which bit is in error. Therefore the output at CH 0 & CH 1 on ST2104
still remains distorted.

26.

You can carry on the same experiment by selecting the odd parity option. You
will get the same result as the earlier ones. Note switch 'Off' the fault prior to
selecting the Error check code option.

27.

Switch ''Off'' the fault. Select the hamming code option by placing the A & B
switches in the corresponding block to A = 1 & B = 1 position.

28.

Switch On fault '2'

Observe that the D6 LED marked in error check code detector's hamming code
error bit glows. Since its 3 bit hamming code, it can detect as well as correct
one bit error in a sample. It reveals the erroneous bit in the data format by
lighting the corresponding LED (D6 in the present case). Notice, now that the
outputs at CH 0 & CH 1 on ST2104 are now distortion less. This is because the
erroneous bit has even been corrected by the receiver.

29.

You can induce any switched fault /faults in the ST2103 & ST2104 trainer to
investigate the effect of particular faults on the whole system. This also allows
you the opportunity to practice & test your skills in fault detection trouble shooting. The list of various faults that can be induced in the system is given in
this manual.

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Figure 6.3
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Questions:
1.

What are the advantages of using digital transmission?

2.

How many types of digital transmission are there?

3.

Which type of transmission is best for long distance communication?

4.

What are the advantages of serial transmission?

5.

What are the advantages of parallel transmission?

6.

How many modes are there for digital transmission?

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Experiment 7
Objective: Computer Communication using RS232 interface via ST2103 & ST2104
Equipment required:
1.

ST2103 & ST2104 trainer with power supply cord

2.

Computer system with software

3.

Connection cords

4.

RS232 cable

There are two channels provided on ST2103 & ST2104. It utilizes these two channels
to communicate between two computers, thus forming a full duplex link. It will need
the following :
System:
Microsoft Windows 95, 98, or above
Software:
Supplied with the trainer in CD
Procedure:
1.

Keep PCs on either side of the ST2103 & ST2104.

2.

Connect the RS232 cable to the serial port of the computer and the other end to
ST2103 & ST2104 as shown in figure 7.1.

3.

Make the interconnections between ST2103 & ST2104 as shown in the figure
7.1. (Before connecting perform the experiment no.6 in mode 3).

4.

Install the Software on both the PCs.

5.

After establishing a connection, select the com port in the "COM Port" window,
and select Baud rate (same on both PCs).

6.

Follow this procedure for both the computers.

7.

Switch On the trainers.

8.

Now type a message in the message window of PC1 and click send, you will
see the message in receiver window of PC2 and in transmit window of PC1.

9.

If you send a message from PC2 you will receive the message in the receiver
window of PC1 and in transmitter window of PC2.

10.

If you disconnect any of the transmitting or receiving wire, you will see that the
data transmission has failed.

11.

You can reduce the baud rate of both PCs and you will observe that the transmit
rate is lower.

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Figure 7.1
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Questions:
1.

What do you understand by RS 232?

2.

What RS stand for?

3.

What is dead zone in RS 232?

4.

For which type of communication RS232 is used?

5.

What are the specifications of RS 232?

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Experiment 8
Objective: Multi point to multi point communication using RS232 interface via
ST2103 & ST2104
Equipment required:
1.

ST2103 & ST2104 trainer with power supply cord

2.

Computer system with software

3.

Connection cords

4.

RS232 cable

There are two channels provided on ST2103 & ST2104. It utilizes these two links to
communicate from two PCs on one end to two PCs on other end. The two PCs
connected to ST2103 will act as transmitter, and those connected to ST2104 will act
as receiver. This will be a one way communication. It will need the following:
System:
Microsoft Windows 95, 98, or above
Software:
Supplied with the trainer in CD.
Procedure:
1.

Keep the PCs on either sides of the ST2103 & ST2104.

2.

Connect the RS232 cable to the serial port of the computer and the other end to
ST2103 & ST2104 as shown in figure 8.1.

3.

Make the interconnections between ST2103 & ST2104 as shown in the figure
8.1 (Before connecting perform the experiment no.6 in mode 3).

4.

Install the software provided with the trainer in all the four PCs.

5.

Run the software in all the PCs and select the respective COM ports and the
same baud rate in all the PCs.

6.

Switch On the trainers.

7.

Now the data transmitted by PC1 and PC2 will be multiplexed, Pulse code
modulated and transmitted via single wire and then, demodulateddemultiplexed and received by PC 3 and PC4 respectively.

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Figure 8.1

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Questions:
1.

What you understand by D type connector?

2.

Which type of signals are used by RS232 interface?

3.

Why signals used are in form of hand shake?

4.

What is the difference between D-9 and D-25 connector?

5.

Draw the pin out diagram for RS232 interface?

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Experiment 9
Objective: Point to multi point communication using RS232 interface via ST2103 &
ST2104
Equipment required:
1.

ST2103 & ST2104 trainer with power supply cord

2.

Computer system with software

3.

Connection cords

4.

RS232 cable

There are two channels provided on ST2103 & ST2104. It utilizes these two links to
communicate from one PC to the two other PC's on the other end. The PC on the
transmitter side will act as master and the PCs on receiver side will act as slaves. This
will also be a one way communication.
System :
Microsoft Windows 95, 98, or above
Software :
Supplied with the trainer in CD
Procedure :
1.

Keep one PC to the left of ST2103 (master) & two PCs to ST2104 (slaves) as
shown in figure 9.1.

2.

Connect the RS232 cable to the serial port of the computer and the other end to
ST2103 & ST2104 as shown in the figure 9.1.

3.

Make the interconnections between ST2103 & ST2104 as shown.

4.

Install the software provided with the trainer in all the three PCs. Run the
software and select the respective COM ports and same BAUD rate in all the
PCs.

5.

Switch On the trainers.

6.

Now the data or instructions transmitted by the master will be received by the
two slaves.

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Figure 9.1

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Switched Faults
1.

Transmitter Switched Faults:

Following faults can be induced in the ST2103 to study their effects on the system &
to practice fault-diagnosis techniques.
Switched Fault 1 :
Switching ON of this fault causes the A/D Converter's D6 Output to be always '0',
irrespective of the applied analog input. The fault occurs before error check code
generator & hence cannot be detected by the receivers error detection correction
logic. Hence the output of the receiver is not always a true representation of the
applied analog input at the transmitter.
Switched Fault 2 :
The switching On of this fault cause D6 bit of the P.C.M. output of the transmitter to
be always '1' irrespective of the connect D6 bit level. This fault is induced after the
error check code generator block & hence can be detected & in case of hamming code
selected, can be corrected also if the same mode is selected on error detection &
correction logic on receiver trainer also. This fault can be used to study the utility of
the error check codes in case of bit corruption in the P.C.M. data along the
transmission path.
Switched Fault 3 :
This fault causes the error check code generator to treat the A/D converter's D5 output
to be always high irrespective of the actual D5 bit in P.C.M. data transmitted. This
fault has no effect when none of the error check code option is selected the receiver
may wrongly decide that the P.C.M. data has a fault.
In case of hamming code, the receiver may try to correct the wrongly diagnosed 'error'
thus distorting the output in this process.
Switched Fault 4 :
This fault affects the pseudo random sync code generator. It causes the generator to
generator a sequence which is not Pseudo Random in Nature. Hence if the receiver is
relying on pseudo random sync code for synchronization as in connecting Modes 2 &
3, the receiver loses frame synchronization. This distorts the receiver's output.
2.

Receiver Switched Faults

The Following faults can be induced in the ST2104 receiver trainer to study their
effects on the system & to practice fault diagnosis techniques
Switched Fault 1 :
This fault breaks the loop between phase locked loop output & loop filter's input on
ST2104 receiver trainer. Thus induction of this fault cause the malfunctioning of
phase locked loop circuit. Hence the receiver doesn't clock into synchronization in
connecting Mode 3. Remember PLL circuit is used to extract clock information in
connecting Mode 3.
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Switched Fault 2 :
This fault affects the functioning of ST2104's pseudo random sync code detector.
When this fault is induced, the receiver cannot detect the transmitted pseudo random
sync code. Hence in connecting Mode 2 & 3 in which the ST2104 depends on sync
code detection for frame synchronization this fault cause the receiver to continuously
try to resynchronize but to do so every time.
Switched Fault 3 :
This fault affects the ST2104's error detection/correction logic when the hamming
option is selected. It causes an error in C1 to be indicated when the received data and
check bits are correct. If the received data actually contains an incorrect bit, the
receiver may decide that the wrong bit is in error, and if that bit is a data bit, try to
correct it. The effect of this fault is detailed in the table below.
Bit Received

Indicated

Bit

In Error

Error

Corrected

None

C1

None

C0

D3

D3

C1

C1

None

C2

D5

D5

D3

D3

D3

D4

D6

D6

D5

D5

D5

D6

D6

D6

Switched Fault 4 :
This fault open circuits the ST2104's channel 1 sample & hold amplifier. This causes
the receiver's channel 1 output CH 1 (TP36) to drift down to 10V supply.

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Setting Up the Receiver's Clock Regeneration Circuit

The receiver's clock regeneration circuit contains a preset labeled VCO frequency
adjusts. The preset adjusts the free-running frequency of the phase-locked loop's
voltage controlled oscillator (VCO). Before connection mode 3 is used, it may be
necessary to trim the frequency of the VCO to ensure that the generated clock signal
remains synchronized to the incoming data, even when the transitions in the data are
only occasional.
The procedure for making this adjustment in ST2104 check regeneration circuit is as
follows:
1.

Set up the system in connection mode 3.

2.

Ensure in ST2104 circuits that :

a. All switched faults are 'Off'.
b. The error check code selector switched are in the '00' ('Off') position
c. FAST Mode is selected.

3.

Switch On the ST2103's pseudo random sync code generator block and the
ST2104's pseudo random sync code detector block.

4.

Ensure 'that the ST2104's pulse generator delay control is in the fully clockwise
position.

5.

Make the following links at the ST2103 :

a. DC 1 to CH 0 input.
b. CH 0 input to CH 1 input

6.

Switch on the power to the boards.

7.

Turn the DC 1 preset, on ST2103 fully clock wise.

8.

Turn the VCO frequency adjust preset, on ST2104 until a position it is found
where the sync bit counter LED, in the sync code detector block of ST2104 is
On.

9.

Turn the DC 1 preset fully counter clockwise and check that the sync bit counter
LED is still On If the LED switches to 'Off', re trim the VCO frequency adjust
preset until the LED stays on for both extreme positions of the DC 1 preset.
After following this procedure, the receiver clock regeneration circuit should be
able to synchronize on any transmitted data stream, providing that there are at
least occasional rising transitions at PCM data output.

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Frequency Asked Question

1.

How PAM signal is converted into PCM signal?

Ans: A PAM system can be converted into a PCM system by adding a suitable
analogue-to-digital (A/D) converter at the source and a digital-to-analogue (D/A)
converter at the destination.
2.

List the steps to get the PCM signals?

Ans: In PCM, modulation process is executed in three steps:

3.

Sampling

Quantizing

Coding

What is Quantization?

Ans: In quantization the levels are assigned a binary codeword. All sample values
falling between two quantization levels are considered to be located at the centre of
the quantization interval. In this manner the quantization process introduces a certain
amount of error or distortion into the signal samples.
4.

What is Quantization noise?

Ans: During the quantization process introduces a certain amount of error or

distortion into the signal samples. This error known as quantization noise
5.

How Quantization noise can be minimized?

Ans: Quantization noise can be minimized by establishing a large number of small

quantization intervals. Of course, as the number of quantization intervals increase, so
must the number or bits increase to uniquely identify the quantization intervals.
6.

Draw the block diagram of Bit step Analog to digital converter?

Ans: The block diagram of Bit step Analog to digital converter is as follows:

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7.

List the pulse modulation techniques and explain them in short?

1.

Pulse Amplitude Modulation (PAM) :

In pulse amplitude modulation system the amplitude of the pulse is varied
in accordance with the instantaneous level of the modulating signal. Now
days, the PAM system is not generally used, but it forms the first stage of
the other types of pulse modulation.

2.

Pulse Width Modulation (PWM) :

In PWM system the width of the pulse is varied in accordance with the
instantaneous level of the modulating signal.

3.

Pulse Position Modulation (PPM) :

In PPM System, the position of the pulse relative to the zero reference
level is varied in accordance with the instantaneous level of the
modulating signal.

4.

Pulse Code Modulation (PCM) :

In PCM System the amplitude of the sampled waveform at definite time
intervals is represented as a binary code. The first three techniques of the
above described systems are not truly digital but in fact are analog in
nature. The very fact that the variation of a particular pulse parameter is
continuous rather than being in the discrete steps makes the system analog
in nature.

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8.

What are the benefits of using TDM?

Ans: Benefits of TDM are as follows:.

1.
2.

3.

9.

TDM is all about cost: fewer wires and simpler receivers are used to transmit
data from multiple sources to multiple destinations.
TDM also uses less bandwidth than Frequency-Division Multiplexing (FDM)
signals, unless the bit rate is increased, which will subsequently increase the
necessary bandwidth of the transmission.
An asset of TDM is its flexibility. The scheme allows for variation in the
number of signals being sent along the line, and constantly adjusts the time
intervals to make optimum use of the available bandwidth. The Internet is a
classic example of a communications network in which the volume of traffic can
change drastically from hour to hour.
What is Pseudo-random Noise (PN) sequence?

Ans: A Pseudo-random Noise (PN) sequence is a sequence of binary numbers, e.g.

1, which appears to be random; but is in fact perfectly deterministic. The sequence
appears to be random in the sense that the binary values and groups or runs of the
same binary value occur in the sequence in the same proportion they would if the
sequence were being generated based on a fair "coin tossing" experiment.
10.

What are the uses of Pseudo-random Noise (PN) sequence?

Ans: They can be used to logically isolate users on the same frequency channel. They
can also be used to perform scrambling as well as spreading and dispreading
functions.
11.

Draw the block diagram and explain how PN sequence can be generated?

Ans: A PN generator is typically made of N cascaded flip-flop circuits and a specially

selected feedback arrangement as shown below.

Figure
The flip-flop circuits when used in the cascaded manner is called a shift register, since
each clock pulse applied to the flip-flops causes the contents of each flip-flop to be
shifted to the right. The feedback connections provide the input to the left-most flipflop. With N binary stages, the largest number of different patterns the shift register
can have is 2N. However, the all-binary-zero state is not allowed because it would
cause all remaining states of the shift register and its outputs to be binary zero. The
all-binary-ones state does not cause a similar problem of repeated binary ones

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provided the number of flip-flops input to the module 2 adder is even. The period of
the PN sequence is therefore 2N-1, but IS-95 introduces an extra binary zero to
achieve a period of 2N, where N equals 15.
12.

Write the advantages and disadvantages of Digital modulation system?

Ans: Advantages of digital modulation system:

a. Noise & Distortion :

Pulse which becomes distorted by the addition of noise can be reshaped

at the regenerators installed at pre-determined intervals along the link.
Thus within certain threshold the error will not creep in.

b. Multiplexing :

The information once sampled & coded can be multiplexed in time

domain, i.e. the coded information from different sources can be sent,
one after another, if it can be re-routed to the corresponding channels at
the receiver.

The information is coded in binary form, the source of information /

sample, becomes unimportant. Therefore many different sources such as
telephone, facsimile, telegraphy and video cap are transmitted over same
channel & circuitry.

c. Store & forward (S & F) facility :

That information which has been binary coded in digital format can be
easily stored in the computer or memory elements, & information can be
forwarded at the desired time. It is required at the time of channel
congestion. The message can be stored in memory. Once the channel
becomes clear, the message can be forwarded to the called party.

d. Encryption & security :

The digital devices today are capable of high grade encryption. The
data can not be correctly interpreted if the receiver has no proper
decoder. Hence the digital communication can be highly secured.

e. Power requirement :

To transmit the digital data over the same channel requires less signal
power than that would be required for same performance of the
receiver for analog systems.

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Disadvantages of digital modulation communication system:

a. Band with requirement :
The digital communication systems need very large bandwidth as compared
to its analog counter part.
b. Complexity :
The digital transmitter & receivers is the complex due to the requirement of
highly reliable timing information. This adds to complexity as well as to the
cost of the communications system. With the advent of new technology, the
digital circuits / IC's are becoming more and cheaper still prices are slightly
at the higher side. But the advantage offered by the digital techniques far
over weighs this consideration.
13.

How many methods are there to transmit the data from one place to other?

Ans: There are two methods for sending digital data over a distance, namely
a. Parallel transmission
b. Serial transmission
14.

Describe the use of serial and parallel transmission?

Ans: In short distance communication like inside terminal equipment or two

computer terminals located near each other, the signals are passed in parallel, format
over parallel wires. Thus the signal in the form of a word is passed. This mode is
faster.
For long distances, even more than few feets, this is uneconomical & inefficient way
of transmission. It is a wasteful of transmission media as each bit requires a separate
link. Therefore the digital signals are transmitted serially over a single link.
15.

What do you mean by sampling?

Ans: To convert continuous time signal to discrete time signal, a process is used
called as sampling.
16.

What is sampling theorem?

Ans: The Sampling Theorem states that a signal can be exactly reproduced if it is
sampled at a frequency Fs, where Fs is greater than twice the maximum frequency
Fmax in the signal.

Fs > 2 Fmax
17.

What is Nyquist frequency?

Ans: The frequency 2 Fmax is called the Nyquist sampling rate. Half of this value,
Fmax, is sometimes called the Nyquist frequency.

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18.

List different sampling techniques?

Ans: There are three types of sampling, which are as follows:

1. Ideal sampling or Instantaneous sampling or Impulse sampling
2. Natural sampling
3. Flat top sampling
19.

What is under sampling?

Ans: When the sampling rate is lower than or equal to the Nyquist rate, a condition
defined as under sampling, it is impossible to rebuild the original signal according to
the sampling theorem.
20.

What do you mean by aliasing?

Ans: Aliasing is the presence of unwanted components in the reconstructed signal.

These components were not present when the original signal was sampled. In
addition, some of the frequencies in the original signal may be lost in the
reconstructed signal. Aliasing occurs because signal frequencies can overlap if the
sampling frequency is too low. As a result, the higher frequency components roll into
the reconstructed signal and cause distortion of the signal Frequencies "fold" around
half the sampling frequency. This type of signal distortion is called aliasing.
21.

Explain the process of sample and hold?

Ans: In electronics, a sample and hold circuit is used to interface real-world signals,
by changing analogue signals to a subsequent system. The purpose of this circuit is to
hold the analogue value steady for a short time while the converter or other following
system performs some operation that takes a little time.
Sampling mode:
In this mode, the switch is in the closed position and the capacitor charges to the
instantaneous input voltage.
Hold mode:
In this mode, the switch is in the open position. The capacitor is now disconnected
from the input. As there is no path for the capacitor to discharge, it will hold the
voltage on it just before opening the switch. The capacitor will hold this voltage till
the next sampling instant.
22.

How aliasing is removed?

Ans: Aliasing is removed by simply filtering out all the high frequency components
before sampling.

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23.

List methods to avoid aliasing?

Ans: To avoid the aliasing there are two approaches:

1. To raise the sampling frequency to satisfy the sampling theorem,
2. The other is to filter off the unnecessary high-frequency component from the
continuous-time signal. We limit the signal frequency by an effective low
pass filter, called anti aliasing pre filter, so that the remained highest
frequency is less than half of the intended sampling rate. If the filter is not
perfect we must give some allowance.
24.

What are active and passive filter?

Ans: Filter is a network designed to pass signals having frequencies within certain
bands (called pass bands) with little attenuation, but greatly attenuates signals within
other bands (called attenuation bands or stop bands).
A filter network containing no source of power is termed passive, and one containing
one or more power sources is known as an active filter network.

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Warranty
1.

We guarantee this product against all manufacturing defects for 24 months from
the date of sale by us or through our dealers. Consumables like dry cell etc. are
not covered under warranty.

2.

The guarantee will become void, if

a)

The product is not operated as per the instruction given in the Learning
Material

b)

The agreed payment terms and other conditions of sale are not followed.

c)

The customer resells the instrument to another party.

d)

Any attempt is made to service and modify the instrument.

3.

The non-working of the product is to be communicated to us immediately giving

full details of the complaints and defects noticed specifically mentioning the
type, serial number of the product and date of purchase etc.

4.

The repair work will be carried out, provided the product is dispatched securely
packed and insured. The transportation charges shall be borne by the customer.

List of Accessories
1.

Patch Cord 8"..........................................................................................2 Nos.

2.

Patch Cord 16"........................................................................................2 Nos.

3.

Patch Cord 20"........................................................................................1 No.

4.

Mains Cord .............................................................................................1 No.

5.

RS232 Cable ..........................................................................................2 Nos.

6.

Learning Material (CD) .............................................................................1 No.

7.

CD (Demo VCD) Supplied with Full Set ...................................................1 No.

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