This syllabus outlines a course on computer architecture and parallel processing over 5 units spanning 45 periods. Unit I introduces fundamental computer design concepts, parallel and scalable architectures, and performance measures. Unit II covers instruction-level parallelism, pipelining, and techniques for overcoming data hazards through dynamic scheduling and speculation. Unit III focuses on memory hierarchy design including caches, optimizations, and virtual memory. Unit IV discusses symmetric and distributed shared memory architectures, cache coherence issues, and interconnection networks. Unit V examines software and hardware multithreading, single-chip multiprocessor and multicore architectures. References for further reading are also provided.
This syllabus outlines a course on computer architecture and parallel processing over 5 units spanning 45 periods. Unit I introduces fundamental computer design concepts, parallel and scalable architectures, and performance measures. Unit II covers instruction-level parallelism, pipelining, and techniques for overcoming data hazards through dynamic scheduling and speculation. Unit III focuses on memory hierarchy design including caches, optimizations, and virtual memory. Unit IV discusses symmetric and distributed shared memory architectures, cache coherence issues, and interconnection networks. Unit V examines software and hardware multithreading, single-chip multiprocessor and multicore architectures. References for further reading are also provided.
Original Description:
Computer Architecture and Parallel Processing, Syllabus, Anna University, Chennai, Regulation 2013
This syllabus outlines a course on computer architecture and parallel processing over 5 units spanning 45 periods. Unit I introduces fundamental computer design concepts, parallel and scalable architectures, and performance measures. Unit II covers instruction-level parallelism, pipelining, and techniques for overcoming data hazards through dynamic scheduling and speculation. Unit III focuses on memory hierarchy design including caches, optimizations, and virtual memory. Unit IV discusses symmetric and distributed shared memory architectures, cache coherence issues, and interconnection networks. Unit V examines software and hardware multithreading, single-chip multiprocessor and multicore architectures. References for further reading are also provided.
This syllabus outlines a course on computer architecture and parallel processing over 5 units spanning 45 periods. Unit I introduces fundamental computer design concepts, parallel and scalable architectures, and performance measures. Unit II covers instruction-level parallelism, pipelining, and techniques for overcoming data hazards through dynamic scheduling and speculation. Unit III focuses on memory hierarchy design including caches, optimizations, and virtual memory. Unit IV discusses symmetric and distributed shared memory architectures, cache coherence issues, and interconnection networks. Unit V examines software and hardware multithreading, single-chip multiprocessor and multicore architectures. References for further reading are also provided.
