Open AccessArticle

A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application

Xianfeng Que

Jun Li

and

Yanjie Wang

^2,*

School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510641, China

School of Microelectronics, South China University of Technology, Guangzhou 510641, China

Author to whom correspondence should be addressed.

Electronics 2024, 13(10), 1882; https://doi.org/10.3390/electronics13101882

Submission received: 4 April 2024 / Revised: 7 May 2024 / Accepted: 9 May 2024 / Published: 11 May 2024

(This article belongs to the Special Issue Advanced Wireless Technologies for Next-G Networks: Antennas, Circuits, and Systems)

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Abstract

This article presents a new broadband three-way series Doherty power amplifier (DPA) topology, which enables a broadband output power back-off (OBO) efficiency enhancement of up to 10 dB or higher. The proposed DPA topology achieves Doherty load modulation and three-way power combining through a transformer, which requires only a low coupling factor, thus facilitating its implementation in double-sided PCBs or monolithic microwave integrated circuit (MMIC) processes. The design equations for the proposed DPA topology are proposed and analyzed in detail. A proof-of-concept PA at the 2.1–2.8 GHz band using commercial GaN transistors was designed and fabricated to validate the proposed concept. Within the operating frequency band, it achieves a saturated output power (

P_{sat}

) of 44.5–46.5 dBm with a peak drain efficiency (DE) of 60–72%, and 43–52% DE at 10 dB OBO. Moreover, under a 20 MHz long-term evolution (LTE)-modulated signal, the PA demonstrates a 36.8–37.5 dBm average output power (

P_{avg}

) and 47–53% average drain efficiency (

{DE}_{avg}

). Notably, the adjacent channel leakage ratio (ACLR) is as low as −35–−28.2 dBc without any digital predistortion (DPD).

Keywords:

5G; high efficiency; series Doherty power amplifier (DPA); three-way; wideband

1. Introduction

Demands for elevated data rates and expanded capacity mandate the incorporation of intricate signal modulation techniques in fifth-generation (5G) communication systems, including high-order quadrature amplitude modulation (QAM), massive multiple-input multiple-output (MIMO), and orthogonal frequency-division multiplexing (OFDM) [1,2]. However, these techniques pose challenges, such as a high peak-to-average power ratio (PAPR) of up to 9–12 dB, coupled with the necessity for a high degree of linearity in communication systems [3,4,5]. Consequently, power amplifiers (PAs) must operate at deep output power back-off (OBO), resulting in a diminished average efficiency [6]. Given that PAs are typically the most power-consuming components in wireless communication systems, their inefficiency engenders significant concerns such as constrained battery life and heightened heat dissipation [7]. This underscores the pressing need to augment the efficiency of PAs operating at deep OBO.

The Doherty power amplifier (DPA) is the most widely used architecture for improving the OBO efficiency of PAs due to its intrinsic linearity and low baseband overhead [8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23]. A DPA typically comprises a Main PA and an Auxiliary PA, with its OBO efficiency enhanced through active load modulation between these two sub-PAs. At low power levels with OBO above 6 dB, the Auxiliary PA is off, while the Main PA has a high load impedance and maintains a high efficiency owing to the large drain voltage swing. At high power levels, the Auxiliary PA turns on, modulating the load impedance of the Main PA from high impedance to optimal impedance (

R_{opt}

), thereby ensuring maximum output power.

DPA comprises two fundamental topologies: parallel and series, as depicted in Figure 1 [8]. In the parallel topology, the Main PA is connected in parallel with the Auxiliary PA via a

λ / 4

transmission line (TL), resulting in a load impedance of

R_{opt} / 2

. In the series topology, the Auxiliary PA is connected in series with the Main PA through a

λ / 4

TL and a transformer, resulting in a load impedance of

2 \times

R_{opt}

The parallel topology has been the prevalent choice for reported DPAs due to its ease of implementation [15,16,17,18,19]. Nevertheless, a two-way parallel DPA is restricted to providing efficiency improvements within 6 dB OBO, which is insufficient for the 5G NR waveform. To extend the OBO range, N-way (where N = 3 or 4) parallel DPAs have been developed, achieving a deep OBO range of up to 9–12 dB [20,21,22,23]. However, N-way parallel DPAs typically have a larger impedance transformation ratio (ITR) due to the need for impedance matching between

R_{opt} / N

and 50

Ω

at the combining node, resulting in a reduced bandwidth and efficiency, as well as significant area overhead [9,20]. This issue becomes more pronounced in high-power PA designs, where

R_{opt}

commonly falls below 30

Ω

[15].

Recently, a Doherty-like topology, known as the load-modulated balanced amplifier (LMBA), has been proposed and developed for broadband active load modulation [24,25,26,27,28,29,30]. However, LMBAs are prone to experiencing significant nonlinear gain compression during load modulation, which adversely impacts their linearity [26].

For high-power DPA designs, the series topology may offer more advantages. First, the ITR between

N \times R_{opt}

and 50

Ω

is substantially lower than that of the parallel topology when

R_{opt}

is small [9]. Second, the elimination of the

λ / 4

TL after the Main PA enhances both the bandwidth and the linearity [8]. Nonetheless, while the series DPA topology has been successfully implemented in CMOS processes [8,9,10,11,12,13,14], its application in printed circuit board (PCB) or monolithic microwave integrated circuit (MMIC) processes is still rarely reported. This is primarily attributed to the constraints of these processes, which generally contain only two or three metal layers (including the ground layer), posing significant challenges in the fabrication of transformers with high coupling factors.

To address this issue, this paper presents a novel three-way series Doherty topology, which employs a transformer with a low coupling factor to achieve Doherty load modulation and efficient three-way power combining. The low-coupling transformer can be readily implemented in PCB and MMIC processes. Furthermore, by arranging the power ratio of the Main and Auxiliary PAs, this topology ensures a deep OBO efficiency enhancement with a low ITR, thus facilitating a high efficiency and a broad bandwidth. For the experimental validation, a prototype PA is designed, fabricated, and measured, showing good agreement between the simulated and measured results.

2. Analysis of Proposed Three-Way DPA

The conventional series DPA depicted in Figure 1b typically employs a single transformer for two-way power combining, providing an OBO range of 6 dB. However, the transformers utilized in such topology generally require high coupling factors exceeding 0.7 [12], which is difficult to achieve in double-sided PCB and MMIC processes [31,32]. Consequently, implementing conventional series Doherty PAs in these processes presents notable challenges.

In contrast, the novel series Doherty topology introduced in this paper contains a Main PA and two Auxiliary PAs, employing a single transformer along with two

λ / 4

transmission lines (TLs) to realize three-way power combining, as depicted in Figure 2a. This topology not only enables higher output power but also extends the OBO range to 10 dB or deeper by arranging the power ratio between the Main PA and the Auxiliary PAs. Moreover, the load impedance seen by the Main PA at low input power remains constant at

R_{L}

due to the connection setup of the Main PA and the load

R_{L}

at opposite ends of the secondary coil, and is unaffected by the transformer’s turns ratio. Meanwhile, the impedance seen by the Auxiliary PAs is determined by both the turns ratio k and the characteristic impedance

Z_{0}

of the

λ / 4

TL. Therefore, the transformer in the proposed topology can exhibit a low coupling factor, which is advantageous for implementing this topology in PCB and MMIC processes. A detailed analysis of this topology is presented in this section.

2.1. Load Modulation Analysis

In the proposed Doherty topology, the Aux.1 and Aux.2 PAs are biased at the same gate voltage, both operating at Class-C, while the Main PA is biased at Class-AB. The active load modulation can be analyzed by examining the three-port Z-matrix (1) of the proposed topology, where ports 1 and 2 are connected to the Aux.1 PA and Aux.2 PA, respectively, and port 3 is linked to the Main PA.

I_{1} = j I_{A}

I_{2} = - j I_{A}

, and

I_{3} = I_{M}

[\begin{matrix} V_{1} \\ V_{2} \\ V_{3} \end{matrix}] = [\begin{matrix} 0 & 0 & j k Z_{0} \\ 0 & 0 & - j k Z_{0} \\ j k Z_{0} & - j k Z_{0} & R_{L} \end{matrix}] [\begin{matrix} I_{1} \\ I_{2} \\ I_{3} \end{matrix}]

(1)

\{\begin{matrix} Z_{1} = \frac{V_{1}}{I_{1}} = \frac{k Z_{0} I_{M}}{I_{A}} \\ Z_{2} = \frac{V_{2}}{I_{2}} = \frac{k Z_{0} I_{M}}{I_{A}} \\ Z_{3} = \frac{V_{3}}{I_{3}} = R_{L} - \frac{2 k Z_{0} I_{A}}{I_{M}} \end{matrix}

(2)

It is indicated in (2) that the two Auxiliary PAs have identical load impedances, determined by the current ratio

I_{M} / I_{A}

Z_{0}

, and k. At low input power, only the Main PA is active, while the Auxiliary PAs are off (i.e.,

I_{A} = 0

). Therefore, the Main PA sees a load impedance of

R_{L}

, while the Auxiliary PAs see an infinite impedance (∞). At high input power, the Auxiliary PAs turn on and deliver currents to the output network. In this phase, the impedances of the Main PA and Auxiliary PAs decrease as

I_{A}

increases. At saturation, all three sub-PAs obtain their optimal impedances, guaranteeing maximum output power.

The output powers of each sub-PA are derived from (2), expressed as follows:

\{\begin{matrix} P_{A} = \frac{1}{2} I_{A}^{2} Z_{1} = \frac{1}{2} k Z_{0} I_{M} I_{A} \\ P_{M} = \frac{1}{2} I_{M}^{2} Z_{3} = \frac{1}{2} I_{M}^{2} (R_{L} - \frac{2 k Z_{0} I_{A}}{I_{M}}) \end{matrix}

(3)

The calculation formula for the OBO range is given in (4) by combining (2) and (3).

O B O = \frac{P_{M}}{P_{M} + 2 P_{A}} \times \frac{Z_{3}}{R_{L}} = \frac{I_{M}^{2} {(R_{L} - \frac{2 k Z_{0} I_{A}}{I_{M}})}^{2}}{I_{M}^{2} R_{L} (R_{L} - \frac{2 k Z_{0} I_{A}}{I_{M}}) + 2 k Z_{0} R_{L} I_{M} I_{A}}

(4)

Typically, the saturated output current of a transistor exhibits direct proportionality to its saturated output power (

P_{s a t}

) and inverse proportionality to

R_{o p t}

. Let

α

I_{M, s a t} / I_{A, s a t}

. Then, the following formulas can be derived:

P_{A, s a t} = \frac{1}{α} P_{M, s a t}

(5)

R_{o p t, A} = α R_{o p t, M}

(6)

Substituting (5) and (6) into (2) and (3) gives the following:

\{\begin{matrix} Z_{1, s a t} = α k Z_{0} = α R_{o p t, M} \\ Z_{2, s a t} = α k Z_{0} = α R_{o p t, M} \\ Z_{3, s a t} = k Z_{0} = R_{o p t, M} \\ Z_{3, l o w} = R_{L} = \frac{R_{o p t, M} (α + 2)}{α} \end{matrix}

(7)

O B O = {(\frac{α}{α + 2})}^{2}

(8)

Some important conclusions can be drawn from (7) and (8). First, with given values of

α

and

R_{o p t, M}

, the load modulation behavior of the proposed Doherty topology can be determined. Second, the product of k and

Z_{0}

equals

R_{o p t, M}

. By selecting a higher

Z_{0}

value, the k value can be reduced, thereby avoiding the need for a high-coupling transformer. Third, the OBO range is solely determined by

α

. A smaller

α

results in a deeper OBO range, and the ITR of the Main PA increases correspondingly, as shown in Figure 3. The efficiency curves for different

α

values are illustrated in Figure 4.

It is assumed that the three sub-PAs are of identical sizes, i.e.,

α = 1

. It is indicated from (7) that

Z_{1, s a t} = Z_{2, s a t} = Z_{3, s a t} = k Z_{0} = R_{o p t}

and

Z_{3, O B O} = R_{L} = 3 k Z_{0} = 3 R_{o p t}

. If

R_{o p t}

is less than 25

Ω

, the ITR between

R_{L}

and 50

Ω

is very small, thus facilitating wide bandwidth and high efficiency. The OBO range is calculated from (8) as 9.54 dB, and the corresponding efficiency curve versus OBO is illustrated in Figure 4. The load modulations of the Main PA and Auxiliary PAs are presented in Figure 5.

2.2. Implementation

The ideal transformer in the proposed Doherty topology is realized using a pair of coupled inductors in practice, as described in Figure 2b. It is well known that the equivalent circuit of a pair of coupled inductors comprises an ideal transformer, a magnetizing inductor, and a leakage inductor. In this design, the magnetizing and leakage inductors are resonated out by adding the capacitors

C_{p}

and

C_{s}

, respectively. The formulas for calculating these parameters are provided in (9).

\{\begin{matrix} k = k_{m} \sqrt{\frac{L_{s}}{L_{p}}} \\ C_{p} = \frac{1}{{(2 π f_{0})}^{2} L_{p}} \\ C_{s} = \frac{1}{{(2 π f_{0})}^{2} (1 - k^{2}) L_{s}} \end{matrix}

(9)

Furthermore, to save the circuit area, the

λ / 4

TL can be replaced by a shorter TL with an electrical length of

θ

and a characteristic impedance of

Z_{02}

, along with two shunt capacitors

C_{p}

, as shown in Figure 2c. The calculation formulas for

Z_{02}

θ

, and

C_{02}

are given in (10), revealing that choosing a lower

θ

leads to higher values of both

Z_{02}

and

C_{02}

. Additionally,

C_{02}

can be integrated with

C_{p}

to obtain a capacitance value of

C_{p} + C_{02} / 2

, as depicted in Figure 2d.

\{\begin{matrix} Z_{02} = \frac{Z_{0}}{sin θ} \\ C_{02} = \frac{cos θ}{2 π f_{0} Z_{0}} \end{matrix}

(10)

3. Design Procedure

To verify the proposed theory, a prototype DPA is designed on a Rogers 4350B substrate (

ε_{r} = 3.66

and

tan δ = 0.004

) with a thickness of 0.762 mm. The target frequency range is from 2.2 to 2.8 GHz to cover the 5G NR bands for cellular communication systems, including n40 of 2300–2400 MHz, n41 of 2496–2690 MHz, and n7 of 2620–2690 MHz. Circuit and electromagnetic (EM) simulations are conducted using the PathWave Advanced Design System (ADS) and the ANSYS High-Frequency Structure Simulator (HFSS), respectively. For ease of design, the three sub-PAs use the same packaged 10 W GaN HEMTs from MACOM (CGH40010F), i.e.,

α = 1

. The Main PA is biased at Class-AB with a gate voltage (

V_{G}

) of −2.7 V and a supply voltage of 28 V, and the quiescent drain current is set at 200 mA. The Auxiliary PA is biased at Class-C with a gate voltage (

V_{G}

) of −5.4 V, and is supplied with a slightly higher drain voltage of 32 V. This compensates for the weaker output power capability inherent in the Class-C mode [15], thereby ensuring that the

P_{s a t}

of the Auxiliary PA is close to that of the Main PA. The

R_{o p t}

and output capacitance (

C_{o u t}

) of the HEMTs are extracted from a load-pull simulation, as shown in Figure 6. For maximum output power and optimal bandwidth, the load impedance is selected as 15.9 + j8.1

Ω

at a center frequency of 2.5 GHz, with its conjugate value corresponding to 20

Ω

R_{o p t}

in parallel with 1.6 pF

C_{o u t}

The design of the output network is a crucial task in this work. The transformer features a uniplanar structure, with both the primary and secondary coils comprising a single turn. The width of the coils is designed to be 1 mm to guarantee adequate power-carrying capacity. According to the IPC-2221A standard [33], a 1 mm wide microstrip line carrying a current of 1.5–5.5 A experiences a temperature rise of 10–100 °C. For a 50

Ω

load, the current corresponds to an output power of 112.5–1512.5 W. In this design, with a maximum output power of 46.5 dBm (i.e., 44.7 W), employing a line width of 1 mm ensures that the temperature rise remains below 10 °C. The layout of the output network is illustrated in Figure 7a. The values of

L_{p}

L_{s}

, and

k_{m}

are extracted from the EM simulation results, as shown in Figure 7b.

L_{p}

and

L_{s}

are both approximately 7 nH, and

k_{m}

is 0.4. The other parameters are subsequently calculated from (9) and displayed in Figure 7b. The physical lengths of the two TLs are 13 mm, corresponding to an electrical length of 65°, with a characteristic impedance

Z_{02}

and an associated shunt capacitance

C_{02}

calculated as 55

Ω

and 0.54 pF, respectively, using (10). Additionally, a

λ / 4

TL with a characteristic impedance of 55

Ω

is positioned after the combining node, serving as a post-matching network to transform

R_{L}

to 50

Ω

. It is crucial to note that the ITR between

R_{L}

and 50

Ω

is merely 1.2 in this topology. In comparison, the parallel Doherty counterpart has a much higher ITR of 7.5.

The equivalent circuit of the ideal coupled inductor is illustrated in Figure 2b. However, practical coupled coils exhibit parasitic capacitors

C_{m}

between the primary and secondary coils, as well as parasitic capacitors

C_{g p}

and

C_{g s}

between the coils and the ground [34], as depicted in Figure 8a. These parasitic capacitors cause deviations in the performance of the coupled inductor from the ideal model. The values of

C_{m}

C_{g p}

, and

C_{g s}

in the proposed output network are extracted from the EM simulation and presented in Figure 8b. Among them, the values of

C_{g p}

and

C_{g s}

are relatively small and can be neglected, while the value of

C_{m}

is 0.19 pF. To resonate out

C_{m}

, two 20 nH packaged inductors are inserted between the primary and secondary coils, bringing the performance of the coupled coils closer to that of the ideal coupled inductors.

The three-way Doherty behavior of the output network is simulated by modeling the three sub-PAs as ideal current sources, with the results depicted in Figure 9. At the peak output power, the output network provides nearly identical impedances of approximately 20

Ω

(

R_{o p t}

) for all three sub-PAs. When both Auxiliary PAs are in the off state, the Main PA sees a load impedance of 59.2

Ω

(2.96×

R_{o p t}

). The simulation results confirm that the output network achieves the required Doherty active load modulation across a wide bandwidth, attributed to its low ITR.

The input feed comprises a 2:1 unequal Wilkinson divider with an isolation resistor of 75

Ω

and a lumped LC balun, splitting the input RF power to three paths with equal amplitude and proper phase difference. A lumped isolation circuit is inserted between the balanced ports of the lumped balun to enhance isolation between the two Auxiliary paths, thereby improving the circuit stability [31], as shown in Figure 10. The input matching network (IMN) is designed to maximize the bandwidth and minimize the input reflection coefficient. Given that all three sub-PAs employ identical transistors, the same IMNs are deployed for them to simplify the design process. Additionally, a 10

Ω

resistor is included in the IMN to guarantee the PA’s stability.

A schematic of the entire PA design is illustrated in Figure 10, including the dimensions of the TLs and the values of the lumped components.

The post-layout electromagnetic (EM) simulation of the PA is conducted using ANSYS HFSS 2021 R2. The large-signal simulation results from 2.1 to 2.8 GHz are shown in Figure 11. The proposed PA achieves 63.9–73.1% drain efficiency (DE) at saturation, and 43–51.7% DE at 10 dB OBO. The saturated output power (

P_{s a t}

) reaches 46.7 dBm and remains above 44.8 dBm across the entire frequency range.

To better illustrate the load modulation of the proposed PA, Figure 12 presents the simulated load impedance at the drain of the Main PA, and the output currents of the Main, Aux.1, and Aux.2 PAs versus the output power at 2.5 GHz. The output current of the Main PA increases monotonically as the input power increases, while the Aux.1 and Aux.2 PAs remain inactive at low input power and become activated around the 10 dB OBO point. With the activation of the Auxiliary PAs, the load impedance of the Main PA decreases from 59.6

Ω

(2.98

\times R_{o p t}

) to 20.2

Ω

(1.01

\times R_{o p t}

). At the saturation power, the three sub-PAs exhibit nearly identical output currents, delivering a maximum output power. The simulated load modulation aligns well with the values calculated using (5)–(8), verifying the accuracy of the theoretical analysis.

4. Measurement Results

Figure 13a presents a photograph of the fabricated DPA, which occupies an area of

66 mm \times 65 mm

. The DPA was mounted on a heat sink to dissipate heat during operation. Continuous-wave (CW) and modulated signal measurements were conducted. The supply voltages for the Main and Auxiliary PAs were set to 28 V and 32 V, respectively. The gate bias voltage for the Main PA was set to −2.7 V to obtain a quiescent current of 200 mA. The gate bias voltage for the Auxiliary PAs was −5.4 V.

As illustrated in Figure 13b, a signal generator was used to generate the requisite input signal, and a broadband linear driver was positioned between the signal generator and the fabricated DPA to amplify the input power. A spectrum analyzer was utilized to monitor the output signal, with a 30 dB attenuator inserted preceding it. Several DC voltage suppliers were employed to provide the DC voltages.

The measured small-signal S-parameters of the fabricated DPA are depicted in Figure 14, which includes a comparison between the measured and simulated results. The PA achieves a wide 3 dB gain bandwidth (

B W_{3 - d B}

) of 1.14 GHz, spanning from 1.89 to 3.03 GHz, with a peak gain of 9.4 dB at 2.05 GHz. Across the frequencies within the 3 dB bandwidth, the input is well matched with

S_{11}

below −8.5 dB.

The large-signal CW results measured in the frequency range of 2.1–2.8 GHz are shown in Figure 15, and the measured power-added efficiency (PAE) is presented in Figure 16. The large-signal performance versus frequency is summarized in Figure 17. Within the frequencies of 2.1–2.8 GHz, the PA exhibits a high

P_{s a t}

, ranging from 44.5 to 46.5 dBm. The DE at saturation is in the range of 60–72%. In the deep OBO region of up to 10 dB, the PA still maintains a high measured DE from 43% to 52%, and the corresponding PAE is in the range of 36–44%. The measured results show good agreement with the simulated results, thereby validating the proposed concept.

The linearity of the PA is evaluated using a 20 MHz long-term evolution (LTE) signal with 8.5 dB PAPR. The measured output signal spectra without any digital predistortion (DPD) at several representative frequencies are presented in Figure 18. The measured modulation results over the whole operating frequency band are illustrated in Figure 19. The PA achieves a high average drain efficiency (

{DE}_{avg}

) of 47–53% at an average output power (

P_{avg}

) of 36.8–37.5 dBm. Notably, the PA exhibits a low adjacent channel leakage ratio (ACLR) ranging from −35 to −28.2 dBc without any DPD, which is attributable to the intrinsic high linearity of the series Doherty topology [8].

The CW and modulation performance comparisons of the proposed PA with prior-art three-way parallel DPAs and LMBAs are presented in Table 1 and Table 2, respectively. Owing to the low ITR of the proposed three-way series Doherty topology, this DPA demonstrates a high

P_{s a t}

of 44.5–46.5 dBm and a high efficiency of 60–72%/43–52% at saturation/10 dB OBO across a broad bandwidth of 2.1–2.8 GHz, corresponding to a fractional bandwidth (FBW) of 28.6%. Notably, as can be seen from Table 2, this DPA exhibits a better linearity with a lower ACLR of −35–−28.2 dBc without any DPD. This can be attributed to the elimination of the

λ

/4 TL after the Main PA in the series Doherty topology [8]. Conversely, three-way LMBAs are prone to significant nonlinear gain compression during load modulation, resulting in a compromised linearity [24,25,26]. In summary, the proposed DPA exhibits outstanding performance in terms of bandwidth, efficiency, and linearity.

5. Conclusions

In this article, a new broadband three-way series Doherty topology is proposed. This topology enables a broadband output power back-off (OBO) efficiency enhancement of up to 10 dB or higher by arranging the power ratio of the Main PA and the Auxiliary PAs. A transformer is employed for Doherty load modulation and three-way power combining, and it requires only a low coupling factor. This characteristic facilitates the implementation of the proposed topology in double-sided PCBs or MMIC processes. The theory and design methodology of the proposed topology are discussed in detail. Experimental validation through the fabrication of a prototype DPA demonstrates its capability to achieve a high efficiency, wide bandwidth, and deep OBO range for both CW and modulated signal measurements. In addition, it is noteworthy that the PA achieves an ACLR of as low as −35 to −28.2 dBc without DPD, which can be attributed to the intrinsic high linearity of the series Doherty topology.

Author Contributions

Conceptualization, X.Q. and Y.W.; methodology, X.Q.; software, X.Q.; validation, X.Q., J.L. and Y.W.; formal analysis, X.Q.; investigation, X.Q.; resources, X.Q.; data curation, X.Q.; writing—original draft preparation, X.Q.; writing—review and editing, Y.W.; visualization, X.Q.; supervision, Y.W.; project administration, Y.W.; funding acquisition, Y.W. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the Fundamental Research Funds for the Central Universities under Grant No. 2020ZYGXZR067.

Data Availability Statement

The data that support the findings of this study are available from the corresponding author, Yanjie Wang, upon reasonable request.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. (a) Parallel Doherty topology. (b) Series Doherty topology.

Figure 2. (a) Proposed three-way Doherty topology. (b) Realization of the transformer using coupled inductors. (c) Shortening of the

λ / 4

TL. (d) Integrating

C_{02}

with

C_{p}

Figure 2. (a) Proposed three-way Doherty topology. (b) Realization of the transformer using coupled inductors. (c) Shortening of the

λ / 4

TL. (d) Integrating

C_{02}

with

C_{p}

Figure 3. Normalized impedance (

R_{L} / Z_{3, s a t}

) and OBO range under various

α

values.

Figure 3. Normalized impedance (

R_{L} / Z_{3, s a t}

) and OBO range under various

α

values.

Figure 4. Efficiency versus OBO under various

α

values.

Figure 4. Efficiency versus OBO under various

α

values.

Figure 5. Load modulations of the Main PA and Auxiliary PAs under

α = 1

Figure 5. Load modulations of the Main PA and Auxiliary PAs under

α = 1

Figure 6. Optimal load impedance with maximum output power obtained from load-pull simulation.

Figure 7. (a) Layout of the output network. (b) EM simulation and other parameters of the output network.

Figure 8. (a) Practical coupled coils model containing parasitic capacitors

C_{m}

C_{g p}

, and

C_{g s}

. (b) Values of the parasitic capacitors and resonant inductors in the proposed output network.

Figure 8. (a) Practical coupled coils model containing parasitic capacitors

C_{m}

C_{g p}

, and

C_{g s}

. (b) Values of the parasitic capacitors and resonant inductors in the proposed output network.

Figure 9. (a) Load impedances of the Auxiliary PAs at saturation. (b) Load impedances of the Main PA at saturation and 9.5 dB OBO.

Figure 10. Schematic of the designed DPA. Transmission line width and length (W/L) are given in millimeters.

Figure 11. Simulated drain efficiency and gain versus output power within the frequency range of 2.1–2.8 GHz.

Figure 12. Simulated load impedance at the drain of the Main PA and output currents of the Main, Aux.1, and Aux.2 PAs versus output power at 2.5 GHz.

Figure 13. (a) Photograph of the fabricated PA. (b) Measurement setup.

Figure 14. Measured and simulated S-parameters of the proposed PA.

Figure 15. Measured drain efficiency and gain versus output power within the frequency range of 2.1–2.8 GHz.

Figure 16. Measured PAE versus output power within the frequency range of 2.1–2.8 GHz.

Figure 17. Measured CW results of the proposed PA.

Figure 18. Output spectra of 20 MHz LTE signal with 8.5 dB PAPR at (a) 2.4 GHz and (b) 2.7 GHz without DPD.

Figure 19. Measured modulation results of the proposed PA.

Table 1. CW performance comparison of the proposed PA with prior-art three-way load modulation PAs.

Ref.	Architecture	Freq. (GHz)	FBW (%)	Gain (dB)	$P_{sat}$ (dBm)	${DE@P}_{sat}$ (%)	OBO (dB)	DE@OBO (%)
This work	three-way series DPA	2.1–2.8	28.6	8.2–9.3	44.5–46.5	60–72	10	43–52
[21]	three-way parallel DPA	2.0–2.6	26	8–12	43.6–45.4	53–76	8	41–48
[22]	three-way parallel DPA	2.04–2.24	9.3	8	43.7–45.3	50–68	10	29–56
[23]	reflective-type DPA	2.1–3.0	35	7.5–11	46.6–49	48–58	19/9	33–50
[24]	SLMBA ^a	3.05–3.55	15.2	9.5–10.3	42.3–43.7	61–75	10	43–51
[25]	pseudo-LMBA	1.6–2.0	22.2	8.5–9.7	43.4–44	65–75	10	49–62

^a SLMBA: sequential load-modulated balanced power amplifier.

Table 2. Modulation performance comparison of the proposed PA with prior-art three-way load modulation PAs.

Ref.	Freq. (GHz)	Modulation	PAPR (dB)	$P_{avg}$ (dBm)	${DE}_{avg}$ (%)	${ACLR}^{b}$ (dBc)
This work	2.1–2.8	20 MHz LTE	8.5	36.8–37.5	47–53	−35–−28.2
[21]	2.3	20 MHz LTE	8	36.6	46	−29
[22]	2.14	20 MHz LTE	8.5	36.8	56.6	−28.6
[23]	2.1–3.0	20 MHz LTE	9	40	45–52	−27–−23
[24]	3.05–3.55	40 MHz LTE	8	35.5	57.8	−26
[25]	1.6–2.0	20 MHz LTE	10.32	33.6–34.5	42.8–54.6	−30.76–−23.5

^b without DPD.

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Que, X.; Li, J.; Wang, Y. A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application. Electronics 2024, 13, 1882. https://doi.org/10.3390/electronics13101882

AMA Style

Que X, Li J, Wang Y. A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application. Electronics. 2024; 13(10):1882. https://doi.org/10.3390/electronics13101882

Chicago/Turabian Style

Que, Xianfeng, Jun Li, and Yanjie Wang. 2024. "A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application" Electronics 13, no. 10: 1882. https://doi.org/10.3390/electronics13101882

APA Style

Que, X., Li, J., & Wang, Y. (2024). A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application. Electronics, 13(10), 1882. https://doi.org/10.3390/electronics13101882

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A Broadband Three-Way Series Doherty Power Amplifier with Deep Power Back-Off Efficiency Enhancement for 5G Application

Abstract

1. Introduction

2. Analysis of Proposed Three-Way DPA

2.1. Load Modulation Analysis

2.2. Implementation

3. Design Procedure

4. Measurement Results

5. Conclusions

Author Contributions

Funding

Data Availability Statement

Conflicts of Interest

References

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